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检索条件"任意字段=PDSE 2000: International Symposium on Software Engineering for Parallel and Distributed Systems"

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Semantics driven dynamic partial-order reduction of MPI-based parallel programs

Semantics driven dynamic partial-order reduction of MPI-base...

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2007 ACM international symposium on software Testing and Analysis, ISSTA'07 and PADTAD-V Workshop

作者： Palmer, Robert Gopalakrishnan, Ganesh Kirby, Robert M. School of Computing University of Utah Salt Lake City UT 84112 United States

ISBN: (纸本)159593748X

Most distributed parallel programs in the high performance computing (HPC) arena are written using the MPI library. There is growing interest in using model checking for debugging these MPI programs. In this context, partial-order reduction has considerable potential for containing state explosion, given the distributed memory nature of MPI programs. This potential is largely unmet. In this paper, we first define the formal semantics for a non-trivial subset of MPI. We then prove independence theorems based on theformal semantics, paving the way to a semantically clear and general partial-order reduction approach for MPI. Our work describes, for the first time, the exact dependencies between MPI non-blocking send operations and their tests for completion, namely wait and test. We also offer a cleaner solution than in previous works for MPI wildcard receives,a proper handling of which requires knowledge of the future course of computations. We show that Flanagan and Godefroid's dynamic patial-order reduction algorithm offers a natural way to handle the need for future information. Our initial experimental results are encouraging. Copyright 2007 ACM.

关键词： parallel processing systems

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Client-side implementation of dynamic asynchronous invocations for Web services

Client-side implementation of dynamic asynchronous invocatio...

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21st international parallel and distributed Processing symposium, IPDPS 2007

作者： Tretola, Giancarlo Zimeo, Eugenio University of Sannio Dept. of Engineering Benevento 82100 Italy University of Sannio Research Centre on Software Technology Benevento 82100 Italy

ISBN: (纸本)1424409101

Web Services are becoming more and more fundamental building blocks of Web-based distributed applications and a core technology for Grid systems. Due to their flexibility, Web Services easily combine, in a common and coherent framework, ubiquitous computing with heterogeneous applications composed of different kinds of resources and, typically distributed in many organizations. We expect that this technology will follow the same evolution paths that have characterized other technologies so far, with some specificity due to the openness and size of the application context. In this connection, optimizations tied to invocations and workflows are assuming a primary role in Web Services research. The synchronous request/reply nature of the most diffused underling protocol (HTTP) introduces several restrictions in many application scenarios. On the other hand, asynchronous interactions are allowed by using message oriented middleware platforms, like JMS, which are typically harder to handle than object- and process-oriented middleware. In this paper, we propose a first implementation of a module that allows for dynamic Web Services invocations, which, on the basis of metadata added to WSDL, is able to select the most appropriate invocation technique for calling a Web Services operation. © 2007 IEEE.

关键词： Web services

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Using an interactive software environment for the parallelization of real-world scientific applications

Using an interactive software environment for the paralleliz...

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Joint Meeting of the international symposium on distributed Computing and Applications to Business, engineering and Science/international Conference on parallel Algorithms and Computing Evironments

作者： Ierotheou, C. S. Jin, H. Matthews, G. Johnson, S. P. Hood, R. Leggett, P. F. Univ Greenwich Parallel Proc Res Grp London SE10 9LS England NASA Ames Res Ctr Adv Supercomp Div Moffett Field CA 94035 USA

The parallelization of real-world compute intensive Fortran application codes is generally not a trivial task. If the time to complete the parallelization is to be significantly reduced then an environment is needed that will assist the programmer in the various tasks of code parallelization. In this paper the authors present a code parallelization environment where a number of tools that address the main tasks such as code parallelization, debugging and optimization are available. The ParaWise and CAPO parallelization tools are discussed which enable the near automatic parallelization of real-world scientific application codes for shared and distributed memory-based parallel systems. As user involvement in the parallelization process can introduce errors, a relative debugging tool (P2d2) is also available and can be used to perform nearly automatic relative debugging of a program that has been parallelized using the tools. A high quality interprocedural dependence analysis as well as usertool interaction are also highlighted and are vital to the generation of efficient parallel code and in the optimization of the backtracking and speculation process used in relative debugging. Results of benchmark and real-world application codes parallelized are presented and show the benefits of using the environment.

关键词： iterative parallelization software tools and environment OpenMP message passing compiler directives

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Architectural considerations for efficient software execution on parallel microprocessors

Architectural considerations for efficient software executio...

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21st international parallel and distributed Processing symposium, IPDPS 2007

作者： Vadlamani, Srinivas Jenks, Stephen Dept. of Electrical Engineering and Computer Science University of California Irvine CA United States

ISBN: (纸本)1424409101

Chip Multiprocessors (CMPs) and Simultaneous Multithreading (SMT) processors provide high performance but put more pressure on the memory interface than their single-thread counterparts. The "memory wall" problem is exacerbated, by multiple threads sharing a memory interface, and will get worse as more cores are added. Therefore, communications between cores, using shared caches or fast interconnects between private caches, are needed to keep the CPUs busy without burdening the memory interface. Multiple CMP systems add another dimension to this challenging problem, as the communication mechanism is no longer uniform. To parallelize data-intensive applications for high performance on these systems, one must explore a number of execution behaviors in a complex architecture-dependent exercise that entails identifying key components of the communication subsystem and understanding their behavior under varying workloads. As part of ongoing research into efficient program execution models for parallel microprocessors, we have developed a tool to evaluate the performance of the storage controllers at different levels of the memory hierarchy under varying workloads and measure cache coherence overhead. The tool allows exploration of architectural features of real processors that affect the performance of several parallel execution approaches. Here, we demonstrate its use by evaluating two of our parallel programming models that employ architecture-specific optimizations and compare them to a conventional model for several applications on parallel microprocessors. © 2007 IEEE.

关键词： Microprocessor chips

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A debugger for flow graph based parallel applications

A debugger for flow graph based parallel applications

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2007 ACM international symposium on software Testing and Analysis, ISSTA'07 and PADTAD-V Workshop

作者： Al-Shabibi, Ali Gerlach, Sebastian Hersch, Roger D. Schaeli, Basile School of Computer and Communication Sciences CH-1015 Lausanne Switzerland

ISBN: (纸本)159593748X

Flow graphs provide an explicit description of the parallelization of an application by mapping vertices onto serial computations and edges onto message transfers. We present the design and implementation of a debugger for the flow graph based Dynamic parallel Schedules (DPS) parallelization framework. We use the flow graph to provide both a high level and detailed picture of the current state of the application execution. We describe how reordering incoming messages enables testing for the presence of message races while debugging a parallel application. The knowledge about causal dependencies between messages enables tracking messages and computations along individual branches of the flow graph. In addition to common features such as restricting the analysis to a subset of threads or processes and attaching sequential debuggers to running processes, the proposed debugger also provides support for message alterations and for message content dependent breakpoints. Copyright 2007 ACM.

关键词： parallel processing systems

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High performance distributed lock management services using network-based remote atomic operations 07

High performance distributed lock management services using ...

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7th IEEE international symposium on Cluster Computing and the Grid

作者： Narravula, S. Mamidala, A. Vishnu, A. Vaidyanathan, K. Panda, D. K. Ohio State Univ Columbus OH 43210 USA

ISBN: (纸本)9780769528335

Recently there has been a massive increase in computing requirements for parallel applications. These parallel applications and supporting cluster services often need to share system-wide resources. The coordination of these applications is typically managed by a distributed lock manager. The performance of the lock manager is extremely critical for application performance. Researchers have shown that the use of two sided communication protocols, like TCP/IP (used by current generation lock managers), can have significant impact on the scalability of distributed lock managers. in addition, existing one-sided communication based locking designs support locking in exclusive access mode only and can pose significant scalability limitations on applications that need both shared and exclusive access modes like cooperative/file-system caching. Hence the utility of these existing designs in high performance scenarios can be limited. In this paper we present a novel protocol, for distributed locking services, utilizing the advanced network-level one-sided atomic operations provided by InfiniBand. Our approach augments existing approaches by eliminating the need for two sided communication protocols in the critical locking path. Further we also demonstrate that our approach provides significantly higher performance in scenarios needing both shared and exclusive mode access to resources. Our experimental results show 39% improvement in basic locking latencies over traditional send/receive based implementations. Further we also observe a significant (upto 317% for 16 nodes) improvement over existing RDMA based distributed queuing schemes for shared mode locking scenarios.

关键词： Concurrent computing Application software distributed computing Scalability Computer architecture Computer network management engineering management Computer science Computer networks High performance computing

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A comprehensive analysis of openmp applications on dual-core intel xeon SMPs

A comprehensive analysis of openmp applications on dual-core...

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21st international parallel and distributed Processing symposium, IPDPS 2007

作者： Grant, Ryan E. Afsahi, Ahmad Department of Electrical and Computer Engineering Queen's University Kingston Ont. K7L 3N6 Canada

ISBN: (纸本)1424409101

Hybrid chip multithreaded SMPs present new challenges as well as new opportunities to maximize performance. Our intention is to discover the optimal operating configuration of such systems for scientific applications and to identify the shared resources that might become a bottleneck to performance under the different hardware configurations. This knowledge will be useful to the research community in developing software techniques to improve the performance of shared memory programs on modern multi-core multiprocessors. In this paper, we study a two-way dual-core Hyper-Threaded (HT) Intel Xeon SMP server under single program and multi-program multithreaded workloads using the NAS OpenMP benchmark suite. Our performance results indicate that in the single-program case, the CMP-based SMP and CMT-based SMP configurations have the highest average speedup across all of the applications. The most efficient architecture is a single HT-enabled dual-core processor that is almost comparable to the performance of a 2-way dual-core HT-disabled system. © 2007 IEEE.

关键词： Microprocessor chips

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Testing patterns for software transactional memory engines

Testing patterns for software transactional memory engines

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2007 ACM international symposium on software Testing and Analysis, ISSTA'07 and PADTAD-V Workshop

作者： Lourenço, JoĄo Cunha, Gonçalo CITI Departamento de Informática Universidade Nova de Lisboa Portugal

ISBN: (纸本)159593748X

The emergence of multi-core processors is promoting the use of concurrency and multithreading. To raise the abstraction level of synchronization constructs is fundamental to ease the development of concurrent software, and software Transactional Memory (STM) is a good approach towards such goal. However, execution environment issues such as the processor instruction set, caching policy, and memory model, may have strong influence upon the reliability of STM engines. This paper addresses the testing of STM engines aiming at improving their reliability and independence from execution environment. From our experience with porting and extending a specific STM engine, we report on some of the bugs found and synthesize some testing patterns that proved to be useful at testing STM engines. Copyright 2007 ACM.

关键词： Multitasking

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Pseudo trust: Zero-knowledge based authentication in anonymous peer-to-peer protocols

Pseudo trust: Zero-knowledge based authentication in anonymo...

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21st international parallel and distributed Processing symposium, IPDPS 2007

作者： Lu, Li Han, Jinsong Hu, Lei Huai, Jinpeng Liu, Yunhao Ni, Lionel M. State Key Lab. of Information Security Graduate School Chinese Academy of Sciences Beijing China Dept. of Computer Science and Engineering Hong Kong University of Science and Technology Kowloon Hong Kong School of Computer Science Beihang University Beijing China State Key Lab. of Software Developing Environment Beihang University Beijing China

ISBN: (纸本)1424409101

Most of the current trust models in peer-to-peer (P2P) systems are identity based, which means that in order for one peer to trust another, it needs to know the other peer's identity. Hence, there exists an inherent tradeoff between trust and anonymity. To the best of our knowledge, there is currently no P2P protocol that provides complete mutual anonymity as well as authentication and trust management. We propose a zero-knowledge authentication scheme called Pseudo Trust (PT), where each peer, instead of using its real identity, generates an unforgeable and verifiable pseudonym using a one-way hash function. A novel authentication scheme based on Zero-Knowledge Proof is designed so peers can be authenticated without leaking any sensitive information. With the help of PT, most existing identity-based trust management schemes become applicable in mutual anonymous P2P systems. We analyze the levels of security and anonymity in PT, and evaluate its performance using trace-driven simulations and a prototype implementation. The strengths of Pseudo Trust include the lack of need for a centralized trusted party or CA, high scalability and security, low traffic and cryptography processing overheads, and man-in-middle attack resistance. We aim for the Pseudo Trust design to be included in the P2P trust and anonymity context. © 2007 IEEE.

关键词： distributed computer systems

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The Next Generation software Workshop - IPDPS'07

The Next Generation Software Workshop - IPDPS'07

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international symposium on parallel and distributed Processing (IPDPS)

作者： Frederica Darema Computer and Information Science and Engineering Directorate National Science Foundation Arlington VA USA

This workshop provides a forum for an overview, project presentations, and discussion of the research fostered and funded initially by the NSF next generation software (NGS) program, and more recently through the advanced execution systems (AES) and the systems modeling and analysis (SMA) components of the follow-up computer systems research (CSR) program. The present workshop is part of the series of the next generation software workshops that have been conducted since 2001, on a yearly basis and in conjunction with IPDPS. The topics addressed in the workshop are on research in systems' software technology in the scope of NGS and of the AES and the SMA components, namely: methods for systems modeling and analysis, performance engineering, dependability, fault tolerance, and power-management, programming environments, enhanced compiler capabilities, tools for the development, dynamic runtime support and dynamic composition of complex applications executing on heterogeneous, parallel and distributed computing platform assemblies, such as computational grids, encompassing, advanced multiprocessing nodes, mid-range and high-end platforms, clusters, embedded and sensor systems, and special purpose processing systems.

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