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检索条件"任意字段=PDSE 2000: International Symposium on Software Engineering for Parallel and Distributed Systems"

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An entropy-based algorithm for time-driven software instrumentation in parallel systems 20

An entropy-based algorithm for time-driven software instrume...

引用

20th IEEE international parallel and distributed Processing symposium, IPDPS 2006

作者： Özmen, Ahmet Dumlupmar University Dept. of Electrical and Electronics Engineering Tavşanli Yolu 12 Km. Kütahya 43100 Turkey

ISBN: (纸本)1424400546

While monitoring, instrumented long running parallel applications generate huge amount of instrumentation data. Processing and storing this data incurs overhead, and perturbs the execution. Techniques that eliminates unnecessary instrumentation data and lower the intrusion without loosing any performance information is valuable to tool developers. This paper presents a new algorithm for software instrumentation to measure the amount of information content of instrumentation data to be collected. The algorithm is based on entropy concept introduced in information theory, and it makes selective data collection for a time-driven software monitoring system possible. © 2006 IEEE.

关键词： Computer software

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engineering reliability into hybrid systems via rich design models: Recent results and current directions 20

Engineering reliability into hybrid systems via rich design ...

引用

20th IEEE international parallel and distributed Processing symposium, IPDPS 2006

作者： Banerjee, Somo Cheung, Leslie Golubchik, Leana Medvidovic, Nenad Roshandel, Roshanak Sukhatme, Gaurav Computer Science Department University of Southern California Los Angeles CA 90089 United States EE-Systems Dept. IMSC University of Southern California Los Angeles CA 90089 United States Dept. of Comp. Sci. and Software Engr. Seattle University Seattle WA 98122 United States

ISBN: (纸本)1424400546

software reliability techniques are aimed at reducing or eliminating failures in software systems. Reliability in software systems has traditionally been measured during or after system implementation. However, software engineering methodology lays stress on doing the "correct things" early on in the software development lifecycle in order to curb development and maintenance costs. In this paper, we argue that reliability of a software system should be assessed throughout the system 's life span, starting with the software architecture level. Our research goal is to estimate the reliability of software systems in early design stages, which we believe involves the ability to reason about numerous uncertainties that exist in this stage, including uncertainty due to lack of execution artifacts. Our proposed approach is to develop techniques that will couple software architectural models with a suite of stochastic reliability estimation models and allow us to reason about these uncertainties. In this paper, we present our recent results using our technique for reliability estimation of software components at the level of software architecture. Another important part of this paper is the discussion of our ongoing research efforts and open research problems in this area. © 2006 IEEE.

关键词： software engineering

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An economy-driven mapping heuristic for hierarchical master-slave applications in grid systems 20

An economy-driven mapping heuristic for hierarchical master-...

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20th IEEE international parallel and distributed Processing symposium, IPDPS 2006

作者： Ranaldo, Nadia Zimeo, Eugenio University of Sannio Department of Engineering Benevento 82100 Italy University of Sannio Research Centre on Software Technology Benevento 82100 Italy

ISBN: (纸本)1424400546

In heterogeneous distributed systems, such as Grids, a resource broker is responsible of automatically selecting resources, and mapping application tasks to them. A crucial aspect of resource broker design, especially in a next commercial exploitation of grid systems, in which economy theories for resource management will be applied, is the support to task mapping based on the fulfilment of Quality of Service (QoS) constraints. The paper presents an economy-driven mapping heuristic, called time minimization, for mapping and scheduling the tasks assigned to the slaves of a master-slave application in a hierarchical and heterogeneous distributed system. The validity and accuracy of such heuristic are tested by implementing it in a resource broker of a hierarchical grid middleware used for running a real world application. © 2006 IEEE.

关键词： distributed computer systems

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SMTPS keynote: Research and technology advances in systems software for large scale computing systems 20

SMTPS keynote: Research and technology advances in systems s...

引用

20th IEEE international parallel and distributed Processing symposium, IPDPS 2006

作者： Darema, Frederica NSF CISE Arlington VA United States

ISBN: (纸本)1424400546

The talk will address research and technology advances for optimized and dependable execution in large scale computing environments. Applications in nearly all sectors, scientific, engineering, and commercial, are becoming more encompassing in including the behaviors of the systems of the systems they represent, and becoming at the same time more powerful but also more complex. At the same time, driven by application requirements and enabled by hardware technology advances, computational platforms are becoming as well increasingly more powerful but also more complex. Efficient and effective development of applications, optimized use of the computational resources, and guaranteeing quality of service and dependability at all layers of the computational system, requires systems software advances, such as in programming environments, application composition systems, optimized application mapping and dynamic runtime technologies, debugging and check-pointing methods, and performance-engineered hardware and software capabilities at all layers. An overarching consideration, and thesis of this talk, is that these advances need to be made in a synergistic and integrated manner, taking a systems-view in developing these enabling technologies, rather than advancing each of the individual technologies in an isolated manner. © 2006 IEEE.

关键词： Large scale systems

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software-based fault-tolerant routing algorithm in multi-dimensional networks 20

Software-based fault-tolerant routing algorithm in multi-dim...

引用

20th IEEE international parallel and distributed Processing symposium, IPDPS 2006

作者： Safaei, F. Rezazad, M. Khonsari, A. Fathy, M. Ould-Khaoua, M. Alzeidi, N. IPM School of Computer Science Tehran Iran Dept. of Electrical and Computer Engineering University of Tehran Tehran Iran Dept. of Computer Engineering Iran University of Science and Technology Tehran Iran Dept. of Computing Science University of Glasgow United Kingdom

ISBN: (纸本)1424400546

Massively parallel computing systems are being built with hundreds or thousands of components such as nodes, links, memories, and connectors. The failure of a component in such systems will not only reduce the computational power but also alter the network's topology. The software-Based fault-tolerant routing algorithm is a popular routing to achieve fault-tolerance capability in networks. This algorithm is initially proposed only for two dimensional networks [1]. Since, higher dimensional networks have been widely employed in many contemporary massively parallel systems;this paper proposes an approach to extend this routing scheme to these indispensable higher dimensional networks. Deadlock and livelock freedom and the performance of presented algorithm, have been investigated for networks with different dimensionality and various fault regions. Furthermore, performance results have been presented through simulation experiments. © 2006 IEEE.

关键词： Routers

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Facing the challenges of multicore processor technologies using autonomic system software 20

Facing the challenges of multicore processor technologies us...

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20th IEEE international parallel and distributed Processing symposium, IPDPS 2006

作者： Nikolopoulos, Dimitris Department of Computer Science College of William and Mary Williamsburg VA United States

ISBN: (纸本)1424400546

Multicore processor technologies, which appear to dominate the processor design landscape, require a shift of paradigm in the development of programming models and supporting environments for scientific and engineering applications. System software for multicore processors needs to exploit fine-grain concurrent execution capabilities and cope with deep, non- uniform memory hierarchies. software adaptation to multicore technologies needs to happen even as hardware platforms change underneath the software. Last but not least, due to the extremely high compute density of chip multiprocessing components, system software needs to increase its energy-awareness and treat energy and temperature distribution as first-class optimization targets. Unfortunately, energy awareness is most often at odds with high performance. In the first part of this talk I will discuss some of the major challenges of software adaptation to multicore technologies and motivate the use of autonomic, self- optimizing system software, as a vehicle for both high performance portability and energy-efficient program execution. In the second part of the talk I will present ongoing research in runtime environments for dense parallel systems built from multicore and SMT components, and focus on two topics, polymorphic multithreading, and power-aware concurrency control with quality-of-service guarantees. In the same context, I will discuss enabling technologies for improved software autonomy via dynamic runtime optimization, including continuous hardware profilers, and online power-efficiency predictors. © 2006 IEEE.

关键词： Multiprocessing systems

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The Robot software Communications Architecture (RSCA): Embedded middleware for networked service robots 20

The Robot Software Communications Architecture (RSCA): Embed...

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20th IEEE international parallel and distributed Processing symposium, IPDPS 2006

作者： Hong, Seongsoo Lee, Jaesoo Eom, Hyeonsang Jeon, Gwangil Real-Time Operating Systems Laboratory School of Electrical Engineering and Computer Science Seoul National University Seoul 151-744 Korea Republic of Distributed Information Processing Laboratory School of Computer Science and Computer Engineering Seoul National University Seoul 151-744 Korea Republic of Department of Computer Engineering Korea Polytechnic University 2121 Jungwang-Dong Siheung-Si Gyunggi-Do 429-793 Korea Republic of

ISBN: (纸本)1424400546

In this paper, we present a robot middleware technology named Robot software Communications Architecture (RSCA) for its use in networked home service robots. The RSCA provides a standard operating environment for the robot applications together with a framework that expedites the development of such applications. The operating environment is comprised of a real-time operating system, a communication middleware, and a deployment middleware. Particularly, the deployment middleware supports the reconfiguration of component-based robot applications including installation, creation, start, stop, tear-down, and un-installation, In designing RSCA, we have adopted a middleware called SCA from the software defined radio domain and extend it since the original SCA lacks the real-time guarantees and appropriate event services. We have fully implemented RSCA and performed measurements to quantify its run-time performance. Our implementation clearly shows the viability of RSCA. © 2006 IEEE.

关键词： Middleware

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Workflow fine-grained concurrency with automatic continuation 20

Workflow fine-grained concurrency with automatic continuatio...

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20th IEEE international parallel and distributed Processing symposium, IPDPS 2006

作者： Tretola, Giancarlo Zimeo, Eugenio University of Sannio Department of Engineering Benevento 82100 Italy University of Sannio Research Centre on Software Technology Benevento 82100 Italy

ISBN: (纸本)1424400546

Workflow enactment systems are becoming an effective solution to ease programming, deployment and execution of distributed applications in several domains such as telecommunication, manufacturing, e-business, e-government and grid computing. In some of these fields, efficiency and traffic optimization represent key aspects for a wide diffusion of workflow engines and modeling tools. This paper focuses on a technique that enables fine-grained concurrency in compute and data-intensive workflows and reduces the traffic on the network by limiting the number of interactions to the ones strictly needed to bring the data where they are really necessary for continuing the flow of computations. We implemented this technique by using the concepts of wait by necessity and automatic continuation and we integrated it in a flexible, Java workflow engine that through the new mechanisms is able to navigate a workflow anticipating the enactment of sequential activities. © 2006 IEEE.

关键词： Concurrent engineering

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Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic 20

Design flow for optimizing performance in processor systems ...

引用

20th IEEE international parallel and distributed Processing symposium, IPDPS 2006

作者： Galanis, Michails D. Dimitroulakos, Gregory Goutis, Costas E. VLSI Design Lab. Electrical and Computer Engineering Department University of Patras Rio 26500 Greece

ISBN: (纸本)1424400546

A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented The reconfigurable logic is realized by a 2-Ditnensional Array of Processing Elements, Performance is improved by accelerating critical software loops, called kernels, on the Reconfigurable Array. Basic steps of the design flow have been automated. A procedure for detecting critical loops in the input C code was developed, while a mapping technique for Coarse Grain Reconfigurable Arrays, based on software pipelining, was also devised. Analytical results derived from mapping five real-life DSP applications on eight different instances of a generic system architecture are presented. Large values of Instructions Per Cycle were achieved on two Reconfigurable Arrays that resulted in high-performance kernel mapping. Additionally, by mapping critical code on the reconfigurable logic, speedups ranging from 1.27 to 3.18 relative to an all-processor execution were achieved. © 2006 IEEE.

关键词： Program processors

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Power-dependable transactions in mobile networks 20

Power-dependable transactions in mobile networks

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20th IEEE international parallel and distributed Processing symposium, IPDPS 2006

作者： Marowka, Ami Semé, David Software Engineering Department Shenkar College of Engineering and Design 12 Anna Frank Ramat-Gan 52526 Israel LaRIA: Laboratoire de Recherche en Informatique d'Amiens Université de Picardie Jules Verne 33 rue Saint Leu 80000 Amiens France

ISBN: (纸本)1424400546

We define a Quality-of-Power-Service (QoPS) metric to evaluate the efficiency of power-aware routing protocols in wireless ad-hoc networks. The aim of power management of routing protocols is to prolong the life-time of individual nodes in wireless network and thus to increase the delivery rate of Unicast transactions. QoPS metric is applied to different location-based Unicast transaction protocols. The results confirm that power-relative distribution of data streams in multi-paths Unicast transaction protocols consume substantially less energy from individual nodes than from other distribution methods. The locality distribution phenomenon discovered by the simulations explains, on the one hand, the long lifetime of large, dense, and highly degree wireless networks, and on the other hand, the short lifetime of small, sparse, and low degree networks © 2006 IEEE.

关键词： Mobile telecommunication systems

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