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检索条件"任意字段=PDSE 2000: International Symposium on Software Engineering for Parallel and Distributed Systems"

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parallel and distributed Computing with Java

Parallel and Distributed Computing with Java

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international symposium on parallel and distributed Computing

作者： Mark A. Baker Matthew Grove Aamir Shafi School of Systems Engineering University of Reading Reading UK DSG University of Portsmouth UK

ISBN: (纸本)9780769526381;0769526381

The Java language first came to public attention in 1995. Within a year, it was being speculated that Java may be a good language for parallel and distributed computing. Its core features, including being objected oriented and platform independence, as well as having built-in network support and threads, has encouraged this view. Today, Java is being used in almost every type of computer-based system, ranging from sensor networks to high performance computing platforms, and from enterprise applications through to complex research-based simulations. In this paper the key features that make Java a good language for parallel and distributed computing are first discussed. Two Java-based middleware systems, namely MPJ Express, an MPI-like Java messaging system, and Tycho, a wide-area asynchronous messaging framework with an integrated virtual registry are then discussed. The paper concludes by highlighting the advantages of using Java as middleware to support distributed applications

关键词： distributed computing Java High performance computing Middleware Yarn Computer networks Sensor systems and applications Application software Computational modeling Computer simulation

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Managing Information and Time Flow in an Agent-Based E-Commerce System

Managing Information and Time Flow in an Agent-Based E-Comme...

引用

international symposium on parallel and distributed Computing

作者： Maciej Gawinecki Maria Ganzha Pawel Kobzdej Marcin Paprzycki Costin Badica Mihnea Scafes Gabriel-george Popa Systems Research Institute Polish Academy of Sciences Warsaw Poland Department of Software Engineering University of Craiova Craiova Romania

ISBN: (纸本)9780769526381;0769526381

Recently, we have proposed a comprehensive agent-based e-commerce system. While UML formalized, it lacked details how basic functions - e.g. user request to purchase a given product - are to be implemented. Furthermore, the "airline ticket reservation model" used in the system involves time management issues that have not been addressed. The aim of the paper is to discuss the way in which the information flow and data transformations involved in it are to be implemented; assuming that information about products is to be ontologically represented. Furthermore, a simple way in which time information can be successfully managed to support the proposed product reservation approach will be discussed

关键词： Information management engineering management software engineering Unified modeling language Ontologies Marketing and sales Intelligent agent OWL Computer architecture Service oriented architecture

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Facing the challenges of multicore processor technologies using autonomic system software 06

Facing the challenges of multicore processor technologies us...

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international symposium on parallel and distributed Processing (IPDPS)

作者： D. Nikolopoulos Department of Computer Science College of William and Mary Williamsburg VA USA

ISBN: (纸本)9781424400546

Summary form only given. Multicore processor technologies, which appear to dominate the processor design landscape, require a shift of paradigm in the development of programming models and supporting environments for scientific and engineering applications. System software for multicore processors needs to exploit fine-grain concurrent execution capabilities and cope with deep, non- uniform memory hierarchies. software adaptation to multicore technologies needs to happen even as hardware platforms change underneath the software. Last but not least, due to the extremely high compute density of chip multiprocessing components, system software needs to increase its energy-awareness and treat energy and temperature distribution as first-class optimization targets. Unfortunately, energy awareness is most often at odds with high performance. In the first part of this talk, the author discusses some of the major challenges of software adaptation to multicore technologies and motivate the use of autonomic, self-optimizing system software, as a vehicle for both high performance portability and energy-efficient program execution. In the second part of the talk, the author presents ongoing research in runtime environments for dense parallel systems built from multicore and SMT components, and focus on two topics, polymorphic multithreading, and power-aware concurrency control with quality-of-service guarantees. In the same context, the author discusses enabling technologies for improved software autonomy via dynamic runtime optimization, including continuous hardware profilers, and online power-efficiency predictors

关键词： Multicore processing System software Hardware Process design Design engineering Application software distributed computing Temperature distribution software performance Vehicles

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D1HT: a distributed one hop hash table 06

D1HT: a distributed one hop hash table

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international symposium on parallel and distributed Processing (IPDPS)

作者： L.R. Monnerat C.L. Amorim Comput. & Syst. Eng. Fed. Univ. of Rio de Janeiro Brazil COPPE-Computer and Systems Engineering Federal University of Rio de Janeiro Brazil

ISBN: (纸本)9781424400546

distributed hash tables (DHTs) have been used in a variety of applications, but most DHTs so far have opted to solve lookups with multiple hops, which sacrifices performance in order to keep little routing information and minimize maintenance traffic. In this paper, we introduce D1HT, a novel single hop DHT that is able to maximize performance with reasonable maintenance traffic overhead even for huge and dynamic peer-to-peer (P2P) systems. We formally define the algorithm we propose to detect and notify any membership change in the system, prove its correctness and performance properties, and present a quarantine-like mechanism to reduce the overhead caused by volatile peers. Our analyses show that D1HT has reasonable maintenance bandwidth requirements even for very large systems, while presenting at least twice less bandwidth overhead than previous single hop DHT

关键词： Routing Bandwidth Peer to peer computing Telecommunication traffic Application software Delay distributed computing systems engineering and theory Change detection algorithms Mechanical factors

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On-chip and on-line self-reconfigurable adaptable platform: the non-uniform cellular automata case 06

On-chip and on-line self-reconfigurable adaptable platform: ...

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international symposium on parallel and distributed Processing (IPDPS)

作者： A. Upegui E. Sanchez Logic Systems Laboratory Ecole Polytechnique Fédérale de Lausanne Lausanne Switzerland

ISBN: (纸本)9781424400546

In spite of the high parallelism exhibited by cellular automata architectures, most implementations are usually run in software. For increasing execution parallelism, hardware implementations on FPGAs have been proposed, under the cost of being un-flexible, and inefficient in terms of resource utilization. In this paper, we present a platform for evolving CA by exploiting the partial re-configurability of current commercial FPGAs. Our implementation includes an on-chip soft-processor that generates a partial bitstream, reconfigures the FPGA, and computes the fitness. After finding a good individual, the evolved CA can be used as a peripheral for performing useful computation. As case study we present CA co-evolution for a random number generator and for the firefly synchronization problem

关键词： Computer aided software engineering Hardware Field programmable gate arrays Circuits Genomics Bioinformatics Programmable logic arrays System-on-a-chip parallel processing Costs

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Automatic performance visualization of distributed real-time systems

Automatic performance visualization of distributed real-time...

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international symposium on Object-Oriented Real-Time distributed Computing

作者： T. Harmon R. Klefstad Department of Electrical Engineering and Computer Science The Henry Samueli University of California Irvine Irvine CA USA

For distributed real-time systems, adequate profiling tools are exceedingly rare. The sheer variety and low-level nature of these systems impede the adoption of standard, general-purpose tools for performance analysis and visualization. Although much research has been devoted to profiling parallel clusters and supercomputers, the literature virtually ignores the real-time domain. Correspondingly, a handful of commercial tools is available for profiling realtime software, but they invariably make a single-node assumption and are unable to cope with distributed environments. We examine the state of performance analysis and discuss why profilers are conspicuously absent in the field of distributed real-time systems. We then explore how developers of these systems could benefit from graphical profiling tools with automatic instrumentation and data collection. Toward that end, we demonstrate the prototype of a performance visualization tool called "Bacara", the second addition to our suite of tools for visual analysis of distributed real-time systems, or VADR (vamacr'der)

关键词： Visualization Real time systems Performance analysis Instruments Sampling methods software performance Cryptography Poles and towers Impedance Supercomputers

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A note on broadcast encryption key management with applications to large scale emergency alert systems 06

A note on broadcast encryption key management with applicati...

引用

international symposium on parallel and distributed Processing (IPDPS)

作者： Guoqiang Shu D. Lee M. Yannakakis Department of Computer Science and Engineering Ohio State Uinversity Columbus OH USA Department of Computer Science Columbia University New York NY USA

ISBN: (纸本)9781424400546

Emergency alerting capability is crucial for the prompt response to natural disasters and terrorist attacks. The emerging network infrastructure and secure broadcast techniques enable prompt and secure delivery of emergency notification messages. With the ubiquitous deployment of alert systems, scalability and heterogeneity pose new challenges for the design of secure broadcast schemes. In this paper, we discuss the key generation problem with the goal of minimizing the total number of keys which need to be generated by the alert center and distributed to the users. Two encryption schemes, zero message scheme and extended header scheme, are modeled formally. For both schemes we show the equivalence of the general optimal key generation (OKG) problem and the bipartite clique cover (BCC) problem, and show that OKG problem is NP-hard. The result is then generalized to the case with resource constraints, and we provide a heuristic algorithm for solving the restricted BCC (and OKG) problem.

关键词： Cryptography Disaster management Large-scale systems TV broadcasting Application software Computer science Terrorism engineering management Scalability Heuristic algorithms

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An adaptive system-on-chip for network applications 06

An adaptive system-on-chip for network applications

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international symposium on parallel and distributed Processing (IPDPS)

作者： R. Koch T. Pionteck C. Albrecht E. Maehle Institute of Computer Engineering University of Lübeck Lubeck Germany

ISBN: (纸本)9781424400546

This paper presents the hardware architecture of DynaCORE, a dynamically reconfigurable system-on-chip for network applications. DynaCORE is an application specific coprocessor for offloading computationally intensive tasks from a network processor. The system-on-chip architecture is based on an adaptable network-on-chip which allows the dynamic replacement of hardware modules as well as the adaptation of the on-chip communication structure. The coprocessor leverages the active partial reconfiguration feature of modern FPGAs in order to adapt to shifting demand patterns. An embedded general-purpose processor core within the coprocessor runs software which manages the configurations of the device. With reference to a prototypical implementation targeting a Xilinx Virtex-II Pro FPGA, this paper focuses on on-chip communication issues. Topics include the integration of PowerPC processor cores into the configurable logic as well as the mode of operation of the network-on-chip

关键词： Adaptive systems System-on-a-chip Coprocessors Network-on-a-chip Hardware Computer architecture Field programmable gate arrays Computer networks Embedded software software prototyping

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Interconnect performance evaluation of SGI Altix 3700 BX2, Cray XI, Cray Opteron Cluster, and Dell PowerEdge

Interconnect performance evaluation of SGI Altix 3700 BX2, C...

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international symposium on parallel and distributed Processing (IPDPS)

作者： R. Fatoohi S. Saini R. Ciotti Computer Engineering Department San Jose State University Foundation San Jose CA USA Advanced Supercomputing Division NASA Ames Research Center CA USA

We study the performance of inter-process communication on four high-speed multiprocessor systems using a set of communication benchmarks. The goal is to identify certain limiting factors and bottlenecks with the interconnect of these systems as well as to compare these interconnects. We measured network bandwidth using different numbers of communicating processors and communication patterns - such as point-to-point communication, collective communication, and dense communication patterns. The four platforms are: a 512-processor SGIAltix 3700 BX2 shared-memory machine with 3.2 GB/s links; a 64-processor (single-streaming) Cray XI shared-memory machine with 32 1.6 GB/s links; a 128-processor Cray Opteron cluster using a Myrinet network; and a 1280-node Dell PowerEdge cluster with an InfiniBand network. Our results show the impact of the network bandwidth and topology on the overall performance of each interconnect

关键词： Bandwidth NASA Message passing Application software Delay Kernel High performance computing Network topology Power engineering computing Power engineering and energy

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High-level synthesis with reconfigurable datapath components 06

High-level synthesis with reconfigurable datapath components

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international symposium on parallel and distributed Processing (IPDPS)

作者： G. Economakos School of Electrical and Computer Engineering Microprocessors and Digital Systems Laboratory National and Technical University of Athens Athens Greece

ISBN: (纸本)9781424400546

High-level synthesis is becoming more popular as design densities keep increasing, especially in the ASIC design world. Although FPGA design follows ASIC design methodologies and FPGA densities are increasing too, programmable devices also offer the advantage of partial reconfiguration, which allows an algorithm to be partially mapped into a small and fixed FPGA device that can be reconfigured at run time, as the mapped application changes its requirements. This paper presents a novel resource constrained high-level synthesis scheduling heuristic, which utilizes reconfigurable datapath components. The resulting schedule can be shortened so as the gain in clock cycles can overcome the timing overhead of reconfiguration. The main advantage of the proposed methodology is that through run time reconfiguration, more complicated algorithms can be mapped into smaller devices without speed degradation

关键词： High level synthesis Hardware Field programmable gate arrays software maintenance Microprocessors Application specific integrated circuits Clocks Timing software performance Programmable logic arrays

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