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Improving memory performance of embedded Java applications by dynamic layout modifications

Improving memory performance of embedded Java applications b...

引用

international symposium on parallel and distributed Processing (IPDPS)

作者： F. Li P. Agrawal G. Eberhardt E. Manavoglu S. Ugurel M. Kandemir Department of Computer Science and Engineering Pennsylvania State University University Park PA USA

Summary form only given. Unlike desktop systems, embedded systems use different user interface technologies; have significantly smaller form factors; use a wide variety of processors; and have very tight constraints on power/energy consumption, user response time, and physical space. With its platform independence and secure execution environment, Java is fast becoming the language of choice for programming embedded systems. In order to extend its use to array based applications from embedded image and video processing, Java programmers need to employ several optimizations. Unfortunately, due to its precise exception mechanism and bytecode distribution form, it is not generally possible to use classical loop based optimization techniques for array based embedded Java applications. Observing this, this paper proposes a dynamic memory layout optimization strategy for Java applications. The strategy is based on observing the cache behavior dynamically and transforming memory layouts of arrays, when necessary, during the course of execution. This is in contrast to many previously proposed memory layout optimization strategies, which are static in nature (i.e., they are applied at compile time). Our results indicate large performance improvements on a suite of seven array based applications.

关键词： Java Embedded system Power engineering and energy Space technology Electric breakdown Application software Computer science User interfaces Energy consumption Delay

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Nemos: a framework for axiomatic and executable specifications of memory consistency models

Nemos: a framework for axiomatic and executable specificatio...

引用

international symposium on parallel and distributed Processing (IPDPS)

作者： Y. Yang Ganesh Gopalakrishnan G. Lindstrom K. Slind School of Computing University of Utah USA

Summary form only given. Conforming to the underlying memory consistency rules is a fundamental requirement for implementing shared memory systems and developing multiprocessor programs. In order to promote understanding and enable automated verification, it is highly desirable that a memory model specification be both declarative and executable. We present a specification framework called Nemos (Nonoperational yet Executable Memory Ordering Specifications), which supports precise specification and automatic execution in the same framework. We employ a uniform notation based on predicate logic to define shared memory semantics in an axiomatic as well as compositional style. We also apply constraint logic programming and SAT solving to make the axiomatic specifications executable for memory model analysis. To illustrate our approach, we formalize a collection of classical memory models, including sequential consistency, coherence, PRAM, causal consistency, and processor consistency.

关键词： Coherence Phase change random access memory Logic programming Random access memory Read-write memory Yarn Computer languages Java software engineering Programming profession

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An integrated FPGA design framework: custom designed FPGA platform and application mapping toolset development

An integrated FPGA design framework: custom designed FPGA pl...

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international symposium on parallel and distributed Processing (IPDPS)

作者： V. Kalenteridis H. Pournara K. Siozios K. Tatas G. Koytroympezis I. Pappas S. Nikolaidis S. Siskos D.J. Soudris A. Thanailakis Electronics and Computers Division Department of Physics Aristotle University of Thessaloniki Thessaloniki Greece VLSI Design and Testing Center Department of Electrical and Computer Engineering Democritus University of Thrace Xanthi Greece

Summary form only given. A complete system for the implementation of digital logic in a fine-grain reconfigurable platform is introduced. The system is composed of two parts: The fine-grain reconfigurable hardware platform (FPGA) on which the logic is implemented and the set of CAD tools for mapping logic to the FPGA platform. The novel energy-efficient FPGA architecture was designed and simulated in STM 0.18/spl mu/m CMOS technology. Concerning the tool flow, each tool can operate as a standalone program as well as part of a complete design framework, composed by existing and new tools.

关键词： Field programmable gate arrays Logic design Reconfigurable logic Integrated circuit interconnections CMOS technology Graphical user interfaces Operating systems Delay Application software Electronic equipment testing

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Multiple-route ad hoc on-demand distance vector (MRAODV) routing protocol

Multiple-route ad hoc on-demand distance vector (MRAODV) rou...

引用

international symposium on parallel and distributed Processing (IPDPS)

作者： H. Higaki S. Umeshima Department of Computers and Systems Engineering Tokyo Denki University Hiki Saitama Japan

Summary form only given. Several routing protocols, e.g. DSR(dynamic source routing protocol) and AODV(ad-hoc ondemand distance vector routing protocol), have been proposed for routing data packets in ad hoc networks. These are ondemand routing protocols. Only when a node requires to transmit data packets, it searches a route to a destination node. In addition, these are single-path protocols which detect only one route. However, in an ad hoc network, due to mobility of nodes and instability of communication links, multiple-route protocols are required. Here, we propose a novel multiple-route protocol MRAODV(multiple-route ondemand distance vector routing protocol) where separated reverse path fragments are connected to achieve additional routes. According to simulation results, more additional routes are detected in our protocol than MNH protocol.

关键词： Routing protocols Mobile computing Computer networks Ad hoc networks Application software Personal digital assistants Personal communication networks Wireless LAN Computer network management Mobile communication

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Construct a grid computing environment for bioinformatics

Construct a grid computing environment for bioinformatics

引用

international symposium on parallel Architectures, Algorithms and Networks (ISPAN)

作者： Yu-Lun Kuo Chao-Tung Yang Chuan-Lin Lai Tsai-Ming Tseng High-Performance Computing Laboratory Department of Computer Science and Information Engineering Tunghai University Taichung Taiwan

ISBN: (纸本)0769521355

Internet computing and grid technologies promise to change the way we tackle complex problems. They will enable large-scale aggregation and sharing of computational, data and other resources across institutional boundaries. And harnessing these new technologies effectively will transform scientific disciplines ranging from high-energy physics to the life sciences. The computational analysis of biological sequences is a kind of computation driven science. Cause the biology data growing quickly and these databases are heterogeneous. We can use the grid system sharing and integrating the heterogeneous biology database. As we know, bioinformatics tools can speed up analysis the large-scale sequence data, especially about sequence alignment. The FASTA is a tool for aligning multiple protein or nucleotide sequences. FASTA which we used is a distributed and parallel version. The software uses a message-passing library called MPl (Message Passing Interface) and runs on distributed workstation clusters as well as on traditional parallel computers. A grid computing environment is proposed and constructed on multiple Linux PC clusters by using Globus Toolkit (GT) and SUN Grid Engine (SGE). The experimental results and performances of the bioinformatics tool using on grid system are also presented in this paper.

关键词： Grid computing Bioinformatics Sequences Biology computing Large-scale systems Databases Internet Physics Proteins software libraries

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A channel caching scheme on an optical bus-based distributed architecture

A channel caching scheme on an optical bus-based distributed...

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international symposium on parallel and distributed Processing (IPDPS)

作者： M. Zhu H. Narravula C. Katsinis D. Hecht Department of Electrical and Computer Engineering Drexel University Philadelphia PA USA

Summary form only given. Reducing the effect of hot spots is increasingly important to gain performance out of modern processor clusters. Traditionally, compiler techniques have been used for static analysis of hot spot patterns in parallel applications. The operating system then performs the optimization to reduce the overhead of hot spots. However, hot spots cannot be avoided due to the dynamic nature of applications. We propose a new hot spot optimization scheme based on a broadcast-based optical interconnection network, the SOME-Bus, where each node has a dedicated broadcast channel to connect with other nodes without any contention. The scheme introduces additional hardware to considerably reduce the latency of hot spot request/acknowledges. Hot spots are assumed to be identifiable either through static analysis, or by a run-time profiler. Our scheme then provides a way to cache these hot spot blocks much closer to the network/channel, thereby providing a very low latency path between the input and the output queues in the network. The technique has been implemented in a SOME-Bus simulator, and verified with popular parallel algorithms like matrix-matrix multiplication. Preliminary results show that the scheme results in the reduction of completion times of applications by up to 24% over a system without channel caching.

关键词： Hardware Delay Scheduling algorithm Computer architecture Operating systems Broadcasting Optical interconnections Performance gain Pattern analysis Application software

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Analysis of parallel Matrix Multiplication Algorithms

Analysis of Parallel Matrix Multiplication Algorithms

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2004 international symposium on distributed Computing and Applications to Business, engineering and Science

作者： Wanlong Liu Yaolin Gu Southern Yangtze University Wuxi,Jiangsu,214036,PR of China

Matrix multiplication is the fundamental operation in many numerical linear algebra *** efficient implementation on parallel high performance computers, together with the implementation of other basic linear algebra operations,is an issue of primary importance for providing these systems with scientific software libraries. Consequently,considerable effort has been devoted to development of efficient practical parallel matrix multiplication *** this paper,we describe performance analysis of a simple parallel algorithm, Cannon's algorithm,systolic algorithm and hyper-systolic *** analysis indicates that the performance of the hyper-systolic algorithm outperforms the other algorithms.

关键词： Matrix Multiplication Performance Analysis Cannon's Algorithm Systolic Algorithm Hyper-systolic Algorithm

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Scheduling real time parallel structures on cluster computing with possible processor failures

Scheduling real time parallel structures on cluster computin...

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IEEE symposium on Computers and Communications (ISCC)

作者： A. Amin R. Ammar A. El Dessouly Computer Science and Engineering Department University of Connecticut USA Electronics Research Institute Giza Egypt

Efficient task scheduling is essential for achieving high performance computing applications for distributed systems. Most of existing real-time systems consider schedulability as a main goal and ignores other effects such as machines failures. In This work we develop an algorithm to efficiently schedule parallel task graphs (fork-join structures). Our scheduling algorithm considers more than one factor at the same time. These factors are scheduability, reliability of the participating processors and achieved degree of parallelism. To achieve most of these goals, we composed an objective function that combines these different factors simultaneously. The proposed objective function is adjustable to provide the user with a way to prefer one factor to the others. The simulation results indicate that our algorithm produces schedules where the applications deadlines are met, reliability is maximized and the application parallelism is exploited.

关键词： Processor scheduling Concurrent computing Application software Real time systems Scheduling algorithm parallel processing Telecommunication network reliability Computer science High performance computing Clustering algorithms

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FM screening by the local exhaustive search, with hardware acceleration

FM screening by the local exhaustive search, with hardware a...

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international symposium on parallel and distributed Processing (IPDPS)

作者： Y. Ito K. Nakano Department of Artificial Complex Systems Engineering Hiroshima University Japan

Summary form only given. The main contribution of this paper is to show a new approach for FM screening which we call local exhaustive search (LES) method, and to present ways to accelerate the computation using an FPGA. FM screening, as opposed to conventional AM screening, keeps unit dot size when converting an original gray-scale image into the binary image for printing. FM screening pays great attention to generate moire-free binary images reproducing continuous-tone and fine details of original photographic images. Our basic approach for FM screening is to generate a binary image whose projected image onto human eyes is very close to the original image. The projected image is computed by applying a Gaussian filter to the binary image. LES performs an exhaustive search for each of the small square subimages in the binary image and replaces the subimage by the best binary pattern. The exhaustive search is repeated until no more improvement is possible. The experimental results show that LES produces high quality sharp binary images. We also implemented LES on an FPGA to accelerate the computation and achieved a speedup factor of up to 43 over the software implementations.

关键词： Hardware Acceleration Field programmable gate arrays Image generation Image converters Gray-scale Printing Humans Eyes Filters

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A Comparative Survey of Fault-tolerant and Load balanced MPI Implementations,software Packages and Algorithms

A Comparative Survey of Fault-tolerant and Load balanced MPI...

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2004 international symposium on distributed Computing and Applications to Business, engineering and Science

作者： Raihan Ur Rasool School of Computer Science and Technology The Wuhan University of Technology

Advancement in high-speed networks and rapid improvement in microprocessor design enabled cost-effective highperformance parallel computing on clustered low cost workstations and *** based on message passing draw attractions in the field of high performance computing, where loop or data parallelism is a main source of parallel ***,MPI is one of the most adopted programming models for Large Clusters and Grid ***,these systems often suffer from network or node failures,because the nodes of such systems are likely to be heterogeneous with respect to computing power and *** raises the issue of selecting a fault tolerance approach for MPI to manage various dynamic failures ***,loads should be balanced according to the performance of nodes to minimize the elapsed time of *** models have emerged to simplify the task of programming in network environment,but MPI approach is considered one of the most mature methods currently used in parallel *** paper presents an overview of Message-passing models in the context of Grid Computing and a comparative survey of fault-tolerant and load balanced system,algorithms and software packages for MPI.

关键词： Fault-tolerant MPI Grid Computing Dynamic Load-balanced systems parallel Computing Cluster of workstations

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