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international parallel and distributed Processing symposium, IPDPS 2003

作者： Lundberg, Lars Häggander, Daniel Klonowska, Kamilla Svahnberg, Charlie Department of Software Engineering and Computer Science Blekinge Institute of Technology RonnebyS-372 25 Sweden

ISBN: (纸本)0769519261

Clusters and distributed systems offer fault tolerance and high performance through load sharing, and are thus attractive in real-time applications. When all computers are up and running, we would like the load to be evenly distributed among the computers. When one or more computers-fail the must be redistributed. The redistribution is determined by the recovery scheme. The recovery scheme should keep the load as evenly distributed as possible even when the most unfavorable combinations of computers break down, i.e. we want to optimize the worst-case behavior. In this paper we define recovery schemes, which are optimal for a number of important cases. We also show that the problem of finding optimal recovery schemes corresponds to the mathematical problem of finding sequences of integers with minimal sum and for which all sums of subsequences are unique. © 2003 IEEE.

关键词： Fault tolerance

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HiDISC: A decoupled architecture for data-intensive applications

HiDISC: A decoupled architecture for data-intensive applicat...

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international parallel and distributed Processing symposium, IPDPS 2003

作者： Ro, Won W. Gaudiot, Jean-Luc Crago, Stephen P. Despain, Alvin M. Department of Electrical Engineering University of Southern California United States Department of Electrical Engineering and Computer Science University of California Irvine United States Information Sciences Institute-East University of Southern California United States

ISBN: (纸本)0769519261

This paper presents the design and performance evaluation of our high-performance decoupled architecture, the HiDISC (Hierarchical Decoupled Instruction Stream Computer). HiDISC provides low memory access latency by introducing enhanced data prefetching techniques at both the hardware and the software levels. Three processors, one for each level of the memory hierarchy, act in concert to mask the memory latency. Our performance evaluation benchmarks include the Data-Intensive systems Benchmark suite and the DIS Stressmark suite. Our simulation results point to a distinct advantage of the HiDISC system over current prevailing superscalar architectures for both sets of the benchmarks. On the average, a 12% improvement in performance is achieved while 17% of cache misses are eliminated. © 2003 IEEE.

关键词： Benchmarking

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Dynamic scheduling issues in SMT architectures

Dynamic scheduling issues in SMT architectures

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international parallel and distributed Processing symposium, IPDPS 2003

作者： Shin, Chulho Lee, Seong-Won Gaudiot, Jean-Luc System Design Technology Laboratory Samsung Electronics Corporation Korea Republic of Dept. of Electrical Engineering - Systems University of Southern California United States Dept. of Electrical Engineering and Computer Science University of California Irvine United States

ISBN: (纸本)0769519261

Simultaneous multithreading (SMT) attempts to attain higher processor utilization by allowing instructions from multiple independent threads to coexist in a processor and compete for shared resources. Previous studies have shown, however, that its throughput may be limited by the number of threads. A reason is that a fixed thread scheduling policy cannot be optimal for the varying mixes of threads it may face in an SMT processor. Our adaptive dynamic thread scheduling (ADTS) was previously proposed to achieve higher utilization by allowing a detector thread to make use of wasted pipeline slots with nominal hardware and software costs. The detector thread adaptively switches between various fetch policies. Our previous study showed that a single fixed thread scheduling policy presents much room (some 30%) for improvement compared to an oracle-scheduled case. In this paper, we take a closer look at ADTS. We implemented the functional model of the ADTS and its software architecture to evaluate various heuristics for determining a better fetch policy for a next scheduling quantum. We report that performance could be improved by as much as 25%. © 2003 IEEE.

关键词： Scheduling

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distributed P2P computing within Triana: A galaxy visualization test case

Distributed P2P computing within Triana: A galaxy visualizat...

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international parallel and distributed Processing symposium, IPDPS 2003

作者： Taylor, Ian Shields, Matthew Wang, Ian Philp, Roger Department of Computer Science Cardiff University United Kingdom Departments of Physics and Astronomy and Computer Science Cardiff University United Kingdom Cardiff Centre for Computational Science and Engineering Cardiff University United Kingdom

ISBN: (纸本)0769519261

We discuss here a parallel implementation of the visualisation of data from a galaxy formation simulation within the Triana problem-solving environment. The visualisation is a test case for our prototype Triana Grid software using a decentralized peer-to-peer approach. The Triana distributed environment is middleware independent and designed in such a way as to make it easily extensible by users of the system. This novel approach is usable both within a peer-to-peer framework, using JXTA, and within service oriented architectures, such as OGSA, by the use of a Grid application toolkit (GAT) interface. Furthermore, Triana has a pluggable architecture that allows the middleware independent representations of distributed task-graphs to be written in several popular formats. This facilitates the use of the mechanism within other disparate systems. Galaxy-formation simulation codes generate data that represent a series of particles in three dimensions and their associate properties as snapshots in time. An important aspect of these types of calculation is the visualization of time sequence data. The user of the code would like to visualize this data as an animation in two dimensions with the ability to vary the point of view, project that particular two dimensional slice and re-run the animation. The recalculation of the projection can be computed in parallel resulting in a considerable speedup. © 2003 IEEE.

关键词： Visualization

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Sensitivity estimation for magnetic devices using a double-layer model

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international JOURNAL OF APPLIED ELECTROMAGNETICS AND MECHANICS 2003年第1-3期17卷 221-230页

作者： Mueller, C Scheinert, G Uhlmann, FH Objexxts Software GmbH Ltd D-98693 Ilmenau Germany

The paper describes an approach to general-purpose design sensitivity analysis for electromagnetic devices. Microsystem technology often requires the assessment of manufacturing techniques or effects of tolerances. Emphasis is therefore put on the adaptability to different requirements, depending on desired accuracy, computational effort and significance. By introducing a distributed sensitivity function, the effect of small contour distortions can be described. The design sensitivity is based on a magnetic double-layer model. It is shown that sensitivity can be expressed in terms of virtual anti-parallel double-layer currents, flowing in a movable contour. The sensitivity is explicitly derived for two-dimensional coordinate systems using the finite-difference method within a commercially available field computation program. The proposed method is demonstrated by two examples.

关键词： SENSITIVITY theory (Mathematics) MAGNETIC devices MAGNETICS MAGNETISM CONTROL theory (Mathematics)

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Using TOP-C and AMPIC to port large parallel applications to the Computational Grid

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FUTURE GENERATION COMPUTER systems-THE international JOURNAL OF ESCIENCE 2003年第4期19卷 587-596页

作者： Cooperman, G Casanova, H Hayes, J Witzel, T Northeastern Univ Coll Comp Sci Boston MA 02115 USA Univ Calif San Diego Dept Comp Sci & Engn San Diego CA 92103 USA Univ Calif San Diego San Diego Supercomp Ctr San Diego CA 92103 USA

Porting large parallel applications to new and various distributed computing platforms is a challenging task from a software engineering perspective. The primary aim of this paper is to demonstrate how the development time to port very large applications to the Computational Grid can be significantly reduced. TOP-C and AMPIC are software packages that have each seen successful applications in their respective domains of parallel computing and process creation/communication over the Computational Grid. We combined the two packages in I man-week, thereby leveraging several man-years of previous independent software development. As a real world test case, the 1,000,000 line Geant4 sequential application was then deployed over the Computational Grid in 3 man-weeks by using TOP-C/AMPIC. The cluster parallelization of Geant4 using TOP-C is now included as part of the Geant44.1 distribution, and the integration of TOP-C/AMPIC and the Globus protocols will additionally enable the use of the fundamental Grid middleware services in the future. (C) 2003 Elsevier Science B.V. All rights reserved.

关键词： Computational Grid master-worker parallelism TOP-C AMPIC Geant4

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Using TOP-C and AMPIC to port large parallel applications to the Computational Grid

Using TOP-C and AMPIC to port large parallel applications to...

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2nd IEEE/ACM international symposium on Cluster Computing and the Grid

ISBN: (纸本)0769515827

关键词： Computational Grid master-worker parallelism TOP-C AMPIC Geant4

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Programming models and system software for future high-end computing systems: Work-in-progress

Programming models and system software for future high-end c...

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international parallel and distributed Processing symposium, IPDPS 2003

作者： Gao, Guang R. Theobald, Kevin B. Govindarajan, R. Leung, Clement Hu, Ziang Wu, Haiping Lu, Jizhu Del Cuvillo, Juan Jacquet, Adeline Janot, Vincent Sterling, Thomas L. Department of Electrical and Computer Engineering University of Delaware NewarkDE19711 United States Center for Advanced Computing Research California Institute of Technology PasadenaCA91125A United States

ISBN: (纸本)0769519261

Future high-end computers which promise very high performance require sophisticated program execution models and languages in order to deal with very high latencies across the memory hierarchy and to exploit massive parallelism. This paper presents our progress in an ongoing research toward this goal. Specifically we develop a suitable program execution model, a high-level programming notation which shields the application developer from the complexities of the architecture, and a compiler and runtime system based on the underlying models. In particular, we propose fine-grain multithreading and thread percolation as key components of our program execution model. We investigate implementing these models and systems on novel architectures such as the HTMT architecture and IBM's Blue Gene. Also, we report early performance prediction of thread percolation and its impact on execution time. © 2003 IEEE.

关键词： Program compilers

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Evolutionary fault recovery in a Virtex FPGA using a representation that incorporates routing

Evolutionary fault recovery in a Virtex FPGA using a represe...

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international parallel and distributed Processing symposium, IPDPS 2003

作者： Lohn, Jason Larchev, Greg De Mara, Ronald Computational Sciences Division NASA Ames Research Center Mail Stop 269-1 Moffett FieldCA94035-1000 United States School of Electrical Engineering and Computer Science University of Central Florida OrlandoFL32816-2450 United States

ISBN: (纸本)0769519261

Most evolutionary approaches to fault recovery in FPGA focus on evolving alternative logic configurations as opposed to evolving the intra-cell routing. Since the majority of transistors in a typical FPGA are dedicated to interconnect, nearly 80% according to one estimate, evolutionary fault-recovery systems should benefit by accommodating routing. In this paper, we propose an evolutionary fault-recovery system employing a genetic representation that takes into account both logic and routing configurations. Experiments were run using a software model of the Xilinx Virtex FPGA. We report that using four Virtex combinational logic blocks, we were able to evolve a 100% accurate quadrature decoder finite state machine in the presence of a stuck-at-zero fault. Evolutionary experiments with the hardware in the loop have begun and we discuss the preliminary results. © 2003 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Sensitivity estimation for magnetic devices using a double-layer model

Sensitivity estimation for magnetic devices using a double-l...

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11th international symposium on Theoretical Electrical engineering

作者： Mueller, C Scheinert, G Uhlmann, FH Objexxts Software GmbH Ltd D-98693 Ilmenau Germany

关键词： Magnetic devices

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