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检索条件"任意字段=PDSE 2000: International Symposium on Software Engineering for Parallel and Distributed Systems"

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Evolutionary fault recovery in a Virtex FPGA using a representation that incorporates routing

Evolutionary fault recovery in a Virtex FPGA using a represe...

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international symposium on parallel and distributed Processing (IPDPS)

作者： J. Lohn G. Larchev R. DeMara Computational Sciences Division NASA Ames Research Center Moffett Field CA USA School of Electrical Engineering and Computer Science University of Central Florida Orlando FL USA

Most evolutionary approaches to fault recovery in FPGA focus on evolving alternative logic configurations as opposed to evolving the intra-cell routing. Since the majority of transistors in a typical FPGA are dedicated to interconnect, nearly 80% according to one estimate, evolutionary fault-recovery systems should benefit by accommodating routing. In this paper, we propose an evolutionary fault-recovery system employing a genetic representation that takes into account both logic and routing configurations. Experiments were run using a software model of the Xilinx Virtex FPGA. We report that using four Virtex combinational logic blocks, we were able to evolve a 100% accurate quadrature decoder finite state machine in the presence of a stuck-at-zero fault. Evolutionary experiments with the hardware in the loop have begun and we discuss the preliminary results.

关键词： Field programmable gate arrays Routing Logic Redundancy Probes Space technology NASA Postal services Computer science Genetics

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Targeting tiled architectures in design exploration

Targeting tiled architectures in design exploration

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international symposium on parallel and distributed Processing (IPDPS)

作者： L. Bossuet W. Burleson G. Gogniat V. Anand A. Laffely J.-L. Philippe LESTER Laboratory University of South Brittany Lorient France Department of Electrical and Computer Engineering University of Massachusetts Amherst USA

Tiled architectures can provide a model for early estimation of global interconnect costs. A design exploration tool for reconfigurable architectures is currently under development at LESTER-UBS. The tool allows various reconfigurable architectures to be compared for different applications and sets of constraints. One of the challenges of the tool is the ability to estimate interconnect costs at a high level of abstraction. This project explores the use of the Adaptive System on a Chip (aSoC) tiled architecture, developed at UMASS as a target architecture for design exploration. aSoC provides an important capability to the LESTER tool by allowing interconnect costs to be modeled very early in the design process by partitioning and placing each portion of the computation into a square tile on a 2D grid. aSoC is primarily an interconnect architecture, based on static scheduling of virtual interconnects onto a highly characterized and regular physical interconnect fabric. aSoC supports a wide variety of cores, including dedicated, hardware programmable and software programmable thus allowing a wide range of design exploration.

关键词： Costs Computer architecture Reconfigurable architectures Adaptive systems Process design Grid computing Physics computing Tiles Processor scheduling Fabrics

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Approximate search engine optimization for directory service

Approximate search engine optimization for directory service

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international symposium on parallel and distributed Processing (IPDPS)

作者： Kai-Hsiang Yang Chi-Chien Pan Tzao-Lin Lee Department of Computer Science and Information Engineering National Taiwan University Taipei Taiwan R.O.C.

ISBN: (纸本)0769519261

Today, in many practical e-commerce systems, the real stored data usually are short strings, such as names, addresses, or other information. Searching data within these short strings is not the same as searching within longer strings. General search engines try their best to scan all long strings (or articles) quickly, and find out the places that match the search conditions. Some great online search algorithms (such as "agrep" as used inside glimpse, or "cgrep " as used inside compressed indices, or 'NR-grep') are proposed for searching without any indices in the sub-linear time O(n). However, for short strings (n is small), the practical performance of algorithms of O(n) and O(n) are much the same. Therefore, suitable indices are necessary to optimize the performance of the search engine. On the other hand, directory services are more and more important because of its optimization for searching data. The data stored in directory servers are almost short strings. The approximate search engine for directory service must take the properties of short strings into considerations. In our previous research, we have designed one approximate search engine especially for short strings by using filters to filter out the possible short strings, and then checking for the answers. However the performance of the previous search engine needs to be enhanced. In this paper, we propose new architecture and algorithm to optimize the performance of searching for directory service.

关键词： Search engines Signal processing algorithms Databases Computer science Filters Pattern matching Telephony Application software Computational biology Pattern recognition

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Scheduling distributed applications: the SimGrid simulation framework 03

Scheduling distributed applications: the SimGrid simulation ...

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IEEE/ACM international symposium on Cluster Computing and the Grid (CCGRID)

作者： A. Legrand L. Marchal H. Casanova Laboratoire de l'Informatique du Parallélisme ÉEcole Normale Supérieure de Lyon France Department of Computer Science and Engineering San Diego Supercomputer Center University of California San Diego San Diego USA

ISBN: (纸本)9780769519197

Since the advent of distributed computer systems an active field of research has been the investigation of scheduling strategies for parallel applications. The common approach is to employ scheduling heuristics that approximate an optimal schedule. Unfortunately, it is often impossible to obtain analytical results to compare the efficacy of these heuristics. One possibility is to conducts large numbers of back-to-back experiments on real platforms. While this is possible on tightly-coupled platforms, it is infeasible on modern distributed platforms (i.e. Grids) as it is labor-intensive and does not enable repeatable results. The solution is to resort to simulations. Simulations not only enables repeatable results but also make it possible to explore wide ranges of platform and application scenarios. In this paper we present the SimGrid framework which enables the simulation of distributed applications in distributed computing environments for the specific purpose of developing and evaluating scheduling algorithms. This paper focuses on SimGrid v2, which greatly improves on the first version of the software with more realistic network models and topologies. SimGrid v2 also enables the simulation of distributed scheduling agents, which has become critical for current scheduling research in large-scale platforms. After describing and validating these features, we present a case study by which we demonstrate the usefulness of SimGrid for conducting scheduling research.

关键词： Optimal scheduling Processor scheduling Computational modeling Application software distributed computing Computer simulation Concurrent computing Network topology Grid computing Computer networks

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Large-scale network simulation: how big? how fast?

Large-scale network simulation: how big? how fast?

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international symposium on Modeling, Analysis and Simulation of Computer and Telecommunication systems (MASCOTS)

作者： R.M. Fujimoto K. Perumalla A. Park H. Wu M.H. Ammar G.F. Riley College Of Computing Georgia Institute of Technology Atlanta GA USA Electrical and Computer Engineering Georgia Institute of Technology Atlanta GA USA

parallel and distributed simulation tools are emerging that offer the ability to perform detailed, packet-level simulations of large-scale computer networks on an unprecedented scale. The state-of-the-art in large-scale network simulation is characterized quantitatively. For this purpose, a metric based on the number of packet transmissions that can be processed by a simulator per second of wallclock time (PTS) is used as a means to quantitatively assess packet-level network simulator performance. An approach to realizing scalable network simulations that leverages existing sequential simulation models and software is described. Results from a recent performance study are presented concerning large-scale network simulation on a variety of platforms ranging from workstations to cluster computers to supercomputers. These experiments include runs utilizing as many as 1536 processors yielding performance as high as 106 million PTS. The performance of packet-level simulations of web and ftp traffic, and denial of service attacks on networks containing millions of network nodes are briefly described, including a run demonstrating the ability to simulate a million web traffic flows in near real-time. New opportunities and research challenges to fully exploit this capability are discussed.

关键词： Large-scale systems Computational modeling Computer simulation Computer networks Analytical models Telecommunication traffic Traffic control Concurrent computing Discrete event simulation Protocols

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A software design model for parallel applications on heterogeneous systems 16

A software design model for parallel applications on heterog...

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16th international parallel and distributed Processing symposium, IPDPS 2002

作者： Dwivedula, M. Hariri, S. Parashar, M. Laboratory Department of Electrical and Computer Engineering University of Arizona TucsonAZ85721 United States Department of Electrical and Computer Engineering CAIP Center Rutgers University 94 Brett Road PiscatawayNJ08854 United States

ISBN: (纸本)0769515738

Overlap of computations and communications is an effective mechanism to improve the performance of parallel/distributed applications significantly. This overlap can be achieved efficiently by using data partitioning and properly scheduling the data transfer. Various asynchronous communication primitives, that are provided by most message passing tools (e.g. PVM, MPI), can be used to implement the required overlapping mechanism. In this paper, we present a design model, the distributed software Design Model (DSDM) and show how it can be applied to optimize parallel/distributed applications. We show through several examples, the Master-Slave Merge Sorting Application and the astrophysical N-Body Problem, how the DSDM can be used to develop efficient and optimized implementations of parallel and distributed algorithms. © 2002 IEEE.

关键词： astrophysical N-body problem asynchronous message passing blocking/nonblocking primitives distributed software Design Model overlap of computation/communication

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Hardware-software Co-reliability in field reconfigurable multi-processor-memory systems 16

Hardware-software Co-reliability in field reconfigurable mul...

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16th international parallel and distributed Processing symposium, IPDPS 2002

作者： Choi, M. Park, N. Lombardi, F. Department of Computer Science Oklahoma State University StillwaterOK74078-1053 United States Department of Electrical and Computer Engineering Northeastern University BostonMA02115 United States

ISBN: (纸本)0769515738

Advances in field reconfigurable technology have made possible the design and implementation of highly flexible parallel multi-processor-memory systems;system reliability is often an important measure of these systems because a degradation of an individual module can unacceptably impair the reliable operation of these systems. System reliability is mainly determined by the hardware (HW) configurations (requested by the software, SW) and the process of field reconfiguration/repair (by utilizing unused processors and memory modules as spares). This is referred to as HW/SW Co-reliability. System configurations are categorized in terms of parallel processor size and processor/memory intensity as affecting the HW/SW Co-reliability. Their characteristics are discussed. A model for HW/SW Co-reliability based on a combinatorial analysis for field reconfigurable multiprocessor-memory systems is then proposed and further validated by extensive parametric simulations, thus allowing the design and implementation of highly reliable field-reconfigurable multiprocessor-memory systems. © 2002 IEEE.

关键词： Field Reconfiguration HW/SW Co-reliability Modular Redundancy Multi-Processor-Memory System

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Multi-level modeling of software on hardware in concurrent computation 16

Multi-level modeling of software on hardware in concurrent c...

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16th international parallel and distributed Processing symposium, IPDPS 2002

作者： Paul, J.M. Suppé, A.J. Adams, H.I. Thomas, D.E. Electrical and Computer Engineering Department Carnegie Mellon University PittsburghPA15213 United States

ISBN: (纸本)0769515738

The fundamental modeling differences between hardware and software modeling can be thought of as reasoning about connectedness vs. reasoning about interleaved (shared) access to resources. A natural design hierarchy for physical systems is component-based because of the existence of a consistent basis for interconnect between design levels. However, performance modeling and design of concurrent, programmable systems require new ways of thinking about what it means to abstract detail, add detail and partition a model of software executing on hardware. We motivate frequency interleaving (FI) as a common simulation foundation for these systems because it resolves flow and partitioning with software on hardware layering. Thus, FI provides a basis for hardware and software designs that do not simply co-execute together in fixed system views or later mappings but to truly be co-designed together from highlevel conceptualizations to low-level implementable models. We include an example of a network switch within a client-server application. © 2002 IEEE.

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Designing energy-efficient software 16

Designing energy-efficient software

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16th international parallel and distributed Processing symposium, IPDPS 2002

作者： Sivasubramaniam, A. Kandemir, M. Vijaykrishnan, N. Irwin, M.J. Dept. of Computer Science and Engineering Pennsylvania State University University ParkPA16802 United States

ISBN: (纸本)0769515738

Energy-efficient system design and optimization is rapidly becoming an important consideration across a spectrum of computing systems - from embedded and mobile devices to high end platforms. This paper presents recent research results and experiences when attempting energy optimization at the software level, which is anticipated to have much more impact than micro-management of resources at the hardware level. © 2002 IEEE.

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An implementation of a distributed algorithm for detection of local knots and cycles in directed graphs based on the CSP model and Java 6

An implementation of a distributed algorithm for detection o...

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6th IEEE international Workshop on distributed Simulation and Real-Time Applications (DS-RT 2002)

作者： de Souza, GP Pfitscher, GH Univ Brasilia Dept Comp Sci BR-70910900 Brasilia DF Brazil

ISBN: (纸本)0769518532

Cycles and knots in directed graphs are problems that can be associated with deadlocks in database and communication systems. Many algorithms to detect cycles and knots in directed graphs were proposed. Boukerche and Tropper have proposed a distributed algorithm that solve the problem in a efficient away. Their algorithm has a message complexity of 2m vs. (at least) 4m for the Chandy and Misra algorithm, where in is the number of links in the graph, and requires 0 (n log n) bits of memory, where n is the number of nodes. We have implemented Boukerche and Tropper's algorithm according to the construction of processes of the CSP model. Our implementation was done. using JCSP, an implementation of CSP for Java, and the results are presented.

关键词： Algorithm design and analysis Communication systems Computer aided software engineering Database systems distributed algorithms Fault tolerant systems Frequency IP networks Java System recovery

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