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Static Analysis for Probabilistic Programs: Inferring Whole Program Properties from Finitely Many Paths

Static Analysis for Probabilistic Programs: Inferring Whole ...

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34th acm sigplan conference on programming language design and implementation (pldi)

作者： Sankaranarayanan, Sriram Chakarov, Aleksandar Gulwani, Sumit Univ Colorado Boulder CO 80309 USA Microsoft Res Redmond WA USA

ISBN: (纸本)9781450320146

We propose an approach for the static analysis of probabilistic programs that sense, manipulate, and control based on uncertain data. Examples include programs used in risk analysis, medical decision making and cyber-physical systems. Correctness properties of such programs take the form of queries that seek the probabilities of assertions over program variables. We present a static analysis approach that provides guaranteed interval bounds on the values (assertion probabilities) of such queries. First, we observe that for probabilistic programs, it is possible to conclude facts about the behavior of the entire program by choosing a finite, adequate set of its paths. We provide strategies for choosing such a set of paths and verifying its adequacy. The queries are evaluated over each path by a combination of symbolic execution and probabilistic volume-bound computations. Each path yields interval bounds that can be summed up with a "coverage" bound to yield an interval that encloses the probability of assertion for the program as a whole. We demonstrate promising results on a suite of benchmarks from many different sources including robotic manipulators and medical decision making programs.

关键词： Probabilistic programming Program Verification Volume Bounding Symbolic Execution Monte-Carlo Sampling

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A new perspective on processing-in-memory architecture design 13

A new perspective on processing-in-memory architecture desig...

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acm sigplan Workshop on Memory Systems Performance and Correctness, MSPC 2013, co-located with the 34th annual acm sigplan conference on programming language design and implementation, pldi

作者： Zhang, Dong Ping Jayasena, Nuwan Lyashevsky, Alexander Greathouse, Joseph Meswani, Mitesh Nutter, Mark Ignatowski, Mike Research Group AMD CA United States

ISBN: (纸本)9781450321037

As computation becomes increasingly limited by data movement and energy consumption, exploiting locality throughout the memory hierarchy becomes critical for maintaining the performance scaling that many have come to expect from the computing industry. Moving computation closer to main memory presents an opportunity to reduce the overheads associated with data movement. We explore the potential of using 3D die stacking to move memory-intensive computations closer to memory. This approach to processing-in-memory addresses some drawbacks of prior research on in-memory computing and appears commercially viable in the foreseeable future. We show promising early results from this approach and identify areas that are in need of research to unlock its full potential. © 2013 acm.

关键词： Memory architecture

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It's alive! Continuous feedback in UI programming

It's alive! Continuous feedback in UI programming

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34th acm sigplan conference on programming language design and implementation, pldi 2013

作者： Burckhardt, Sebastian De Halleux, Peli Moskal, Michal Fähndrich, Manuel McDirmid, Sean Tillmann, Nikolai Kato, Jun Microsoft Research United States University of Tokyo Japan

ISBN: (纸本)9781450320146

Live programming allows programmers to edit the code of a running program and immediately see the effect of the code changes. This tightening of the traditional edit-compile-run cycle reduces the cognitive gap between program code and execution, improving the learning experience of beginning programmers while boosting the productivity of seasoned ones. Unfortunately, live programming is difficult to realize in practice as imperative languages lack well-defined abstraction boundaries that make live programming responsive or its feedback comprehensible. This paper enables live programming for user interface programming by cleanly separating the rendering and non-rendering aspects of a UI program, allowing the display to be refreshed on a code change without restarting the program. A type and effect system formalizes this separation and provides an evaluation model that incorporates the code update step. By putting live programming on a more formal footing, we hope to enable critical and technical discussion of live programming systems. Copyright © 2013 acm.

关键词： Graphical user interfaces

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TRANSIT: Specifying Protocols with Concolic Snippets

TRANSIT: Specifying Protocols with Concolic Snippets

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34th acm sigplan conference on programming language design and implementation (pldi)

作者： Udupa, Abhishek Raghavan, Arun Deshmukh, Jyotirmoy V. Mador-Haim, Sela Martin, Milo M. K. Alur, Rajeev Univ Penn Philadelphia PA 19104 USA

ISBN: (纸本)9781450320146

With the maturing of technology for model checking and constraint solving, there is an emerging opportunity to develop programming tools that can transform the way systems are specified. In this paper, we propose a new way to program distributed protocols using concolic snippets. Concolic snippets are sample execution fragments that contain both concrete and symbolic values. The proposed approach allows the programmer to describe the desired system partially using the traditional model of communicating extended finite-state-machines (EFSM), along with high-level invariants and concrete execution fragments. Our synthesis engine completes an EFSM skeleton by inferring guards and updates from the given fragments which is then automatically analyzed using a model checker with respect to the desired invariants. The counterexamples produced by the model checker can then be used by the programmer to add new concrete execution fragments that describe the correct behavior in the specific scenario corresponding to the counterexample. We describe TRANSIT, a language and prototype implementation of the proposed specification methodology for distributed protocols. Experimental evaluations of TRANSIT to specify cache coherence protocols show that (1) the algorithm for expression inference from concolic snippets can synthesize expressions of size 15 involving typical operators over commonly occurring types, (2) for a classical directory-based protocol, TRANSIT automatically generates, in a few seconds, a complete implementation from a specification consisting of the EFSM structure and a few concrete examples for every transition, and (3) a published partial description of the SGI Origin cache coherence protocol maps directly to symbolic examples and leads to a complete implementation in a few iterations, with the programmer correcting counterexamples resulting from underspecified transitions by adding concrete examples in each iteration.

关键词： Program Synthesis Distributed Protocol Synthesis Cache Coherence Protocols programming by Example

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Halide: A language and Compiler for Optimizing Parallelism, Locality, and Recomputation in Image Processing Pipelines

Halide: A Language and Compiler for Optimizing Parallelism, ...

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34th acm sigplan conference on programming language design and implementation (pldi)

作者： Ragan-Kelley, Jonathan Barnes, Connelly Adams, Andrew Paris, Sylvain Durand, Fredo Amarasinghe, Saman MIT CSAIL United States Adobe United States

ISBN: (纸本)9781450320146

Image processing pipelines combine the challenges of stencil computations and stream programs. They are composed of large graphs of different stencil stages, as well as complex reductions, and stages with global or data-dependent access patterns. Because of their complex structure, the performance difference between a naive implementation of a pipeline and an optimized one is often an order of magnitude. Efficient implementations require optimization of both parallelism and locality, but due to the nature of stencils, there is a fundamental tension between parallelism, locality, and introducing redundant recomputation of shared values. We present a systematic model of the tradeoff space fundamental to stencil pipelines, a schedule representation which describes concrete points in this space for each stage in an image processing pipeline, and an optimizing compiler for the Halide image processing language that synthesizes high performance implementations from a Halide algorithm and a schedule. Combining this compiler with stochastic search over the space of schedules enables terse, composable programs to achieve state-of-the-art performance on a wide range of real image processing pipelines, and across different hardware architectures, including multicores with SIMD, and heterogeneous CPU+GPU execution. From simple Halide programs written in a few hours, we demonstrate performance up to 5x faster than hand-tuned C, intrinsics, and CUDA implementations optimized by experts over weeks or months, for image processing applications beyond the reach of past automatic compilers.

关键词： domain specific language compiler image processing locality parallelism redundant computation optimization GPU vectorization

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Proceedings of the acm sigplan Workshop on Memory Systems Performance and Correctness, MSPC 2013

Proceedings of the ACM SIGPLAN Workshop on Memory Systems Pe...

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acm sigplan Workshop on Memory Systems Performance and Correctness, MSPC 2013, co-located with the 34th annual acm sigplan conference on programming language design and implementation, pldi

ISBN: (纸本)9781450321037

The proceedings contain 12 papers. The topics discussed include: APE: accelerator processor extensions to optimize data-compute co-location;a study of data structures with a deep heap shape;introducing kernel-level page reuse for high performance computing;a low overhead method for recovering unused memory inside regions;software-controlled transparent management of heterogeneous memory resources in virtualized systems;program-centric cost models for locality;a new perspective on processing-in-memory architecture design;a coldness metric for cache optimization;all-window data liveness;software-level scheduling to exploit non-uniformly shared data cache on GPGPU;cache rationing for multicore;and analyzing locality of memory references in GPU architectures.

关键词： Data structures

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CLAP: Recording Local Executions to Reproduce Concurrency Failures

CLAP: Recording Local Executions to Reproduce Concurrency Fa...

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34th acm sigplan conference on programming language design and implementation (pldi)

作者： Huang, Jeff Zhang, Charles Dolby, Julian Hong Kong Univ Sci & Technol Hong Kong Hong Kong Peoples R China

ISBN: (纸本)9781450320146

We present CLAP, a new technique to reproduce concurrency bugs. CLAP has two key steps. First, it logs thread local execution paths at runtime. Second, offline, it computes memory dependencies that accord with the logged execution and are able to reproduce the observed bug. The second step works by combining constraints from the thread paths and constraints based on a memory model, and computing an execution with a constraint solver. CLAP has four major advantages. First, logging purely local execution of each thread is substantially cheaper than logging memory interactions, which enables CLAP to be efficient compared to previous approaches. Second, our logging does not require any synchronization and hence with no added memory barriers or fences;this minimizes perturbation and missed bugs due to extra synchronizations foreclosing certain racy behaviors. Third, since it uses no synchronization, we extend CLAP to work on a range of relaxed memory models, such as TSO and PSO, in addition to sequential consistency. Fourth, CLAP can compute a much simpler execution than the original one, that reveals the bug with minimal thread context switches. To mitigate the scalability issues, we also present an approach to parallelize constraint solving, which theoretically scales our technique to programs with arbitrary execution length. Experimental results on a variety of multithreaded benchmarks and real world concurrent applications validate these advantages by showing that our technique is effective in reproducing concurrency bugs even under relaxed memory models;furthermore, it is significantly more efficient than a state-of-the-art technique that records shared memory dependencies, reducing execution time overhead by 45% and log size by 88% on average.

关键词： Algorithms design Performance Theory Concurrency Bug Reproduction Local Execution Constraint Solving

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SPL^LIFT - Statically Analyzing Software Product Lines in Minutes Instead of Years 13

SPL<SUP>LIFT</SUP> - Statically Analyzing Software Product L...

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34th acm sigplan conference on programming language design and implementation (pldi)

作者： Bodden, Eric Toledo, Tarsis Ribeiro, Marcio Brabrand, Claus Borba, Paulo Mezini, Mira Tech Univ Darmstadt EC SPRIDE Darmstadt Germany IT Univ Copenhagen Copenhagen Denmark Univ Fed Pernambuco Recife PE Brazil Univ Fed Alagoas Maceio Brazil

ISBN: (纸本)9781450320146

A software product line (SPL) encodes a potentially large variety of software products as variants of some common code base. Up until now, re-using traditional static analyses for SPLs was virtually intractable, as it required programmers to generate and analyze all products individually. In this work, however, we show how an important class of existing inter-procedural static analyses can be transparently lifted to SPLs. Without requiring programmers to change a single line of code, our approach SPLLIFT automatically converts any analysis formulated for traditional programs within the popular IFDS framework for inter-procedural, finite, distributive, subset problems to an SPL-aware analysis formulated in the IDE framework, a well-known extension to IFDS. Using a full implementation based on Heros, Soot, CIDE and JavaBDD, we show that with SPLLIFT one can reuse IFDS-based analyses without changing a single line of code. Through experiments using three static analyses applied to four Java-based product lines, we were able to show that our approach produces correct results and outperforms the traditional approach by several orders of magnitude.

关键词： Software product lines inter-procedural static analysis context sensitive flow sensitive design languages Performance

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It's Alive! Continuous Feedback in UI programming

It's Alive! Continuous Feedback in UI Programming

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34th acm sigplan conference on programming language design and implementation (pldi)

作者： Burckhardt, Sebastian Faehndrich, Manuel de Halleux, Peli McDirmid, Sean Moskal, Michal Tillmann, Nikolai Kato, Jun Univ Tokyo Tokyo 1138654 Japan

关键词： languages Human Factors Live programming Graphical User Interface

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Fast RMWs for TSO: Semantics and implementation

Fast RMWs for TSO: Semantics and Implementation

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34th acm sigplan conference on programming language design and implementation (pldi)

作者： Rajaram, Bhargava Nagarajan, Vijay Sarkar, Susmit Elver, Marco Univ Edinburgh Edinburgh EH8 9YL Midlothian Scotland Univ St Andrews St Andrews KY16 9AJ Fife Scotland

ISBN: (纸本)9781450320146

Read-Modify-Write (RMW) instructions are widely used as the building blocks of a variety of higher level synchronization constructs, including locks, barriers, and lock-free data structures. Unfortunately, they are expensive in architectures such as x86 and SPARC which enforce (variants of) Total-Store-Order (TSO). A key reason is that RMWs in these architectures are ordered like a memory barrier, incurring the cost of a write-buffer drain in the critical path. Such strong ordering semantics are dictated by the requirements of the strict atomicity definition (type-1) that existing TSO RMWs use. Programmers often do not need such strong semantics. Besides, weakening the atomicity definition of TSO RMWs, would also weaken their ordering - thereby leading to more efficient hardware implementations. In this paper we argue for TSO RMWs to use weaker atomicity definitions - we consider two weaker definitions: type-2 and type-3, with different relaxed ordering differences. We formally specify how such weaker RMWs would be ordered, and show that type-2 RMWs, in particular, can seamlessly replace existing type-1 RMWs in common synchronization idioms - except in situations where a type-1 RMW is used as a memory barrier. Recent work has shown that the new C/C++ 11 concurrency model can be realized by generating conventional (type-1) RMWs for C/C++ 11 SC-atomic-writes and/or SC-atomic-reads. We formally prove that this is equally valid using the proposed type-2 RMWs;type-3 RMWs, on the other hand, could be used for SC-atomic-reads (and optionally SC-atomic-writes). We further propose efficient microarchitectural implementations for type-2 (type-3) RMWs - simulation results show that our implementation reduces the cost of an RMW by up to 58.9% (64.3%), which translates into an overall performance improvement of up to 9.0% (9.2%) on a set of parallel programs, including those from the SPLASH-2, PARSEC, and STAMP benchmarks.

关键词： design Performance Experimentation Read-Modify-Write (RMW) Total-Store-Order (TSO) Atomics

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