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Lightweight Multi-language Syntax Transformation with Parser Parser Combinators 2019

Lightweight Multi-Language Syntax Transformation with Parser...

40th acm sigplan conference on programming language design and implementation (pldi) part of acm's Federated Computing Research conference (FCRC)

作者： van Tonder, Rijnard Le Goues, Claire Carnegie Mellon Univ Sch Comp Sci Pittsburgh PA 15213 USA

ISBN: (纸本)9781450367127

Automatically transforming programs is hard, yet critical for automated program refactoring, rewriting, and repair. Multi-language syntax transformation is especially hard due to heterogeneous representations in syntax, parse trees, and abstract syntax trees (ASTs). Our insight is that the problem can be decomposed such that (1) a common grammar expresses the central context-free language (CFL) properties shared by many contemporary languages and (2) open extension points in the grammar allow customizing syntax (e.g., for balanced delimiters) and hooks in smaller parsers to handle language-specific syntax (e.g., for comments). Our key contribution operationalizes this decomposition using a Parser Parser combinator (PPC), a mechanism that generates parsers for matching syntactic fragments in source code by parsing declarative user-supplied templates. This allows our approach to detach from translating input programs to any particular abstract syntax tree representation, and lifts syntax rewriting to a modularly-defined parsing problem. A notable effect is that we skirt the complexity and burden of defining additional translation layers between concrete user input templates and an underlying abstract syntax representation. We demonstrate that these ideas admit efficient and declarative rewrite templates across 12 languages, and validate effectiveness of our approach by producing correct and desirable lightweight transformations on popular real-world projects (over 50 syntactic changes produced by our approach have been merged into 40+). Our declarative rewrite patterns require an order of magnitude less code compared to analog implementations in existing, language-specific tools.

关键词： syntax transformation parsers rewriting

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Descend: A Safe GPU Systems programming language

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PROCEEDINGS OF THE acm ON programming languageS-PacmPL 2024年第PLDI期8卷 841-864页

作者： Koepcke, Bastian Gorlatch, Sergei Steuwer, Michel Univ Munster Munster Germany Tech Univ Berlin Berlin Germany

Graphics Processing Units (GPU) offer tremendous computational power by following a throughput oriented paradigm where many thousand computational units operate in parallel. programming such massively parallel hardware is challenging. Programmers must correctly and efficiently coordinate thousands of threads and their accesses to various shared memory spaces. Existing mainstream GPU programming languages, such as CUDA and OpenCL, are based on C/C++ inheriting their fundamentally unsafe ways to access memory via raw pointers. This facilitates easy to make, but hard to detect bugs, such as data races and deadlocks. In this paper, we present Descend: a safe GPU programming language. In contrast to prior safe high-level GPU programming approaches, Descend is an imperative GPU systems programming language in the spirit of Rust, enforcing safe CPU and GPU memory management in the type system by tracking Ownership and Lifetimes. Descend introduces a new holistic GPU programming model where computations are hierarchically scheduled over the GPU's execution resources: grid, blocks, warps, and threads. Descend's extended Borrow checking ensures that execution resources safely access memory regions without data races. For this, we introduced views describing safe parallel access patterns of memory regions, as well as atomic variables. For memory accesses that can't be checked by our type system, users can annotate limited code sections as unsafe. We discuss the memory safety guarantees offered by Descend and evaluate our implementation using multiple benchmarks, demonstrating that Descend is capable of expressing real-world GPU programs showing competitive performance compared to manually written CUDA programs lacking Descend's safety guarantees.

关键词： GPU programming language design memory safety type systems

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ABCD:: Eliminating array bounds checks on demand

<i>ABCD</i>:: Eliminating array bounds checks on demand

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acm sigplan' 00 conference on programming language design and implementation (pldi)

作者： Bodik, R Gupta, R Sarkar, V Univ Wisconsin Madison WI 53706 USA Univ Arizona Tucson AZ 85721 USA IBM Corp TJ Watson Res Ctr Yorktown Hts NY 10598 USA

To guarantee typesafe execution, Java and other strongly typed languages require bounds checking of array accesses. Because array-bounds checks may raise exceptions, they block code motion of instructions with side effects, thus preventing many useful code optimizations, such as partial redundancy elimination or instruction scheduling of memory operations. Furthermore, because it is not expressible at bytecode level, the elimination of bounds checks can only be performed at run time, after the bytecode program is loaded. Using existing powerful bounds-check optimizers at run time is not feasible, however, because they are too heavyweight for the dynamic compilation setting. ABCD is a light-weight algorithm for elimination of Array Bounds Checks on Demand. Its design emphasizes simplicity and efficiency. In essence, ABCD works by adding a few edges to the SSA value graph and performing a simple traversal of the graph. Despite its simplicity, ABCD is surprisingly powerful. On our benchmarks, ABCD removes on average 45% of dynamic bound check instructions, sometimes achieving near-ideal optimization. The efficiency of ABCD stems from two factors. First, ABCD works on a sparse representation. As a result, it requires on average fewer than 10 simple analysis steps per bounds check. Second, ABCD is demand-driven. It can be applied to a set of frequently executed (hot) bounds checks, which makes it suitable for the dynamic-compilation setting, in which compile-time cost is constrained but hot statements are known.

关键词： Java programming language

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Communication optimizations for parallel C programs 98

Communication optimizations for parallel C programs

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Proceedings of the 1998 Annual acm sigplan conference on programming language design and implementation, pldi

作者： Zhu, Yingchun Hendren, Laurie J. McGill Univ Montreal Que Canada

ISBN: (纸本)9780897919876

This paper presents algorithms for reducing the communication overhead for parallel C programs that use dynamically-allocated data structures. The framework consists of an analysis phase called possible-placement analysis, and a transformation phase called communication selection. The fundamental idea of possible-placement analysis is to find all possible points for insertion of remote memory operations. Remote reads are propagated upwards, whereas remote writes are propagated downwards. Based on the results of the possible-placement analysis, the communication selection transformation selects the `best' place for inserting the communication, and determines if pipelining or blocking of communication should be performed. The framework has been implemented in the EARTH-McCAT optimizing/parallelizing C compiler, and experimental results are presented for five pointer-intensive benchmarks running on the EARTH-MANNA distributed-memory parallel architecture. These experiments show that the communication optimization can provide performance improvements of up to 16% over the unoptimized benchmarks.

关键词： C (programming language)

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Wire Sorts: A language Abstraction for Safe Hardware Composition 2021

Wire Sorts: A Language Abstraction for Safe Hardware Composi...

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42nd acm sigplan International conference on programming language design and implementation (pldi)

作者： Christensen, Michael Sherwood, Timothy Balkind, Jonathan Hardekopf, Ben Univ Calif Santa Barbara Dept Comp Sci Santa Barbara CA 93106 USA

ISBN: (纸本)9781450383912

Effective digital hardware design fundamentally requires decomposing a design into a set of interconnected modules, each a distinct unit of computation and state. However, naively connecting hardware modules leads to real-world pathological cases which are surprisingly far from obvious when looking at the interfaces alone and which are very difficult to debug after synthesis. We show for the first time that it is possible to soundly abstract even complex combinational dependencies of arbitrary hardware modules through the assignment of IO ports to one of four new sorts which we call: to-sync, to-port, from-sync, and from-port. This new taxonomy, and the reasoning it enables, facilitates modularity by escalating problematic aspects of module input/output interaction to the language-level interface specification. We formalize and prove the soundness of our new wire sorts, implement them in a practical hardware description language, and demonstrate they can be applied and even inferred automatically at scale. Through an examination of the BaseJump STL, the OpenPiton manycore research platform, and a complete RISC-V implementation, we find that even on our biggest design containing 1.5 million primitive gates, analysis takes less than 31 seconds;that across 172 unique modules analyzed, the inferred sorts are widely distributed across our taxonomy;and that by using wire sorts, our tool is 2.6-33.9x faster at finding loops than standard synthesis-time cycle detection.

关键词： hardware description languages modules composition

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Expressive and safe static reflection with MorphJ 08

Expressive and safe static reflection with MorphJ

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acm sigplan conference on programming language design and implementation

作者： Huang, Shan Shan Smaragdakis, Yannis Georgia Inst Technol Coll Comp Atlanta GA 30332 USA Univ Oregon Dept Comp & Informat Sci Eugene OR 97403 USA

ISBN: (纸本)9781595938602

Recently, language extensions have been proposed for Java and C# to support pattern-based reflective declaration. These extensions introduce a disciplined form of meta-programming and aspect-oriented programming to mainstream languages: They allow members of a class (i.e., fields and methods) to be declared by statically iterating over and pattern-matching on members of other classes. Such techniques, however, have been unable to safely express simple, but common, idioms such as declaring getter and setter methods for fields. In this paper, we present a mechanism that addresses the lack of expressiveness in past work without sacrificing safety. Our technique is based on the idea of nested patterns that elaborate the outer-most pattern with blocking or enabling conditions. We implemented this mechanism in a language, MorphJ. We demonstrate the expressiveness of MorphJ with real-world applications. In particular, the MorphJ reimplementation of DSTM2, a software transactional memory library, reduces 1,107 lines of Java reflection and bytecode engineering library calls to just 374 lines of MorphJ code. At the same time, the MorphJ solution is both high level and safer, as MorphJ can separately type check generic classes and catch errors early. We present and formalize the MorphJ type system, and offer a type-checking algorithm.

关键词： languages object-oriented programming structural abstraction class morphing aspect-oriented programming meta-programming language extensions

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Region inference for an object-oriented language

Region inference for an object-oriented language

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Proceedings of the 2004 acm sigplan conference on programming language design and implementation (pldi'04)

作者： Chin, Wei-Ngan Craciun, Florin Qin, Shengchao Rinard, Martin Computer Science Programme Singapore-MIT Alliance Singapore Department of Computer Science National University of Singapore Singapore Laboratory for Computer Science Massachusetts Inst. of Technology United States

Region-based memory management offers several important potential advantages over garbage collection, including real-time performance, better data locality, and more efficient use of limited memory. Researchers have advocated the use of regions for functional, imperative, and object-oriented languages. Lexically scoped regions are now a core feature of the Real-Time Specification for Java (RTSJ). Recent research in region-based programming for Java has focused on region checking, which requires manual effort to augment the program with region annotations. In this paper, we propose an automatic region inference system for a core subset of Java. To provide an inference method that is both precise and practical, we support classes and methods that are region-polymorphic, with region-polymorphic recursion for methods. One challenging aspect is to ensure region safety in the presence of features such as class sub-typing, method overriding, and downcast operations. Our region inference rules can handle these object-oriented features safely without creating dangling references.

关键词： Object oriented programming

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Armada: Low-Effort Verification of High-Performance Concurrent Programs 2020

Armada: Low-Effort Verification of High-Performance Concurre...

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41st acm sigplan conference on programming language design and implementation (pldi)

作者： Lorch, Jacob R. Chen, Yixuan Kapritsos, Manos Parno, Bryan Qadeer, Shaz Sharma, Upamanyu Wilcox, James R. Zhao, Xueyuan Microsoft Res Redmond WA 98052 USA Univ Michigan Ann Arbor MI 48109 USA Yale Univ New Haven CT 06520 USA Carnegie Mellon Univ Pittsburgh PA 15213 USA Calibra Seattle WA USA Certora San Francisco CA USA

ISBN: (纸本)9781450376136

Safely writing high-performance concurrent programs is notoriously difficult. To aid developers, we introduce Armada, a language and tool designed to formally verify such programs with relatively little effort. Via a C-like language and a small-step, state-machine-based semantics, Armada gives developers the flexibility to choose arbitrary memory layout and synchronization primitives so they are never constrained in their pursuit of performance. To reduce developer effort, Armada leverages SMT-powered automation and a library of powerful reasoning techniques, including rely-guarantee, TSO elimination, reduction, and alias analysis. All these techniques are proven sound, and Armada can be soundly extended with additional strategies over time. Using Armada, we verify four concurrent case studies and show that we can achieve performance equivalent to that of unverified code.

关键词： refinement weak memory models x86-TSO

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Efficient formulation for optimal modulo schedulers

Efficient formulation for optimal modulo schedulers

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Proceedings of the 1997 acm SIGPLAM conference on programming language design and implementation, pldi

作者： Eichenberger, Alexandre E. Davidson, Edward S. North Carolina State Univ Raleigh United States

Modulo scheduling algorithms based on optimal solvers have been proposed to investigate and tune the performance of modulo scheduling heuristics. While recent advances have broadened the scope for which the optimal approach is applicable, this approach increasingly suffers from large execution times. In this paper, we propose a more efficient formulation of the modulo scheduling space that significantly decreases the execution time of solvers based on integer linear programs. For example, the total execution time is reduced by a factor of 8.6 when 782 loops from the Perfect Club, SPEC, and Livermore Fortran Kernels are scheduled for minimum register requirements using the more efficient formulation instead of the traditional formulation. Experimental evidence further indicates that significantly larger loops can be scheduled under realistic machine constraints.

关键词： Computer programming

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Compiling KB-Sized Machine Learning Models to Tiny IoT Devices 2019

Compiling KB-Sized Machine Learning Models to Tiny IoT Devic...

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40th acm sigplan conference on programming language design and implementation (pldi) part of acm's Federated Computing Research conference (FCRC)

作者： Gopinath, Sridhar Ghanathe, Nikhil Seshadri, Vivek Sharma, Rahul Microsoft Res Bengaluru India

ISBN: (纸本)9781450367127

Recent advances in machine learning (ML) have produced KiloByte-size models that can directly run on constrained IoT devices. This approach avoids expensive communication between IoT devices and the cloud, thereby enabling energy-efficient real-time analytics. However, ML models are expressed typically in floating-point, and IoT hardware typically does not support floating-point. Therefore, running these models on IoT devices requires simulating IEEE-754 floating-point using software, which is very inefficient. We present SeeDot, a domain-specific language to express ML inference algorithms and a compiler that compiles SeeDot programs to fixed-point code that can efficiently run on constrained IoT devices. We propose 1) a novel compilation strategy that reduces the search space for some key parameters used in the fixed-point code, and 2) new efficient implementations of expensive operations. SeeDot compiles state-of-the-art KB-sized models to various microcontrollers and low-end FPGAs. We show that SeeDot outperforms 1) software emulation of floating-point (Arduino), 2) high-bitwidth fixed-point (MATLAB), 3) post-training quantization (TensorFlow-Lite), and 4) floating- and fixed-point FPGA implementations generated using high-level synthesis tools.

关键词： Machine Learning IoT device programming language Compiler Fixed-point Microcontroller FPGA

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