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检索条件"任意字段=PLDI 2006 - 2006 ACM SIGPLAN Conference on Programming Language Design and Implementation"

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design and implementation of Sparse Global Analyses for C-like languages 12

Design and Implementation of Sparse Global Analyses for C-li...

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33rd acm sigplan conference on programming language design and implementation

作者： Oh, Hakjoo Heo, Kihong Lee, Wonchan Lee, Woosuk Yi, Kwangkeun Seoul Natl Univ Seoul 151 South Korea

ISBN: (纸本)9781450312059

In this article we present a general method for achieving global static analyzers that are precise, sound, yet also scalable. Our method generalizes the sparse analysis techniques on top of the abstract interpretation framework to support relational as well as non-relational semantics properties for C-like languages. We first use the abstract interpretation framework to have a global static analyzer whose scalability is unattended. Upon this underlying sound static analyzer, we add our generalized sparse analysis techniques to improve its scalability while preserving the precision of the underlying analysis. Our framework determines what to prove to guarantee that the resulting sparse version should preserve the precision of the underlying analyzer. We formally present our framework;we present that existing sparse analyses are all restricted instances of our framework;we show more semantically elaborate design examples of sparse non-relational and relational static analyses;we present their implementation results that scale to analyze up to one million lines of C programs. We also show a set of implementation techniques that turn out to be critical to economically support the sparse analysis process.

关键词： Static analysis abstract interpretation sparse analysis

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Formal loop merging for signal transforms

Formal loop merging for signal transforms

引用

conference on programming language design and implementation

作者： Franchetti, F Voronenko, Y Püschel, M Carnegie Mellon Univ Dept Elect & Comp Engn Pittsburgh PA 15213 USA

A critical optimization in the domain of linear signal transforms, such as the discrete Fourier transform (DFT), is loop merging, which increases data locality and reuse and thus performance. In particular, this includes the conversion of shuffle operations into array reindexings. To date, loop merging is well understood only for the DFT, and only for Cooley-Tukey FFT based algorithms, which excludes DFT sizes divisible by large primes. In this paper, we present a formal loop merging framework for general signal transforms and its implementation within the SPIRAL code generator. The framework consists of Sigma-SPL, a mathematical language to express loops and index mappings;a rewriting system to merge loops in E-SPL;and a compiler that translates Sigma-SPL into code. We apply the framework to DFT sizes that cannot be handled using only the Cooley-Tukey FFT and compare our method to FFTW 3.0.1 and the vendor library Intel MKL 7.2.1. Compared to FFTW our generated code is a factor of 2-4 faster under equal implementation conditions (same algorithms, same unrolling threshold). For some sizes we show a speed-up of a factor of 9 using Bluestein's algorithm. Further, we give a detailed comparison against the Intel vendor library MKL;our generated code is between 2 times faster and 4.5 times slower.

关键词： linear signal transform discrete Fourier transform DFT loop optimization domain-specific language automatic performance tuning

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Automatic Generation of Library Bindings Using Static Analysis 09

Automatic Generation of Library Bindings Using Static Analys...

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acm sigplan conference on programming language design and implementation

作者： Ravitch, Tristan Jackson, Steve Aderhold, Eric Liblit, Ben Univ Wisconsin Dept Comp Sci Madison WI 53706 USA

ISBN: (纸本)9781605583921

High-level languages are growing in popularity. However, decades of C software development have produced large libraries of fast, time-tested, meritorious code that are impractical to recreate from scratch. Cross-language bindings can expose low-level C code to high-level languages. Unfortunately, writing bindings by hand is tedious and error-prone, while mainstream binding generators require extensive manual annotation or fail to offer the language features that users of modem languages have come to expect. We present an improved binding-generation strategy based on static analysis of unannotated library source code. We characterize three high-level idioms that are not uniquely expressible in C's low-level type system: array parameters, resource managers, and multiple return values. We describe a suite of interprocedural analyses that recover this high-level information, and we show how the results can be used in a binding generator for the Python programming language. In experiments with four large C libraries, we find that our approach avoids the mistakes characteristic of hand-written bindings while offering a level of Python integration unmatched by prior automated approaches. Among the thousands of functions in the public interfaces of these libraries, roughly 40% exhibit the behaviors detected by our static analyses.

关键词： FFI foreign function interfaces bindings libraries dataflow analysis modular static program analysis multi-language code reuse

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Concurrency Debugging with Differential Schedule Projections 15

Concurrency Debugging with Differential Schedule Projections

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36th acm sigplan conference on programming language design and implementation

作者： Machado, Nuno Lucia, Brandon Rodrigues, Luis Univ Lisbon Inst Super Tecn INESC ID P-1699 Lisbon Portugal Carnegie Mellon Univ Pittsburgh PA 15213 USA

ISBN: (纸本)9781450334686

We present Symbiosis: a concurrency debugging technique based on novel differential schedule projections (DSPs). A DSP shows the small set of memory operations and data-flows responsible for a failure, as well as a reordering of those elements that avoids the failure. To build a DSP, Symbiosis first generates a full, failing, multithreaded schedule via thread path profiling and symbolic constraint solving. Symbiosis selectively reorders events in the failing schedule to produce a non-failing, alternate schedule. A DSP reports the ordering and data-flow differences between the failing and non-failing schedules. Our evaluation on buggy real-world software and benchmarks shows that, in practical time, Symbiosis generates DSPs that both isolate the small fraction of event orders and data-flows responsible for the failure, and show which event reorderings prevent failing. In our experiments, DSPs contain 81% fewer events and 96% fewer data-flows than the full failure-inducing schedules. Moreover, by allowing developers to focus on only a few events, DSPs reduce the amount of time required to find a valid fix.

关键词： Algorithms design Reliability Concurrency Debugging Symbolic Execution Constraint Solving Differential Schedule Projection

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Latte: A language, Compiler, and Runtime for Elegant and Efficient Deep Neural Networks 16

Latte: A Language, Compiler, and Runtime for Elegant and Eff...

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37th acm sigplan conference on programming language design and implementation

作者： Truong, Leonard Barik, Rajkishore Totoni, Ehsan Liu, Hai Markley, Chick Fox, Armando Shpeisman, Tatiana Univ Calif Berkeley Intel Labs Berkeley CA USA Intel Labs Berkeley CA USA Univ Calif Berkeley Berkeley CA USA

ISBN: (纸本)9781450342612

Deep neural networks (DNNs) have undergone a surge in popularity with consistent advances in the state of the art for tasks including image recognition, natural language processing, and speech recognition. The computationally expensive nature of these networks has led to the proliferation of implementations that sacrifice abstraction for high performance. In this paper, we present Latte, a domain-specific language for DNNs that provides a natural abstraction for specifying new layers without sacrificing performance. Users of Latte express DNNs as ensembles of neurons with connections between them. The Latte compiler synthesizes a program based on the user specification, applies a suite of domain-specific and general optimizations, and emits efficient machine code for heterogeneous architectures. Latte also includes a communication runtime for distributed memory data-parallelism. Using networks described using Latte, we demonstrate 3-6x speedup over Caffe (C++/MKL) on the three state-of-the-art ImageNet models executing on an Intel Xeon E5-2699 v3 x86 CPU.

关键词： Deep Learning Neural Networks Domain Specific language Compiler Optimization

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Expressing and Verifying Probabilistic Assertions 14

Expressing and Verifying Probabilistic Assertions

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35th acm sigplan conference on programming language design and implementation (pldi)

作者： Sampson, Adrian Panchekha, Pavel Mytkowicz, Todd McKinley, Kathryn S. Grossman, Dan Ceze, Luis Univ Washington Seattle WA 98195 USA

ISBN: (纸本)9781450327848

Traditional assertions express correctness properties that must hold on every program execution. However, many applications have probabilistic outcomes and consequently their correctness properties are also probabilistic (e. g., they identify faces in images, consume sensor data, or run on unreliable hardware). Traditional assertions do not capture these correctness properties. This paper proposes that programmers express probabilistic correctness properties with probabilistic assertions and describes a new probabilistic evaluation approach to efficiently verify these assertions. Probabilistic assertions are Boolean expressions that express the probability that a property will be true in a given execution rather than asserting that the property must always be true. Given either specific inputs or distributions on the input space, probabilistic evaluation verifies probabilistic assertions by first performing distribution extraction to represent the program as a Bayesian network. Probabilistic evaluation then uses statistical properties to simplify this representation to efficiently compute assertion probabilities directly or with sampling. Our approach is a mix of both static and dynamic analysis: distribution extraction statically builds and optimizes the Bayesian network representation and sampling dynamically interprets this representation. We implement our approach in a tool called MAYHAP for C and C++ programs. We evaluate expressiveness, correctness, and performance of MAYHAP on programs that use sensors, perform approximate computation, and obfuscate data for privacy. Our case studies demonstrate that probabilistic assertions describe useful correctness properties and that MAYHAP efficiently verifies them.

关键词： languages Reliability Probabilistic programming approximate computing data obfuscation differential privacy sensors symbolic execution

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A provably sound TAL for back-end optimization 03

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conference on programming language design and implementation

作者： Chen, J Wu, DH Appel, AW Fang, H Princeton Univ Princeton NJ 08544 USA Yale Univ New Haven CT 06520 USA

ISBN: (纸本)9781581136623

Typed assembly languages provide a way to generate machine-checkable safety proofs for machine-language programs. But the soundness proofs of most existing typed assembly languages are hand-written and cannot be machine-checked, which is worrisome for such large calculi. We have designed and implemented a low-level typed assembly language (LTAL) with a semantic model and established its soundness from the model. Compared to existing typed assembly languages, LTAL is more scalable and more secure;it has no macro instructions that hinder low-level optimizations such as instruction scheduling;its type constructors are expressive enough to capture dataflow information, support the compiler's choice of data representations and permit typed position-independent code;and its type-checking algorithm is completely syntax-directed. We have built a prototype system, based on Standard ML of New Jersey, that compiles most of core ML to Sparc code. We explain how we were able to make the untyped back end in SML/NJ preserve types during instruction selection and register allocation, without restricting low-level optimizations and without knowledge of any type system pervading the instruction selector and register allocator.

关键词： languages verification typed assembly language proof-carrying code

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Synthesizing Racy Tests 15

Synthesizing Racy Tests

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36th acm sigplan conference on programming language design and implementation

作者： Samak, Malavika Ramanathan, Murali Krishna Jagannathan, Suresh Indian Inst Sci Bangalore 560012 Karnataka India Purdue Univ W Lafayette IN 47907 USA

ISBN: (纸本)9781450334686

Subtle concurrency errors in multithreaded libraries that arise because of incorrect or inadequate synchronization are often difficult to pinpoint precisely using only static techniques. On the other hand, the effectiveness of dynamic race detectors is critically dependent on multithreaded test suites whose execution can be used to identify and trigger races. Usually, such multithreaded tests need to invoke a specific combination of methods with objects involved in the invocations being shared appropriately to expose a race. Without a priori knowledge of the race, construction of such tests can be challenging. In this paper, we present a lightweight and scalable technique for synthesizing precisely these kinds of tests. Given a multithreaded library and a sequential test suite, we describe a fully automated analysis that examines sequential execution traces, and produces as its output a concurrent client program that drives shared objects via library method calls to states conducive for triggering a race. Experimental results on a variety of well-tested Java libraries yield 101 synthesized multithreaded tests in less than four minutes. Analyzing the execution of these tests using an off-the-shelf race detector reveals 187 harmful races, including several previously unreported ones.

关键词： design Reliability Verification Race detection dynamic analysis concurrency

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The Implicit Calculus A New Foundation for Generic programming 12

The Implicit Calculus A New Foundation for Generic Programmi...

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33rd acm sigplan conference on programming language design and implementation

作者： Oliveira, Bruno C. d. S. Schrijvers, Tom Choi, Wontae Lee, Wonchan Yi, Kwangkeun Seoul Natl Univ Seoul 151 South Korea Univ Ghent Ghent Belgium

ISBN: (纸本)9781450312059

Generic programming (GP) is an increasingly important trend in programming languages. Well-known GP mechanisms, such as type classes and the C++0x concepts proposal, usually combine two features: 1) a special type of interfaces;and 2) implicit instantiation of implementations of those interfaces. Scala implicits are a GP language mechanism, inspired by type classes, that break with the tradition of coupling implicit instantiation with a special type of interface. Instead, implicits provide only implicit instantiation, which is generalized to work for any types. This turns out to be quite powerful and useful to address many limitations that show up in other GP mechanisms. This paper synthesizes the key ideas of implicits formally in a minimal and general core calculus called the implicit calculus (lambda(double right arrow)), and it shows how to build source languages supporting implicit instantiation on top of it. A novelty of the calculus is its support for partial resolution and higher-order rules (a feature that has been proposed before, but was never formalized or implemented). Ultimately, the implicit calculus provides a formal model of implicits, which can be used by language designers to study and inform implementations of similar mechanisms in their own languages.

关键词： languages Implicit parameters type classes C plus plus concepts generic programming Haskell Scala

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And Then There Were None: A Stall-Free Real-Time Garbage Collector for Reconfigurable Hardware 12

And Then There Were None: A Stall-Free Real-Time Garbage Col...

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33rd acm sigplan conference on programming language design and implementation

作者： Bacon, David F. Cheng, Perry Shukla, Sunil IBM Research Hawthorne NY USA

ISBN: (纸本)9781450312059

Programmers are turning to radical architectures such as reconfigurable hardware (FPGAs) to achieve performance. But such systems, programmed at a very low level in languages with impoverished abstractions, are orders of magnitude more complex to use than conventional CPUs. The continued exponential increase in transistors, combined with the desire to implement ever more sophisticated algorithms, makes it imperative that such systems be programmed at much higher levels of abstraction. One of the fundamental high-level language features is automatic memory management in the form of garbage collection. We present the first implementation of a complete garbage collector in hardware (as opposed to previous "hardware-assist" techniques), using an FPGA and its on-chip memory. Using a completely concurrent snapshot algorithm, it provides single-cycle access to the heap, and never stalls the mutator for even a single cycle, achieving a deterministic mutator utilization (MMU) of 100%. We have synthesized the collector to hardware and show that it never consumes more than 1% of the logic resources of a high-end FPGA. For comparison we also implemented explicit (malloc/free) memory management, and show that real-time collection is about 4% to 17% slower than malloc, with comparable energy consumption. Surprisingly, in hardware real-time collection is superior to stop-the-world collection on every performance axis, and even for stressful micro-benchmarks can achieve 100% MMU with heaps as small as 1.01 to 1.4 times the absolute minimum.

关键词： design languages Experimentation Performance Block RAM FPGA High Level Synthesis Garbage Collection Real Time

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