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11th acm sigplan International Workshop on the State Of the Art in Program Analysis, SOAP 2022, co-located with the 43rd acm sigplan International conference on programming language design and implementation, pldi 2022

作者： Misu, Md Rakib Hossain Janjanin, Aleksandar Saša Bian, Zhiqiang Burlacu, Valentin-Sebastian Anteski, Naum University College London United Kingdom

ISBN: (纸本)9781450392747

Writing highly maintainable and efficient software code is becoming increasingly difficult, especially while following the rapid, agile development process and working in a distributed team. One of the key indicators of that inefficient software design is a high degree of code coupling, which leads to unwanted side-effects during refactoring and acts as a burden during future development. To alleviate these problems, we developed a visualization tool, ADA, that statically analyzes an open-source repository and seeks to address the issue of code coupling by providing developers with a powerful graphic representation. ADA showcases the relationships and the degree of inter-connectivity between the classes. ADA will ultimately guide developers to instantly locate the coupled area and assist them in decoupling it. © 2022 acm.

关键词： Software design

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EVA: An Encrypted Vector Arithmetic language and Compiler for Efficient Homomorphic Computation 2020

EVA: An Encrypted Vector Arithmetic Language and Compiler fo...

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41st acm sigplan conference on programming language design and implementation (pldi)

作者： Dathathri, Roshan Kostova, Blagovesta Saarikivi, Olli Dai, Wei Laine, Kim Musuvathi, Madan Univ Texas Austin Austin TX 78712 USA Ecole Polytech Fed Lausanne Lausanne Switzerland Microsoft Res Redmond WA USA

ISBN: (纸本)9781450376136

Fully-Homomorphic Encryption (FHE) offers powerful capabilities by enabling secure offloading of both storage and computation, and recent innovations in schemes and implementations have made it all the more attractive. At the same time, FHE is notoriously hard to use with a very constrained programming model, a very unusual performance profile, and many cryptographic constraints. Existing compilers for FHE either target simpler but less efficient FHE schemes or only support specific domains where they can rely on expert-provided high-level runtimes to hide complications. This paper presents a new FHE language called Encrypted Vector Arithmetic (EVA), which includes an optimizing compiler that generates correct and secure FHE programs, while hiding all the complexities of the target FHE scheme. Bolstered by our optimizing compiler, programmers can develop efficient general-purpose FHE applications directly in EVA. For example, we have developed image processing applications using EVA, with a very few lines of code. EVA is designed to also work as an intermediate representation that can be a target for compiling higher-level domain-specific languages. To demonstrate this, we have re-targeted CHET, an existing domain-specific compiler for neural network inference, onto EVA. Due to the novel optimizations in EVA, its programs are on average 5.3x faster than those generated by CHET. We believe that EVA would enable a wider adoption of FHE by making it easier to develop FHE applications and domain-specific FHE compilers.

关键词： Homomorphic encryption compiler neural networks privacy-preserving machine learning

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Optimising aspectJ

Optimising aspectJ

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2005 acm sigplan conference on programming language design and implementation, pldi 05

作者： Avgustinov, Pavel Christensen, Aske Simon Hendren, Laurie Kuzins, Sascha Lhoták, Jennifer Lhoták, Ondřej De Moor, Oege Sereni, Damien Sittampalam, Ganesh Tibble, Julian Programming Tools Group Oxford University United Kingdom dnk can Montreal Que.

AspectJ, an aspect-oriented extension of Java, is becoming increasingly popular. However, not much work has been directed at optimising compilers for AspectJ. Optimising AOP languages provides many new and interesting challenges for compiler writers, and this paper identifies and addresses three such challenges. First, compiling around advice efficiently is particularly challenging. We provide a new code generation strategy for around advice, which (unlike previous implementations) both avoids the use of excessive inlining and the use of closures. We show it leads to more compact code, and can also improve run-time performance. Second, woven code sometimes includes run-time tests to determine whether advice should execute. One important case is the cflow pointcut which uses information about the dynamic calling context. Previous techniques for cflow were very costly in terms of both time and space. We present new techniques to minimise or eliminate the overhead of cflow using both intra- and inter-procedural analyses. Third, we have addressed the general problem of how to structure an optimising compiler so that traditional analyses can be easily adapted to the AOP setting. We have implemented all of the techniques in this paper in abc, our AspectBench Compiler for AspectJ, and we demonstrate significant speedups with empirical results. Some of our techniques have already been integrated into the production AspectJ compiler, ajc 1.2.1. Copyright 2005 acm.

关键词： Java programming language

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Fast RMWs for TSO: Semantics and implementation

Fast RMWs for TSO: Semantics and Implementation

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34th acm sigplan conference on programming language design and implementation (pldi)

作者： Rajaram, Bhargava Nagarajan, Vijay Sarkar, Susmit Elver, Marco Univ Edinburgh Edinburgh EH8 9YL Midlothian Scotland Univ St Andrews St Andrews KY16 9AJ Fife Scotland

ISBN: (纸本)9781450320146

Read-Modify-Write (RMW) instructions are widely used as the building blocks of a variety of higher level synchronization constructs, including locks, barriers, and lock-free data structures. Unfortunately, they are expensive in architectures such as x86 and SPARC which enforce (variants of) Total-Store-Order (TSO). A key reason is that RMWs in these architectures are ordered like a memory barrier, incurring the cost of a write-buffer drain in the critical path. Such strong ordering semantics are dictated by the requirements of the strict atomicity definition (type-1) that existing TSO RMWs use. Programmers often do not need such strong semantics. Besides, weakening the atomicity definition of TSO RMWs, would also weaken their ordering - thereby leading to more efficient hardware implementations. In this paper we argue for TSO RMWs to use weaker atomicity definitions - we consider two weaker definitions: type-2 and type-3, with different relaxed ordering differences. We formally specify how such weaker RMWs would be ordered, and show that type-2 RMWs, in particular, can seamlessly replace existing type-1 RMWs in common synchronization idioms - except in situations where a type-1 RMW is used as a memory barrier. Recent work has shown that the new C/C++ 11 concurrency model can be realized by generating conventional (type-1) RMWs for C/C++ 11 SC-atomic-writes and/or SC-atomic-reads. We formally prove that this is equally valid using the proposed type-2 RMWs;type-3 RMWs, on the other hand, could be used for SC-atomic-reads (and optionally SC-atomic-writes). We further propose efficient microarchitectural implementations for type-2 (type-3) RMWs - simulation results show that our implementation reduces the cost of an RMW by up to 58.9% (64.3%), which translates into an overall performance improvement of up to 9.0% (9.2%) on a set of parallel programs, including those from the SPLASH-2, PARSEC, and STAMP benchmarks.

关键词： design Performance Experimentation Read-Modify-Write (RMW) Total-Store-Order (TSO) Atomics

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Automatic Generation of Efficient Sparse Tensor Format Conversion Routines 2020

Automatic Generation of Efficient Sparse Tensor Format Conve...

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41st acm sigplan conference on programming language design and implementation (pldi)

作者： Chou, Stephen Kjolstad, Fredrik Amarasinghe, Saman MIT CSAIL Cambridge MA 02139 USA Stanford Univ Stanford CA 94305 USA

ISBN: (纸本)9781450376136

This paper shows how to generate code that efficiently converts sparse tensors between disparate storage formats (data layouts) such as CSR, DIA, ELL, and many others. We decompose sparse tensor conversion into three logical phases: coordinate remapping, analysis, and assembly. We then develop a language that precisely describes how different formats group together and order a tensor's nonzeros in memory. This lets a compiler emit code that performs complex remappings of nonzeros when converting between formats. We also develop a query language that can extract statistics about sparse tensors, and we show how to emit efficient analysis code that computes such queries. Finally, we define an abstract interface that captures how data structures for storing a tensor can be efficiently assembled given specific statistics about the tensor. Disparate formats can implement this common interface, thus letting a compiler emit optimized sparse tensor conversion code for arbitrary combinations of many formats without hard-coding for any specific combination. Our evaluation shows that the technique generates sparse tensor conversion routines with performance between 1.00 and 2.01x that of hand-optimized versions in SPARSKIT and Intel MKL, two popular sparse linear algebra libraries. And by emitting code that avoids materializing temporaries, which both libraries need for many combinations of source and target formats, our technique outperforms those libraries by 1.78 to 4.01x for CSC/COO to DIA/ELL conversion.

关键词： sparse tensor conversion sparse tensor assembly sparse tensor algebra sparse tensor formats coordinate remapping notation attribute query language

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SWOOP: Software-Hardware Co-design for Non-speculative, Execute-Ahead, In-Order Cores 2018

SWOOP: Software-Hardware Co-design for Non-speculative, Exec...

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39th acm sigplan conference on programming language design and implementation (pldi)

作者： Tran, Kim-Anh Jimborean, Alexandra Carlson, Trevor E. Koukos, Konstantinos Sjalander, Magnus Kaxiras, Stefanos Uppsala Univ Uppsala Sweden Natl Univ Singapore Singapore Singapore Norwegian Univ Sci & Technol NTNU Trondheim Norway

ISBN: (纸本)9781450356985

Increasing demands for energy eiciency constrain emerging hardware. These new hardware trends challenge the established assumptions in code generation and force us to rethink existing software optimization techniques. We propose a cross-layer redesign of the way compilers and the underlying microarchitecture are built and interact, to achieve both performance and high energy eiciency. In this paper, we address one of the main performance bottlenecksDlast-level cache misses-through a software-hardware co-design. Our approach is able to hide memory latency and attain increased memory and instruction level parallelism by orchestrating a non-speculative, execute-ahead paradigm in software (SWOOP). While out-of-order (OoO) architectures attempt to hide memory latency by dynamically reordering instructions, they do so through expensive, power-hungry, speculative mechanisms. We aim to shift this complexity into software, and we build upon compilation techniques inherited from VLIW, software pipelining, modulo scheduling, decoupled access-execution, and software prefetching. In contrast to previous approaches we do not rely on either software or hardware speculation that can be detrimental to eiciency. Our SWOOP compiler is enhanced with lightweight architectural support, thus being able to transform applications that include highly complex control-low and indirect memory accesses. The efectiveness of our software-hardware co-design is proven on the most limited but energy-eicient micro-architectures, non-speculative, in-order execution (InO) cores, which rely entirely on compile-time instruction scheduling. We show that (1) our approach achieves its goal in hiding the latency of the last-level cache misses and improves performance by 34% and energy eiciency by 23% over the baseline InO core, competitive with an oracle InO core with a perfect last-level cache;(2) can even exceed the performance of the oracle core, by exposing a higher degree of memory and instruction level

关键词： hardware-software co-design compilers memory level parallelism

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Allo: A programming Model for Composable Accelerator design

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PROCEEDINGS OF THE acm ON programming languageS-PacmPL 2024年第PLDI期8卷 593-620页

作者： Chen, Hongzheng Zhang, Niansong Xiang, Shaojie Zeng, Zhichen Dai, Mengjia Zhang, Zhiru Cornell Univ Ithaca NY 14853 USA Univ Sci & Technol China Hefei Peoples R China

Special-purpose hardware accelerators are increasingly pivotal for sustaining performance improvements in emerging applications, especially as the benefits of technology scaling continue to diminish. However, designers currently lack effective tools and methodologies to construct complex, high-performance accelerator architectures in a productive manner. Existing high-level synthesis (HLS) tools often require intrusive source-level changes to attain satisfactory quality of results. Despite the introduction of several new accelerator design languages (ADLs) aiming to enhance or replace HLS, their advantages are more evident in relatively simple applications with a single kernel. Existing ADLs prove less effective for realistic hierarchical designs with multiple kernels, even if the design hierarchy is flattened. In this paper, we introduce Allo, a composable programming model for efficient spatial accelerator design. Allo decouples hardware customizations, including compute, memory, communication, and data type from algorithm specification, and encapsulates them as a set of customization primitives. Allo preserves the hierarchical structure of an input program by combining customizations from different functions in a bottom-up, type-safe manner. This approach facilitates holistic optimizations that span across function boundaries. We conduct comprehensive experiments on commonly-used HLS benchmarks and several realistic deep learning models. Our evaluation shows that Allo can outperform state-of-the-art HLS tools and ADLs on all test cases in the PolyBench. For the GPT2 model, the inference latency of the Allo generated accelerator is 1.7x faster than the NVIDIA A100 GPU with 5.4x higher energy efficiency, demonstrating the capability of Allo to handle large-scale designs.

关键词： Hardware accelerators schedule language accelerator design language compiler optimization

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Co-dfns: Ancient language, modern compiler 1

Co-dfns: Ancient language, modern compiler

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1st acm sigplan International Workshop on Libraries, languages and Compilers for Array programming, ARRAY 2014 - Part of pldi 2014

作者： Hsu, Aaron W. Indiana University United States

ISBN: (纸本)9781450329378

The APL language allows subject matter experts with no computer science experience to create large and complex software implementations of ideas without excessive software engineering and external development costs. The rapid increase in data sizes challenges existing APL systems, which are all interpreters, to scale with the domain expert's problem size. The Co-dfns project, currently in early development stages, focuses on delivering new language innovations and a high-performance compiler for modern APL that enables domain experts to scale their ideas to their data using modern hardware architectures. The Co-dfns language provides concise primitives that allow domain experts to utilize concurrency and explicit task parallelism in their code. The compiler addresses critical performance bottlenecks of the Dyalog APL interpreter, while maintaining strong integration and compatibility with existing APL workflows. Co-dfns will allow domain experts to scale their code more successfully without requiring them to rewrite critical portions of their code in other languages. Early benchmarking efforts indicate that even naive and unoptimized versions of the Co-dfns compiler compete well with Dyalog on code that naturally lends itself to APL.. Copyright © 2014 acm 978-1-4503-2937-8/14/06. 15.00.

关键词： Cost engineering

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Shangri-La: Achieving high performance from compiled network applications while enabling ease of programming

Shangri-La: Achieving high performance from compiled network...

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2005 acm sigplan conference on programming language design and implementation, pldi 05

作者： Chen, Michael K. Li, Xiao Feng Lian, Ruiqi Lin, Jason H. Liu, Lixia Liu, Tao Ju, Roy Microprocessor Technology Labs. Intel Corporation Santa Clara CA United States Intel China Research Center Ltd. Beijing China Institute of Computing Technology China Academy of Sciences Beijing China

programming network processors is challenging. To sustain high line rates, network processors have extremely tight memory access and instruction budgets. Achieving desired performance has traditionally required hand-coded assembly. Researchers have recently proposed high-level programming languages for packet processing, but the challenges of compiling these languages into code that is competitive with hand-tuned assembly remain unanswered. This paper describes the Shangri-La compiler, which accepts a packet program written in a C-like high-level language and applies scalar and specialized optimizations to generate a highly optimized binary. Hot code paths identified by profiling are mapped across processing elements to maximize processor utilization. Since our compilation target has no hardware caches, software-controlled caches are generated for frequently accessed application data structures. Packet handling optimizations significantly reduce perpacket memory access and instruction counts. Finally, a custom stack model maps stack frames to the fastest levels of the target processor's heterogeneous memory hierarchy. Binaries generated by the compiler were evaluated on the Intel 1XP2400 network processor with eight packet processing cores and eight threads per core. Our results show the importance of both traditional and specialized optimization techniques for achieving the maximum forwarding rates on three network applications, L3-Switch, MPLS and Firewall. Copyright 2005 acm.

关键词： Program processors

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Multiprocessor smalltalk: A case study of a multiprocessor-based programming environment 88

Multiprocessor smalltalk: A case study of a multiprocessor-b...

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acm sigplan conference on programming language design and implementation, pldi 1988

作者： Pallas, Joseph Ungar, David Computer Systems Laboratory Stanford University StanfordCA94305 United States

ISBN: (纸本)0897912691

We have adapted an interactive programming system (Smalltalk) to a multiprocessor (the Firefly). The task was not as difficult as might be expected, thanks to the application of three basic strategies: serialization, replication, and reorganization. Serialization of access to resources disallows concurrent access. Replication provides multiple instances of resources when they cannot or should not be serialized. Reorganization allows us to restructure part of the system when the other two strategies cannot be applied. We serialized I/O, memory allocation, garbage collection, and scheduling, we replicated the interpreter process, software caches, and a free-list, and we reorganized portions of the scheduling system to deal with some deep-seated assumptions. Our changes yielded a fairly low static overhead. We attribute our success to the choice of a small, flexible operating system, a set of constraints which simplified the problem, and the versatility of the three strategies for dealing with concurrency. The current system has a moderate amount of overhead when parallelism is being used-25% to 65%. It is acceptable, but we believe it can be improved. © 1988 acm.

关键词： Scheduling

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