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检索条件"任意字段=Pacific-Asia Conference on Knowledge Engineering and Software Engineering"

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Transducer Testing System Based on Virtual Instrument Technology

Transducer Testing System Based on Virtual Instrument Techno...

引用

pacific-asia conference on Circuits, Communications and Systems, PACCS

作者： Jingyi Du Wenqiang Xie Xuan Wang College of Electric & Contorl Engineering Xi''an University of Science and Technology Xi'an Shanxi China

A kind of transducer testing system was designed in this paper. The system utilized data acquisition card and industrial computer as the hardware platform and used LabVIEW as the software platform. The DC motor was used as the load and the high-performance controller which can operate in four quadrants. The system completes dynamic and static performance test of the induction motor and the assessment of the transducer's performance and parameters. The agility and simple of LabVIEW will offer facilities and necessary conditions for the testing system of research and performance.

关键词： Induction motors DC motors Torque Synchronous motors Data acquisition Testing

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A 3.5-GHz SiGe 0.35µm HBT flip-chip assembled on ceramics integrated passive device Doherty power amplifier for SiP integration

A 3.5-GHz SiGe 0.35µm HBT flip-chip assembled on ceramics i...

引用

asia-pacific conference on Microwave

作者： Che-Chung Kuo Po-An Lin Jing-Lin Kuo Hsin-Chia Lu Yue-Ming Hsin Huei Wang Department of Electrical Engineering and Graduate Institute of Communication Engineering National Taiwan University Taipei Taiwan Department of Electrical Engineering National Central University Chungli Taiwan

A 3.5-GHz SiGe 0.35μm HBT Doherty power amplifier (DPA) on ceramics integrated passive device (CIPD) using flip-chip assembled package for system in package (SiP) integration is reported in this paper. The unit cell power amplifier in the DPA demonstrates a saturated output power of 28dBm and 35% PAE at P SAT . When the complete DPA is operated in the quasi-balanced mode, it demonstrates a P SAT of 30.5dBm (PAE = 31%), and a PAE of 8% at OP 1dB . When the complete DPA is operated in the quasi-Doherty mode, it has a P SAT of 30dBm with the same PAE, and an improved PAE of 27% at OP 1dB . The excellent performance is mainly due to the high Q passive elements of CIPD. To the author's knowledge, this is the first demonstration of a watt-level PA using flip-chip assembled on CIPD process with good performance.

关键词： Power amplifiers Silicon germanium Heterojunction bipolar transistors Flip chip Power generation Microwave amplifiers Impedance

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Task-driven Method in Practical Teaching of software engineering

Task-driven Method in Practical Teaching of Software Enginee...

引用

2011 Third pacific-asia conference on Circuits, Communications and System

作者： Dongjin Yu Quan Wang School of Computer Hangzhou Dianzi University Zhijiang College Zhejiang University of Technology

software engineering education is changing at an increasing pace. The practical teaching plays a very important role during the process of software engineering teaching. Traditionally, the practical teaching of software engineering is objective-oriented and usually involves only one single task towards the finally aim. This paper presents the task-driven method and its process framework for the practical teaching of software engineering. Students learn concepts, theorems and methods during the process of finishing multiple and related tasks and in the exploration of corresponding approaches when conducting software projects. The real case led by university teachers and engineers from *** has shown that students are more likely to be engaged while being driven by such multiple organized tasks.

关键词： teaching method,task-driven,practical teaching,software engineering

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Practical IFRS Liability Evaluation System in Japan

Practical IFRS Liability Evaluation System in Japan

引用

The Twelfth asia pacific Industrial engineering ＆ Management Systems conference(APIEMS 2011)

作者： Izumi Yamasaki Kanazawa Seiryo University Kanazawa 920-8620 Japan

In Japan,International Financial Reporting Standards' full-scale implementation is scheduled in two *** finance department of the public-listed companies has already started to review all of the systems in *** finance departments especially focus on estimating the 'fair value' of *** is a difficult task for the finance department to understand IFRS theoretically and to apply practically the computer *** paper focuses on the practical solution to the fair-value of borrowings which is uncommon point of view in Japanese *** is important in this paper to indicate the software which is applicable to a part of usual office *** paper would examine the methods that are in practical use in an example companies and reveal the process of development of the system and the technique for it.

关键词： International Financial Reporting Standards fair value accounting system

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Development and application of Chinese hamster information management system

Development and application of Chinese hamster information m...

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2011 2ND International conference on Innovative Computing and Communication and 2011 asia-pacific conference on Information Technology and Ocean engineering(CICC-ITOE 2011)

作者： Kou Bing Liu Tianfu Song Guohua Chen Zhaoyang Laboratory Animal Center Shan xi Medical University

In order to improve the efficiency of traditional Chinese hamster records management, an information management system of hamsters was introduced in this paper, which combined the idea of software engineering and objectoriented techniques. This system was developed in Visual Basic6.0, based on Access2000. During the management of hamsters, this system improved the efficiency as well as reduced manual mistakes largely which was a satisfied result.

关键词： Chinese hamster software engineering Information Management

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FPGA prototyping using behavioral synthesis for improving video processing algorithm and FHD TV SoC design 11

FPGA prototyping using behavioral synthesis for improving vi...

引用

asia and South pacific Design Automation conference

作者： Masaru Takahashi SoC Software Platform Division Renesas Electronics Corporation Japan

The System on Chip (SoC) can include Full High Definition (FHD) video processing, however the turn around time of algorithm improvement have been long. We provide the new method utilizing the behavioral synthesis. The... 详细信息

ISBN: (纸本)9781424475162

关键词： Field programmable gate arrays Hardware Streaming media Algorithm design and analysis System-on-a-chip IP networks TV

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Integrating Business Processes and Business Rules

Integrating Business Processes and Business Rules

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IEEE asia-pacific conference on Services Computing (APSCC)

作者： Yujing Zhao Dianfu Ma Yongwang Zhao Zhuqing Li Institute of Advanced Computing Technology School of Computer Science and Engineering Beihang University Beijing China

Integration between business processes and business rules is necessary for some applications which not only hold numerous business knowledge or policies but also need the intercommunication among some distributed and heterogeneous components. This paper proposes a main process and multiple bypass process to focus the integration occurring between a bypass process and a rule set. In order to hold the context of some external services decided by business rules, we design a special scope activity in the bypass process. Moreover, an architecture and an algorithm are provided to illustrate the interaction between a BPEL engine and a rule engine for the integrating BPEL processes and business rules.

关键词： Business Engines Web services Fault diagnosis Runtime conferences Telecommunications

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An enhanced leakage-aware scheduler for dynamically reconfigurable FPGAs 11

An enhanced leakage-aware scheduler for dynamically reconfig...

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asia and South pacific Design Automation conference

作者： Jen-Wei Hsieh Yuan-Hao Chang Wei-Li Lee Department of Computer Science and Information Engineering National Taiwan University of Science and Technology Taipei Taiwan Department of Electronic Engineering National Taipei University of Technology Taipei Taiwan

ISBN: (纸本)9781424475162

The FPGAs (Field-Programmable Gate Array) are popular in hardware designs and even hardware/software co-designs. Due to the advance of manufacturing technologies, leakage power has become an important issue in the design of modern FPGAs. In particular, the partially dynamical reconfigurable FPGAs allow the latency between FPGA reconfiguration and task execution for the performance consideration. However, this latency introduces unnecessary leakage power called leakage waste. In this work, we propose a leakage-aware scheduling algorithm to minimize the leakage waste without increasing the schedule length of tasks. In this algorithm, a priority dispatcher with a split-aware placement is proposed to reduce the scheduling complexity with considering the hardware constraints of FPGAs. A series of experiments based on synthetic designs demonstrates that the proposed algorithm could effectively reduce leakage waste with limited sacrifices on the task schedulability.

关键词： Field programmable gate arrays Schedules Hardware Scheduling algorithm Programmable logic arrays Logic gates Job shop scheduling

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Design and realization of Monitoring and management system of large-scale watercraft

Design and realization of Monitoring and management system o...

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2011 International conference on Computers, Communications, Control and Automation

作者： ZHAO Xiaonan GAO Weidong XU Jiren GAO Huaihui WANG Keren College of mechanic Technology university of Hefei Department of inforamtion Eletric engineering Institute of Hefei

ISBN: (纸本)9781612841021

Monitoring and management system of large-sized watercraft is a non-linear complex system with many parameter. Monitoring and management system of large-sized watercraft based on networks is different from other conventional system, its basic idea is: at first large-sized watercraft is divdied into many multi-layer subsystem, computation of every rock-bottom system is finished by networks, and then give effect level of every factor, and then the effect level is taked as input value of the previous subsystem, after neural computation, and we can know evaluation of the previous subsystem of the subsystem, analogy according to this,…, until we give evaluation of the large-sized watercraft. Experiment data and result is the same as the reslult the system give. knowledge library of the system is easy to renew and maintain, and enhance self-learning ability of the system, and avoid the problem of "knowlegye explosion" in conventional expert system.

关键词： neural networks watercraft Monitoring management

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The alarms project: A hardware/software approach to addressing parameter variations 11

The alarms project: A hardware/software approach to addressi...

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asia and South pacific Design Automation conference

作者： David Brooks Computer Science School of Engineering and Applied Sciences Harvard University Cambridge MA USA

ISBN: (纸本)9781424475162

Summary form only given. Parameter variations (process, voltage, and temperature) threaten continued performance scaling of power-constrained computer systems. As designers seek to contain the power consumption of microprocessors through reductions in supply voltage and power-saving techniques such as clock-gating, these systems suffer increasingly large power supply fluctuations due to the finite impedance of the power supply network. These supply fluctuations, referred to as voltage emergencies, must be managed to guarantee correctness. Traditional approaches to address this problem incur high-cost or compromise power/performance efficiency. Our research seeks ways to handle these alarm conditions through a combined hardware/software approach, motivated by root cause analysis of voltage emergencies revealing that many of these events are heavily linked to both program control flow and microarchitectural events (cache misses and pipeline flushes). This talk will discuss three aspects of the project: (1) a fail-safe mechanism that provides hardware guaranteed correctness; (2) a voltage emergency predictor that leverages control flow and microarchitectural event information to predict voltage emergencies up to 16 cycles in advance; and (3) a proof-of-concept dynamic compiler implementation that demonstrates that dynamic code transformations can be used to eliminate voltage emergencies from the instruction stream with minimal impact on performance..

关键词： Automatic voltage control Microarchitecture software Computer architecture Microprocessors Hardware

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