In this paper, it is shown that, through the use of model- integrated program synthesis (MIPS), parallel real-time implementations of imageprocessing data flows can be synthesized from high level graphical specificat...
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Encodings of N-dimensional images on planar screens are studied from the standpoint of their suitability for reduction of N-dimensional imageprocessing to 2-dimensional one. Such a reduction, if possible, would allow...
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The paper introduces a software architecture to support a user from the imageprocessing community in the development of time-constrained imageprocessing applications on parallel computers. The architecture is based ...
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This paper presents the implementation of virtual topologies on top of PVM for developing parallel portable imageprocessing on coarse grained machines. It allows the user to define a high level logical numbering to m...
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The problem of shrinking the connected components of binary images to small residues is addressed. A new parallel algorithm is presented with the lowest known worst case time complexity as measured by iteration counts...
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We have constructed a prototype imageprocessing board containing 384 processors In 8 VLSI chips. The goal of the prototype is to show how fine grain parallelism present in imageprocessing applications can be exploit...
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ISBN:
(纸本)0819425885
We have constructed a prototype imageprocessing board containing 384 processors In 8 VLSI chips. The goal of the prototype is to show how fine grain parallelism present in imageprocessing applications can be exploited by using lots of simple processors inter-connected in clever ways. Each processor has a 16-bit data path, a simple instruction set containing 12 instructions, a simple control unit, and a scan chain for loading data and program, Each VLSI chip, called PADDI-2, contains 48 processors, The programming model used for the processors is MIMD. Each processor has 8 words in the instruction memory. There are internal registers and queues in a processor for storing data and partial results. Data is assumed to be entering the system as a stream and processed by the processors. Each VLSI chip is connected to an external memory (64K x 16). a hardware synchronization mechanism is used for communication between processors;memory, and the external environment. If a sender and receiver is within the same chip, communication can be done in one cycle by the hierarchical interconnect bus structure, Programming the processors and the interconnections are done at compile time. The board is interfaced to a Sun SPARCstation using the SBus. Video input and output is supported by the board and field buffers are used for buffering. Software tools for checking the board, running test programs at the assembly language level, and Libraries for application development have been produced. imageprocessing applications are currently under development. The board is available for experimentation over the Internet. Further details are available from the project web page (http://***/spartan).
The generalized matrix product includes in its formulation many common array manipulations. It also provides a framework for the expression of a number of important imageprocessing algorithms. It is shown that the ge...
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Edge detection is an important first step in many vision tasks where its improvements in speed and efficiency present a continuous challenge for developers of high-speed image recognizers. Classical techniques for acc...
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We describe a dynamic load-balancing algorithm for ray-tracing by progressive refinement on a distributed-memory parallel computer. parallelization of progressive ray-tracing for single images is difficult because of ...
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ISBN:
(纸本)1581130104
We describe a dynamic load-balancing algorithm for ray-tracing by progressive refinement on a distributed-memory parallel computer. parallelization of progressive ray-tracing for single images is difficult because of the inherent sequential nature of the sample location generation process, which is optimized (and different) for any given image. parallelization of progressive ray-tracing when generating image sequences at a fixed interactive rate is even more difficult, because of the time and synchronization constraints imposed on the system. We show how to overcome these problems, which, to the best of our knowledge, have not been treated before. Exploiting the temporal coherence between frames enables us to both accelerate rendering and improve the load-balance throughout the sequence. Our dynamic load-balance algorithm, a blend of local and global methods, accounting not only for rendering performance, but also communication overheads and synchronization issues, is shown to be robust to the harsh environment imposed by a time-critical application, such as the one we consider.
A new algorithm to compute the motion vector has been developed based on the block-matching approach in which bands are used instead of blocks. The new band-matching algorithm (BDMA) offers better performance than bot...
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