We consider the problem of indexing a set of objects moving in d-dimensional spaces along linear trajectories. A simple external-memory indexing scheme is proposed to efficiently answer general range queries. The foll...
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We consider the problem of indexing a set of objects moving in d-dimensional spaces along linear trajectories. A simple external-memory indexing scheme is proposed to efficiently answer general range queries. The following are examples of the queries that can be answered by the proposed method: report all moving objects that will ( i) pass between two given points within a specified time interval;( ii) become within a given distance from some or all of a given set of other moving objects. Our scheme is based on mapping the objects to a dual space, where queries about moving objects are transformed into polyhedral queries concerning their speeds and initial locations. We then present a simple method for answering such polyhedral queries, based on partitioning the space into disjoint regions and using a B+-tree to index the points in each region. By appropriately selecting the boundaries of each region, we guarantee an average search time that matches a known lower bound for the problem. Specifically, for a fixed d, if the coordinates of a given set of N points are statistically independent, the proposed technique answers polyhedral queries, on the average, in O(( N/B)(1-1/d) center dot ( log(B) N)(1/d) + K/B) I/ O's using O(N/B) space, where B is the block size, and K is the number of reported points. Our approach is novel in that, while it provides a theoretical upper bound on the average query time, it avoids the use of complicated data structures, making it an effective candidate for practical applications. The proposed index is also dynamic in the sense that it allows object insertion and deletion in an amortized update cost of logB( N) I/ O's. Experimental results are presented to show the superiority of the proposed index over other methods based on R-trees.
Multi-Processor System-on-Chip (MPSoC) represents today the main trend for future architectural designs. Nonetheless, the scheduling of tasks on these distributed systems is a major problem since it has a central impa...
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Multi-Processor System-on-Chip (MPSoC) represents today the main trend for future architectural designs. Nonetheless, the scheduling of tasks on these distributed systems is a major problem since it has a central impact on global performances. This problem is known to be NP-complete and only approximate methods can be used. In the past, to approach optimal results, many heuristics have been proposed. But their complexity continue to increase, without considering efficient HW implementations. The novel scheduling policy, introduced in this paper, finds an interesting trade off between performance and complexity. Our list scheduling heuristic, called LLD, can near-optimally compute non-malleable tasks on multiple processing elements to minimize the schedule length with a low complexity. The comparison study achieved with already proposed algorithms shows that the LLD scheduling algorithm significantly overcomes the previous approaches in terms of processing element occupation as well as overall execution time.
Fingerprint verification is one of the most reliable personal identification methods in biometrics. In this paper, an effective fingerprint verification system is presented. We describe an enhanced fingerprint verific...
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Fingerprint verification is one of the most reliable personal identification methods in biometrics. In this paper, an effective fingerprint verification system is presented. We describe an enhanced fingerprint verification system consisting of image pre-processing, feature extraction and matching processes. Improved image pre-processing and broken ridge reconnection methods are proposed. In this paper, we also describe the design and implementation of a fingerprint verification system on SoC
This paper describes the design and implementation of an address generator for stream-based computation. The unit can generate addresses by a 1, 2 or 3-dimensional mapping from a linear data string in memory. A proces...
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This paper describes the design and implementation of an address generator for stream-based computation. The unit can generate addresses by a 1, 2 or 3-dimensional mapping from a linear data string in memory. A processing unit will get the required data in a continuous stream without empty time slots, even when switching between addressing algorithms. Each algorithm is specified by a set of parameters loaded into FIFOs in background. The unit is specified by VHDL, simulated, synthesized and implemented on an FPGA of type Xilinx Virtex-ii Pro. A speed of 144 MHz is obtained for generating 36 bit addresses. Ideas for expanding the flexibility of the unit are discussed.
Throughout this paper a catenation between the universal paradigm of cellular nonlinear networks (CNN) and the innovative approach of grid computing is given. CNN are a massive parallel solution for solving non-linear...
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Throughout this paper a catenation between the universal paradigm of cellular nonlinear networks (CNN) and the innovative approach of grid computing is given. CNN are a massive parallel solution for solving non-linear problems, modelling complex phenomena in medicine, physics and data analysis as well as for powerful imageprocessing and recognition systems. They usually are simulated on local computer systems or built as dedicated VLSI-implementations. However, the research of complex CNN structures and settings require massive computing power and thus can benefit from multi-system open architectures which can be provided by the grid approach. Propositions of two different realizations with grid architecture in mind are given by introducing an algorithm of implementing such methods in a CNN software simulator. First a brief introduction to CNN is given. Afterwards, problems for the current determination of such networks are discussed
Hybrid chips containing both CPU's and FPGA components promise the potential of providing a unified platform for seamless implementation of hardware and software co-designed components. Realizing the potential of ...
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Hybrid chips containing both CPU's and FPGA components promise the potential of providing a unified platform for seamless implementation of hardware and software co-designed components. Realizing the potential of these new hybrid chips requires new high level programming model capabilities that support a far more integrated view of the CPU and FPGA components than is achievable with current methods. The KU hybrid threads project has been investigating extending the familiar multithreaded programming model across this CPU/FPGA boundary to support both FPGA based hardware and CPU based software threads. Adopting this generalized multithreaded model can lead to programming productivity improvement, while at the same time providing the benefit of customized hardware from within a familiar software programming model. In this paper we present an application study of our hybrid multithreaded model. We have implemented several image-processing functions in both hardware and software, but from within the common multithreaded programming model on a XILINX V2P7 FPGA. This example demonstrates hardware and software threads executing concurrently using standard multithreaded synchronization primitives transforming real-time images captured by a camera and display it on a workstation.
This paper presents a linear complexity mehtod for real-time stereo matching, in which the processing time is only dependent on the image resolution. Regions along each epipolar line are indexed to produce the dispari...
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This paper presents a linear complexity mehtod for real-time stereo matching, in which the processing time is only dependent on the image resolution. Regions along each epipolar line are indexed to produce the disparity map, instead of searching for the best match. Current local methods have non-linear complexity, as they all rely on searching through a correlation space. The present method is limited to a parallel camera setup, because all disparities must occur in the same direction. A continuity constraint is applied in order to remove false matches. The resulting map is semi-dense, but disparities are well distributed. Experimental results on standard datasets reach around 90% of accuracy using the same parameters in all tests.
This paper presents the hardware implementation of a feature density and distribution algorithm used for autonomous robot navigation. This algorithm is implemented on a Memec Virtex-ii board, taking advantage of the p...
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This paper presents the hardware implementation of a feature density and distribution algorithm used for autonomous robot navigation. This algorithm is implemented on a Memec Virtex-ii board, taking advantage of the parallelism to decrease the processing time and complexity of the algorithm. By comparing consecutive frames against each other and calculating the expansion rate of the features found in the images, we are able to determine how far away we are from the objects we are viewing. This rate of expansion is found by performing a linear search between the two images, using a scalar and a shift to find the best match of the feature between the two images. Once this match is found, a time to impact in terms of frames is calculated and with such information, the robot is able to discover the distance to the object and make plans accordingly.
Facial recognition is applied in a wide range of security systems, and has been studied since the 1970s, with extensive research into and development of digital processing. However, there is only available a 1:1 verif...
Facial recognition is applied in a wide range of security systems, and has been studied since the 1970s, with extensive research into and development of digital processing. However, there is only available a 1:1 verification system combined with ID card identification, or an ID‐less system with a small number of images in the database. The number of images that can be stored is limited, and recognition has to be improved to account for photos taken at different angles. Commercially available facial recognition systems for the most part utilize digital computers performing electronic pattern *** contrast, optical analog operations can process two‐dimensional images instantaneously in parallel using a lens‐based Fourier transform function. In the 1960s two methods were proposed, the Vanderlugt correlator and the joint transform correlator (JTC). We present a new scheme using a multi‐channel parallel JTC to make better use of spatial parallelism, through the use of a diffraction‐type multi‐level zone‐plate array to extend a single‐channel JTC. Our project’s objectives were: (i) to design a matched filter which equips the system with high recognition capability at a faster calculation speed by analyzing the spatial frequency of facial image elements, and (ii) to create a four‐channel Vanderlugt correlator with super‐high‐speed (1000 frame/s) optical parallel facial recognition system, robust enough for 1:N identification, for a large database with 4000 images. Automation was also achieved for the entire process via a practical controlling system. The achieved super‐high‐speed facial recognition system based on optical parallelism is faster in its processing time than the JTC optical correlator.
The mosaic method of the multi-viewpoint pictures provides a quick;practical means to obtain the multi-viewpoint panoramic image. It is a kind of image-based rendering methods, which joints the texture of real world i...
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ISBN:
(纸本)1932415262
The mosaic method of the multi-viewpoint pictures provides a quick;practical means to obtain the multi-viewpoint panoramic image. It is a kind of image-based rendering methods, which joints the texture of real world images. In this paper an image geometrical mosaic model of the overlapping images is constructed, a smooth mosaic method is proposed, and an experimental result is given.
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