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Not All SWAPs Have the Same Cost: A Case for Optimization-Aware Qubit Routing 28

Not All SWAPs Have the Same Cost: A Case for Optimization-Aw...

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28th Annual IEEE International symposium on high-performance computer architecture (HPCA)

作者： Liu, Ji Li, Peiyi Zhou, Huiyang North Carolina State Univ Raleigh NC 27695 USA

ISBN: (纸本)9781665420273

Despite rapid advances in quantum computing technologies, the qubit connectivity limitation remains to be a critical challenge. Both near-term NISQ quantum computers and relatively long-term scalable quantum architectures do not offer full connectivity. As a result, quantum circuits may not be directly executed on quantum hardware, and a quantum compiler needs to perform qubit routing to make the circuit compatible with the device layout. During the qubit routing step, the compiler inserts SWAP gates and performs circuit transformations. Given the connectivity topology of the target hardware, there are typically multiple qubit routing candidates. the state-of-the-art compilers use a cost function to evaluate the number of SWAP gates for different routes and then select the one with the minimum number of SWAP gates. After qubit routing, the quantum compiler performs gate optimizations upon the circuit with the newly inserted SWAP gates. In this paper, we observe that the aforementioned qubit routing is not optimal, and qubit routing should not be independent on subsequent gate optimizations. We find that with the consideration of gate optimizations, not all of the SWAP gates have the same basis-gate cost. these insights lead to the development of our qubit routing algorithm, NASSC (Not All Swaps have the Same Cost). NASSC is the first algorithm that considers the subsequent optimizations during the routing step. Our optimization-aware qubit routing leads to better routing decisions and benefits subsequent optimizations. We also propose a new optimization-aware decomposition for the inserted SWAP gates. Our experiments show that the routing overhead compiled with our routing algorithm is reduced by up to 69.30% (21.30% on average) in the number of CNOT gates and up to 43.50% (7.61% on average) in the circuit depth compared with the state-of-the-art scheme, SABRE.

关键词： quantum computing compiler optimization qubit routing

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DCT Implementation on a Custom FPGA RISC-V Processor 65

DCT Implementation on a Custom FPGA RISC-V Processor

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65th International symposium ELMAR, ELMAR 2023

作者： Harmina, Tomislav Hofman, Daniel Benjak, Jakov University of Zagreb Faculty of Electrical Engineering and Computing Zagreb Croatia

ISBN: (纸本)9798350325126

this paper presents our implementation of an Out-of-Order RISC-V core design. the increasing relevance of open-standard computer architectures and corresponding tools makes the development of custom hardware an increasingly attractive alternative to off-the-shelf components. RISC-V is such an open Instruction Set architecture (ISA) that has become widely used in recent years, especially in low-cost microcontrollers, but also in high-performance computing in recent years. Here we showcase a custom-developed core capable of executing the Discrete Cosine Transform algorithm which gives the core potential uses in image and video processing. Problems with developing such a core are presented and future possibilities and improvements are discussed. © 2023 IEEE.

关键词： computer architecture

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Hierarchical Sketch: An Efficient Solution for threshold-t Flows Measurement in high-Speed Networks 21

Hierarchical Sketch: An Efficient Solution for Threshold-t F...

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21st IEEE International symposium on Parallel and Distributed Processing with Applications, 13th IEEE International Conference on Big Data and Cloud computing, 16th IEEE International Conference on Social computing and Networking and 13th International Conference on Sustainable computing and Communications, ISPA/BDCloud/SocialCom/SustainCom 2023

作者： Han, Yifan Huang, He Du, Yang Sun, Yu-E Liu, Jia Xu, Hongli Soochow University School of Computer Science and Technology China Soochow University School of Rail Transportation China Nanjing University State Key Laboratory for Novel Software Technology China University of Science and Technology of China School of Computer Science and Technology China

ISBN: (纸本)9798350329223

Per-flow size measurement has wide applications in data center networks, such as flow scheduling, anomaly detection, and traffic engineering. To fit the module into limited on-chip memory and catch up with the line speed, existing works either use the bit sharing scheme to compress the flow information or require complex calculations to screen out large flows, resulting in substantial accuracy loss or heavy memory accesses, especially failing to measure medium-sized flows accurately, which are meaningful for practical applications such as usage accounting and billing. In light of this, we propose a new Hierarchical Sketch that adopts a hybrid on-chip/off-chip architecture to detect and estimate the flows whose size exceeds the threshold t (threshold-t flows for short) to cover both large and medium-sized flows. In Hierarchical Sketch, we design an on-chip bucket array together with an adaptive update scheme to record potential candidates for threshold-t flows within one memory access as well as filter out unwanted flows. Besides, the flow records are downloaded to off-chip space for high memory efficiency and supporting online queries. We also implement a prototype on the NetFPGA development platform. Experimental results show that Hierarchical Sketch is up to 72.61% more accurate and 245% faster than the best baseline. © 2023 IEEE.

关键词： high speed networks

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Adaptive Splitting Algorithm for Neural Network Modelling in AMP 21

Adaptive Splitting Algorithm for Neural Network Modelling in...

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作者： Zhang, Kaifei Ma, Yuxiang Wu, Yulei Chen, Tao Ma, Huijie Henan University School of Computer and Information Engineering Kaifeng475004 China University of Bristol School of Electrical Electronic and Mechanical Engineering BristolBS8 1UB United Kingdom

ISBN: (纸本)9798350329223

Artificial Intelligence algorithms usually consume a lot of energy and computing resources during training, so data is usually sent to high-performance devices to complete model training. However, such a computing mode cannot make good use of computing resources in the network and is not conducive to the privacy protection of user information. In recent years, some studies have used end devices to participate in model training, among which federated learning is a typical representative. Due to the heterogeneous computing resources of the end devices, how to split the neural network model to achieve an effective balance between training time and energy consumption is an important issue. In this paper, we propose a novel model splitting method that includes the steps of collecting data, correcting the data, and determining the splitting layers to complete the splitting learning. We consider four factors (training time, energy consumption, CPU utilisation, and memory utilisation) to jointly decide the splitting layer and propose a scheme for adaptively revising the model. We use the VGG16 model for evaluation. the results show that the efficiency of our method is improved by 64.5% compared to the recently proposed ARES scheme. At the same time, our proposed method does not affect the convergence and accuracy of the model. © 2023 IEEE.

关键词： Neural network models

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Parallel Integrity Authentication Data Structure Construction for Encrypted Range Queries 21

Parallel Integrity Authentication Data Structure Constructio...

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作者： Wang, Zhaokang Pan, Jiahui Zhou, Lu Zhang, Zhonghui Ji, Caocong Nanjing University of Aeronautics and Astronautics College of Computer Science and Technology Nanjing China

ISBN: (纸本)9798350329223

With the rapid growth of cloud computing, outsourcing databases to cloud servers is becoming increasingly popular. Query integrity authentication is an effective technique to obtain reliable query results from untrusted clouds. ServeDB (Wu et al., ICDE 2019) is a state-of-the-art system that provides integrity authentication for encrypted range queries. However, ServeDB is a serial system. the high construction cost of its authentication data structure SVETree is the main performance bottleneck that limits its scalability to large datasets. In this study, we overcome the scalability limitation by parallelizing the SVETree construction workflow using the MapReduce framework. We propose the link-free storage layout to store the tree-based SVETree structure in a distributed key-value storage. the parallel SVETree construction algorithm reduces the communication latency of the key-value storage with the batch put/get optimization. the algorithm balances the workload of different tree nodes with the record-centric parallelization optimization. Furthermore, it avoids triggering out-of-core shuffles with the multi-round in-memory shuffle technique. the experimental results show that the parallel algorithm running on 128 cores achieves a 52.7 × speedup over the original serial algorithm. the parallel algorithm exhibits near-linear data and machine scalability. © 2023 IEEE.

关键词： MapReduce

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QULATIS: A Quantum Error Correction Methodology toward Lattice Surgery 28

QULATIS: A Quantum Error Correction Methodology toward Latti...

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28th Annual IEEE International symposium on high-performance computer architecture (HPCA)

作者： Ueno, Yosuke Kondo, Masaaki Tanaka, Masamitsu Suzuki, Yasunari Tabuchi, Yutaka Univ Tokyo Grad Sch Informat Sci & Technol Tokyo Japan Keio Univ Fac Sci & Technol Tokyo Japan RIKEN Ctr Quantum Comp Tokyo Japan Nagoya Univ Grad Sch Engn Nagoya Aichi Japan NTT Comp & Data Sci Labs Tokyo Japan JST PRESTO Tokyo Japan

ISBN: (纸本)9781665420273

Due to the high error rate of a qubit, detecting and correcting errors on it is essential for fault-tolerant quantum computing (FTQC). Surface code (SC) associated with its decoding algorithm is one of the most promising quantum error correction (QEC) methods because it has high fidelity and requires only nearest neighbor qubits connectivity. To realize FTQC, we need a decoder circuit capable of not only QEC in a 3-D lattice to deal with errors in measurement on ancillary qubits but also quantum operations on logically constructed qubits. Whereas several methods to perform logical operations on SC, such as lattice surgery (LS), are known, no practical decoders supporting them have been proposed yet. One of the most promising QC implementations today is made up of superconducting qubits that are located in a cryogenic environment. To reduce the hardware complexity of QC and latency of QEC, we are supposed to perform QEC in a cryogenic environment. Hence a power-efficient decoder is required due to the limited power budget inside a dilution refrigerator. In this paper, we propose an online-QEC algorithm that supports LS with a practical decoder circuit, as well as a new FTQC architecture. We design a key building block of the proposed architecture with a hybrid of SFQ- and Cryo-CMOS-based digital circuits and evaluate it with a SPICE-level simulation. Each logic element includes about 2400 Josephson junctions, and power consumption is estimated to be 2.07 mu W when operating with a 2 GHz clock frequency. We evaluate the decoder performance by a quantum error simulator for an essential operation of LS with code distances up to 11, and it achieves a 0.6% accuracy threshold. In an LS-based architecture further supporting a magic-state distillation protocol, which is expected to run for near-term universal quantum computing, we evaluate the QEC performance and power consumption of the architecture and show that it is practical to be operated in 4-K temperature region of a

关键词： Quantum computing Quantum Error Correction Single flux quantum (SFQ)

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Cascading Structured Pruning: Enabling high Data Reuse for Sparse DNN Accelerators 22

Cascading Structured Pruning: Enabling High Data Reuse for S...

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49th IEEE/ACM Annual International symposium on computer architecture (ISCA)

作者： Hanson, Edward Li, Shiyu Li, Hai 'Helen' Chen, Yiran Duke Univ Durham NC 27706 USA

ISBN: (纸本)9781450386104

performance and efficiency of running modern Deep Neural Networks (DNNs) are heavily bounded by data movement. To mitigate the data movement bottlenecks, recent DNN inference accelerator designs widely adopt aggressive compression techniques and sparse-skipping mechanisms. these mechanisms avoid transferring or computing with zero-valued weights or activations to save time and energy. However, such sparse-skipping logic involves large input buffers and irregular data access patterns, thus precluding many energy-efficient data reuse opportunities and dataflows. In this work, we propose Cascading Structured Pruning (CSP), a technique that preserves significantly more data reuse opportunities for higher energy efficiency while maintaining comparable performance relative to recent sparse architectures such as SparTen. CSP includes the following two components: At algorithm level, CSP-A induces a predictable sparsity pattern that allows for low-overhead compression of weight data and sequential access to both activation and weight data. At architecture level, CSP-H leverages CSP-A's induced sparsity pattern with a novel dataflow to access unique activation data only once, thus removing the demand for large input buffers. Each CSP-H processing element (PE) employs a novel accumulation buffer design and a counter-based sparse-skipping mechanism to support the dataflow with minimum controller overhead. We verify our approach on several representative models. Our simulated results show that CSP achieves on average 15x energy efficiency improvement over SparTen with comparable or superior speedup under most evaluations.

关键词： MLAcceleration Model Compression Hardware/software co-design Low Power Microarchitecture

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A high-performance Data Verification Mechanism in Blockchain-Based IoT Systems 21

A High-Performance Data Verification Mechanism in Blockchain...

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作者： Zhang, Jingyu Zhou, Pian Sun, Yongtao Luo, Lailong Changsha University of Science and Technology School of Computer and Communication Engineering Changsha China National University of Defense Technology Science and Technology on Information Systems Engineering Laboratory School of Systems Engineering Changsha China

ISBN: (纸本)9798350329223

With the rapid development of the distributed network and communication, the Internet of things (IoT) systems have been applied to all walks of life. Blockchain technology is one of the most popular research fields recently, which can provide a reliable storage solution and solve information security issues for IoT systems. Transaction information is the most critical fundamental data in the blockchain systems, which needs to be verified to avoid being tempered with by malicious nodes in the process of transmission. With the exponential growth of the number of IoT devices, the limitations of the current storage structure put too much pressure on the system nodes. How to improve verification efficiency has become a key challenge. To alleviate this problem, this paper proposes a novel high-performance verification mechanism for data security protection in blockchain-based IoT systems. We design a new storage structure based on Huffman trunk tree (HTT), and conduct the quantitative analysis of transaction weights. Transactions are stored in full-featured devices in the form of Huffman Merkle tree (HMT), and only the content of HTT is saved in lightweight devices. Finally, the performance superiority of our mechanism is proved through theoretical analysis and experimental evaluation. In blockchain-based IoT systems, our mechanism significantly reduces the data transmission cost and computation overhead, effectively improving the efficiency of data verification. © 2023 IEEE.

关键词： Efficiency

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MRHS multigrid solver for Wilson-clover fermions 39

MRHS multigrid solver for Wilson-clover fermions

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39th International symposium on Lattice Field theory, LATTICE 2022

作者： Richtmann, Daniel Meyer, Nils Wettig, Tilo Department of Physics University of Regensburg Regensburg93040 Germany

We describe our implementation of a multigrid solver for Wilson-clover fermions, which increases parallelism by solving for multiple right-hand sides (MRHS) simultaneously. the solver is based on Grid and thus runs on all computing architectures supported by the Grid framework. We present detailed benchmarks of the relevant kernels, such as hopping and clover term on the various multigrid levels, intergrid operators, and reductions. the benchmarks were performed on the JUWELS Booster system at Jülich Supercomputing Centre, which is based on Nvidia A100 GPUs. For example, solving a 243 × 128 lattice on 16 GPUs, the overall speedup obtained solely from MRHS is about 10x. © Copyright owned by the author(s) under the terms of the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License (CC BY-NC-ND 4.0).

关键词： computer architecture

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An Experimental Comparison of RISC-V Processors: performance, Power, Area and Security - Special Session Paper 37

An Experimental Comparison of RISC-V Processors: Performance...

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37th IEEE International symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2024

作者： Lazzeri, Elia Forlin, Bruno Endres Furano, Gianluca Ottavi, Marco Cassano, Luca Politecnico di Milano Dipartimento di Elettronica Informazione e Bioingegneria Italy University of Twente Faculty of Electrical Engineering Mathematics and Computer Science Netherlands Europeran Space Agency European Space Research and Technology Centre Netherlands

ISBN: (纸本)9798350366884

the RISC-V instruction set architecture (ISA) has garnered significant interest from both industry and academia because of its open source nature. Recent years have witnessed a surge in published implementations of the RISC-V ISA, with various companies actively pursuing its adoption in their products. However, a comprehensive analysis comparing these emerging RISC-V processors with each other and against established embedded computing platforms has not yet been published. this paper presents an experimental evaluation of three high-performance RISC-V processors: BOOM, NOEL-V, and CVA6 (formerly Ariane). the investigation is conducted on a Xilinx Kintex-7 Field-Programmable Gate Array (FPGA) platform. We perform a detailed analysis of critical performance metrics, covering area footprint, power consumption, and performance efficiency. Additionally, we assess the security posture of these cores against transient execution attacks, a prominent contemporary security threat. Finally, a comparative evaluation is undertaken between the RISC-V processors and two conventional application-level ARM processors to elucidate technological discrepancies and application suitability. this analysis aims to provide valuable insights into the current state and potential of RISC-V processors within the embedded computing domain. © 2024 IEEE.

关键词： ARM processors

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