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检索条件"任意字段=Proceedings - 16th Symposium on Computer Architecture and High Performance Computing"

共 2316 条记录，以下是111-120 订阅

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high-performance Low-Vcc In-Order Core

High-Performance Low-Vcc In-Order Core

引用

16th International symposium on high-performance computer architecture

作者： Abella, Jaume Chaparro, Pedro Vera, Xavier Carretero, Javier Gonzalez, Antonio Intel Labs Barcelona UPC Intel Barcelona Res Ctr Barcelona Spain

ISBN: (纸本)9781424456598

Power density grows in new technology nodes, thus requiring Vcc to scale especially in mobile platforms where energy is critical. this paper presents a novel approach to decrease V cc while keeping operating frequency high. Our mechanism is referred to as immediate read after write (IRAW) avoidance. We propose an implementation of the mechanism for an Intel (R) Silterthorne (TM) in-order core. Furthermore, we show that our mechanism can be adapted dynamically to provide the highest performance and lowest energy-delay product (EDP) at each Vcc level. Results show that IRAW avoidance increases operating frequency by 57% at 500mV and 99% at 400mV with negligible area and power overhead (below 1%), which translates into large speedups (48% at 500mV and 90% at 400mV) and EDP reductions (0.61 EDP at 500mV and 0.33 at 400mV).

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Ridge: Combining reliability and performance in open grid platforms 07

Ridge: Combining reliability and performance in open grid pl...

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16th International symposium on high performance Distributed computing 2007, HPDC'07 and Co-Located Workshops

作者： Budati, Krishnaveni Sonnek, Jason Chandra, Abhishek Weissman, Jon Department of Computer Science and Engineering University of Minnesota - Twin Cities Minneapolis MN United States

ISBN: (纸本)1595936734

Large-scale donation-based distributed infrastructures need to cope with the inherent unreliability of participant nodes. A widely-used work scheduling technique in such environments is to redundantly schedule the out sourced computations to a number of nodes. We present the design and implementation of RIDGE, a reliability aware system which uses a node's prior performance and behavior to make more effective scheduling decisions. We have implemented RIDGE on top of the BOINC distributed computing infrastructure and have evaluated its performance on a live test bed consisting of 120 PlanetLab nodes. Our experimental results show that RIDGE is able to match or surpass the throughput of the best vanilla BOINC configuration under different reliability environments, by automatically adapting to the characteristics of the underlying environment. In addition, RIDGE is able to provide much lower work unit makes pans compared to BOINC, which indicates its desirability in service-oriented environments with time constraints. Copyright 2007 ACM.

关键词： Grid computing

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Efficient all-to-all broadcast schemes in distributed-memory parallel computers 16

Efficient all-to-all broadcast schemes in distributed-memory...

引用

16th Annual International symposium on high performance computing Systems and Applications

作者： Oh, ES Kanj, IA Texas A&M Univ Dept Comp Sci College Stn TX 77843 USA

ISBN: (纸本)0769516262

Distributed-memory parallel computers refer to parallel computers in which each processor has its own private memory In such a system, processors communicate information by exchanging messages via the interconnection network rather than storing it in shared memory. One of the important communication methods in such systems is data broadcasting. All-to-all broadcasting is the process in which each processor sends its message to all other processors, and receives messages from all other processors in the system. Two complexity elements are usually considered when measuring the performance of a distributed-memory parallel model: time complexity and message complexity In this paper, we develop an efficient communication scheme to reduce both the communication time and the message complexity in the star network model under the half-duplex and full-duplex communication capability the complexity measures of our scheme are compared against known bounds to verify the efficiency of the suggested scheme.

关键词： all-to-all broadcast distributed parallel computing systems inter-processor communication star network

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Cooperative secondary authorization recycling 07

Cooperative secondary authorization recycling

引用

16th International symposium on high performance Distributed computing 2007, HPDC'07 and Co-Located Workshops

作者： Wei, Qiang Ripeanu, Matei Beznosov, Konstantin Dept. of Electrical and Computer Engineering University of British Columbia Vancouver BC Canada

ISBN: (纸本)1595936734

As distributed applications such as Grid and enterprise systems scale up and become increasingly complex, their authorization infrastructures-based predominantly on the request-response paradigm-are facing challenges in terms of fragility and poor scalability. We propose an approach where each application server caches previously received authorizations at its secondary decision point and shares them with other application servers to mask authorization server failures and network *** paper presents the design of our cooperative secondary authorization recycling system and its evaluation using simulation and prototype implementation. the results demonstrate that our approach improves the availability of authorization infrastructures while preserving their performance characteristics. Specifically, by sharing authorizations, the cache hit *** indirect metric of *** reach 70%, even when only 10% of authorizations are cached. Depending on the deployment scenario, the performance in terms of the average time for authorizing an application request can be reduced by up to 30%. Copyright 2007 ACM.

关键词： computer supported cooperative work

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A Framework for Routing and Resource Allocation in Network Virtualization

A Framework for Routing and Resource Allocation in Network V...

引用

16th International Conference on high performance computing (HiPC 2009)

作者： Solheim, Ashild Gronstad Lysne, Olav Skeie, Tor Sodring, thomas Reinemo, Sven-Arne Simula Res Lab Networks & Distributed Syst Grp Lysaker Norway

ISBN: (纸本)9781424449217

computer architectures for high performance computing have traditionally been based on an assumption of one parallel application running alone on one machine. the current trend is, however, that huge computer installations offer compute power to a set of users or customers, each demanding only a subset of the available compute resources. this places new requirements on the architecture, in that it must support dynamic partitioning of the resources into several virtual servers as demand changes. We introduce a novel framework which supports flexible formation of such virtual servers while preventing interference between the communication of different virtual servers. this paper investigates the impacts of a shared interconnection network on applications running on virtual compute servers. We show that the interconnect performance supplied to each job is highly unpredictable, and that a job can experience a performance degradation of 97% when its traffic interferes with the traffic of concurrent jobs. With a minor reduction in the utilization of each processing node, this can be considerably improved through a combination of routing-containment in the interconnection network and a carefully designed resource allocation strategy.

关键词： computer architecture

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Load balancing on stateful clustered web servers 15

Load balancing on stateful clustered web servers

引用

15th symposium on computer architecture and high performance computing

作者： Teodoro, G Tavares, T Coutinho, B Meira, W Guedes, D Univ Fed Minas Gerais Dept Comp Sci BR-31270010 Belo Horizonte MG Brazil

ISBN: (纸本)0769520464

One of the main challenges to the wide use of the Internet is the scalability of the servers, that is, their ability to handle the increasing demand. Scalability in stateful servers, which comprise e-Commerce and other transaction-oriented servers, is even more difficult, since it is necessary to keep transaction data across requests from the same user One common strategy for achieving scalability is to employ clustered servers, where the load is distributed among the various servers. However, as a consequence of the workload characteristics and the need of maintaining data coherent among the servers that compose the cluster, load imbalance arise among servers, reducing the efficiency of the server as a whole. In this paper we propose and evaluate a strategy for load balancing in stateful clustered servers. Our strategy is based on control theory and allowed significant gains over configurations that do not employ the load balancing strategy, reducing the response time in up to 50% and increasing the throughput in up to 16%.

关键词： computer architecture computer science Control theory Delay Internet Load management Scalability throughput Web server World Wide Web

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three hardware implementations for the binary modular exponentiation: Sequential, parallel and systolic 15

Three hardware implementations for the binary modular expone...

引用

15th symposium on computer architecture and high performance computing

作者： Nedjah, N Mourelle, LD Univ Estado Rio De Janeiro Fac Engn Dept Syst Engn & Computat Rio De Janeiro Brazil

ISBN: (纸本)0769520464

Modular exponentiation is the cornerstone computation performed in public-key cryptography systems such as the RSA cryptosystem. the operation is time consuming for large operands. this paper describes the characteristics of three architectures designed to implement modular exponentiation using the fast binary method: the first FPGA prototype has a sequential architecture, the second has a parallel architecture and the third has a systolic array-based architecture. the paper compares the three prototypes using the time x area classic factor. All three prototypes implement the modular multiplication using the popular Montgomery algorithm.

关键词： computer architecture Concurrent computing Delay Hardware Iterative algorithms Parallel architectures Prototypes Public key Public key cryptography Systems engineering and theory

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Exploring memory hierarchy with ArchC 15

Exploring memory hierarchy with ArchC

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15th symposium on computer architecture and high performance computing

作者： Viana, P Barros, E Rigo, S Azevedo, R Araújo, G Univ Fed Pernambuco Informat Ctr Recife PE Brazil

ISBN: (纸本)0769520464

this paper presents the cache configuration exploration of a programmable system, in order to find the best matching between the architecture and a given application. Here, programmable systems composed by processor and memories may be rapidly simulated making use of ArchC, an architecture Description Language (ADL) based on SystemC Initially designed to model processor architectures, ArchC was extended to support a more detailed description of the memory subsystem, allowing the design space exploration of the whole programmable system. As an example, it is shown an image processing application, running on a SPARC-V8 processor-based architecture, which had its memory organization adjusted to minimize cache misses.

关键词： Application software architecture description languages Computational modeling computer architecture Design methodology Digital systems Image processing Informatics Process design Software performance

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An enhanced scheduling approach in a distributed parallel environment using mobile agents 16

An enhanced scheduling approach in a distributed parallel en...

引用

16th Annual International symposium on high performance computing Systems and Applications

作者： Dantas, MAR Lopes, JGRC Ramos, TG Univ Brasilia Dept Comp Sci BR-70919970 Brasilia DF Brazil

ISBN: (纸本)0769516262

In this article our goal is to apply the mobile agent technology to provide a better scheduling to MPI applications executing in a cluster configuration. this approach could represent in a distributed cluster environment an enhancement on the load balancing of the parallel processes. MPI in cluster of heterogeneous machines could lead parallel programmers to obtain frustrated results, mainly because of the lack of an even distribution of the workload in the cluster. As a result, before submitting a MPI application to a cluster, we use our JOTA mobile agent approach to acquire a more precise information of machine's workload, therefore, with a more precise knowledge of the load and characteristics in each machine, we are ready to gather lightweight workstations to form a cluster. Our empirical results indicates that it is possible to spend less elapsed time when considering the execution of a parallel application using the agent approach in comparison to an ordinary MPI environment.

关键词： scheduling load balancing mobile agents message passing interface (MPI) and cluster computing

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Simple Virtual Channel Allocation for high throughput and high Frequency On-Chip Routers

Simple Virtual Channel Allocation for High Throughput and Hi...

引用

16th International symposium on high-performance computer architecture

作者： Xu, Yi Zhao, Bo Zhang, Youtao Yang, Jun Univ Pittsburgh Dept Elect & Comp Engn Pittsburgh PA 15621 USA Univ Pittsburgh Dept Comp Sci Pittsburgh PA 15621 USA

ISBN: (纸本)9781424456598

Technology scaling has led to the integration of many cores into a single chip. As a result, on-chip interconnection networks start to play a more and more important role in determining the performance and power of the entire chip. Packet-switched network-on-chip (NoC) has provided a scalable solution to the communications for tiled multicore processors. However the virtual-channel (VC) buffers in the NoC consume significant dynamic and leakage power of the system. To improve the energy efficiency of the router design, it is advantageous to use small buffer sizes while still maintaining throughput of the network. this paper proposes two new virtual channel allocation (VA) mechanisms, termed Fixed VC Assignment with Dynamic VC Allocation (FVADA) and Adjustable VC Assignment with Dynamic VC Allocation (AVADA). the idea is that VCs are assigned based on the designated output port of a packet to reduce the Head-of-Line (HoL) blocking. Also, the number of VCs allocated for each output port can be adjusted dynamically. Unlike previous buffer-pool based designs, we only use a small number of VCs to keep the arbitration latency low. Simulation results show that FVADA and AVADA can improve the network throughput by 41% on average, compared to a baseline design with the same buffer size. AVADA can still outperform the baseline even when our buffer size is halved. Moreover, we are able to achieve comparable or better throughput than a previous dynamic VC allocator while reducing its critical path delay by 60%. Our results prove that the proposed VA mechanisms are suitable for low-power, high-throughput, and high-frequency on-chip network designs.

关键词： Network-on-chip

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