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检索条件"任意字段=Proceedings - 16th Symposium on Computer Architecture and High Performance Computing"

共 2316 条记录，以下是151-160 订阅

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MOB: Zero-configuration high-throughput multicasting for grid applications 07

MOB: Zero-configuration high-throughput multicasting for gri...

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16th International symposium on high performance Distributed computing 2007, HPDC'07 and Co-Located Workshops

作者： Den Burger, Mathijs Kielmann, thilo Dept. of Computer Science Vrije Universiteit Amsterdam

ISBN: (纸本)1595936734

Grid applications often need to distribute large amounts of data efficiently from one cluster to multiple others (multicast). Existing methods usually arrange nodes in optimized tree structures, based on external network monitoring data. this dependence on monitoring data, however, severely impacts both ease of deployment and adaptivity to dynamically changing network conditions. In this paper, we present Multicast Optimizing Bandwidth (MOB), a high-throughput multicast approach, inspired by the BitTorrent protocol. With MOB, data transfers are initiated by the receivers that try to steal data from peer clusters. Instead of using potentially outdated monitoring data, MOB automatically adapts to the currently achievable bandwidth ratios. Our experimental evaluation compares MOB to both the BitTorrent protocol and to our previous approach, Balanced Multicasting, the latter optimizing multicast trees based on external monitoring data. We show that MOB outperforms the BitTorrent protocol. MOB is competitive with Balanced Multicasting as long as the network bandwidth remains stable. With dynamically changing bandwith, MOB outperforms Balanced Multicasting by wide margins. Copyright 2007 ACM.

关键词： Multicasting

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proceedings of the 16th IEEE symposium on Field-Programmable Custom computing Machines, FCCM'08

Proceedings of the 16th IEEE Symposium on Field-Programmable...

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16th IEEE symposium on Field-Programmable Custom computing Machines, FCCM'08

ISBN: (纸本)9780769533070

the proceedings contain 46 papers. the topics discussed include: performance analysis with high-level languages for high-performance reconfigurable computing;a SRAM-based architecture for Trie-based IP lockup using FPGA;a scalable high throughput firewall in FPGA;the effectiveness of configuration merging in point-to-point networks for module-based FPGA reconfiguration;autonomous system on a chip adaptation through partial runtime reconfiguration;FPGA-based co-processor for singular value array reconciliation tomography;real-time optical flow calculations on FPGA and GPU architectures: a comparison study;multiobjective optimization of FPGA-based medical image registration;sparse matrix-vector multiplication on a reconfigurable supercomputer;fast multivariate signature generation in hardware: the case of rainbow;and runtime filesystem support for reconfigurable FPGA hardware process in BORPH.

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Self-Monitored Adaptive cache warm-up for microprocessor simulation

Self-Monitored Adaptive cache warm-up for microprocessor sim...

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proceedings - 16th symposium on computer architecture and high performance computing

作者： Luo, Yue John, Lizy K. Eeckhout, Lieven University of Texas Austin United States Ghent University Belgium

Simulation is the most important tool for computer architects to evaluate the performance of new computer designs. However, detailed simulation is extremely time consuming. Sampling is one of the techniques that effectively reduce simulation time. In order to achieve accurate sampling results, microarchitectural structure must be adequately warmed up before each measurement. In this paper, a new technique for warming up microprocessor caches is proposed. the simulator monitors the warm-up process of the caches and decides when the caches are warmed up based on simple heuristics. In our experiments the Self-Monitored Adaptive (SMA) warm-up technique on average exhibits only 0.2% warm-up error in CPI. SMA achieves smaller warm-up error with only 1/2∼1/3 of the warm-up length of previous methods. In addition, it is adaptive to the cache configuration simulated. For simulating small caches, the SMA technique can reduce the warm-up overhead by an order of magnitude compared to previous techniques. Finally, SMA gives the user some indicator of warm-up error at the end of the cycle-accurate simulation that helps the user to gauge the accuracy of the warm-up. © 2004 IEEE.

关键词： computer architecture

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A new migration model based on the evaluation of processes load and lifetime on heterogeneous computing environments

A new migration model based on the evaluation of processes l...

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proceedings - 16th symposium on computer architecture and high performance computing

作者： De Mello, Rodrigo Fernandes Senger, Luciano José Universidade de São Paulo Inst. de Cie. Matemat. e de Comp. Caixa Postal 668 13560-970 São Carlos - SP Brazil Univ. Estadual de Ponta Grossa Departamento de Informática Av. Carlos Cavalcanti 4748 84030-900 Ponta Grossa - PR Brazil

ISBN: (纸本)0769522408

this paper presents a new model for evaluation of the positive and negative impacts related to the process migration on environments composed by heterogeneous capacity computers. On this model, a busy computer analyzes the occupation of each process and selects the more adequate for migration. the analysis and selection are done through a migration factor. this factor reflects how much the busy computer will be freed and how much the destination computer will be overloaded, in view of the migration of each process. the migrated processes are the ones that present migration factors to enhance the environment load balancing. the results from the carried out experiments have proved this model contributions when compared to related work. the contribution is the decrease in process average response time, which means higher performance. © 2004 IEEE.

关键词： Microprocessor chips

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Precise and realistic utility functions for user-centric performance analysis of schedulers 07

Precise and realistic utility functions for user-centric per...

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16th International symposium on high performance Distributed computing 2007, HPDC'07 and Co-Located Workshops

作者： Lee, Cynthia B. Snavely, Allan E. Dept. of Computer Science and Engineering San Diego Supercomputer Center University of California San Diego San Diego CA 92093-0505

ISBN: (纸本)1595936734

Utility functions can be used to represent the value users attach to job completion as a function of turnaround time. Most previous scheduling research used simple synthetic representations of utility, with the simplicity being due to the fact that real user preferences are difficult to obtain, and perhaps concern that arbitrarily complex utility functions could in turn make the scheduling problem intractable. In this work, we advocate a flexible representation of utility functions that can indeed be arbitrarily complex. We show that a genetic algorithm heuristic can improve global utility by analyzing these functions, and does so tractably. Since our previous work showed that users indeed have and can articulate complicated utility functions, the result here is relevant. We then provide a means to augment existing workload traces with realistic utility functions for the purpose of enabling realistic scheduling simulations. Copyright 2007 ACM.

关键词： Scheduling

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Instruction usage and the memory gap problem 14

Instruction usage and the memory gap problem

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14th symposium on computer architecture and high performance computing

作者： Fernandes, EST Barbosa, VC Ramos, F Univ Fed Rio de Janeiro COPPE Programa Engn Sistemas & Comp BR-21941 Rio De Janeiro Brazil

ISBN: (纸本)0769517722

the gap between memory and processor speeds is responsible for the substantial amount of idle time of current processors. To reduce the impact provoked by the so-called " memory gap problem," many software techniques (e.g., the code layout reorganization) together with hardware mechanisms (cache memory, translation look-aside buffer, branch prediction, speculative execution, trace cache, instruction reuse, and so on) have been successfully implemented. In this paper we present some experiments that explain why these mechanisms and techniques are so efficient. We found that only a small fraction of the object code is actually executed: our experiments disclosed that more than 50% of the instructions remain untouched during the whole execution, and the percentages of basic blocks which remain unused are slightly greater In addition to the usage of instructions and blocks, the paper provides further insights regarding the behavior of application programs, and gives some suggestions for extra performance gains.

关键词： Cache memory computer aided instruction computer architecture Delay Hardware performance gain performance loss Prefetching Random access memory Software performance

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Design and implementation of secured information services for the ASCI Grid 11

Design and implementation of secured information services fo...

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11th IEEE International symposium on high performance Distributed computing (HPDC-11)

作者： Johnson, WR Sandia Natl Labs Albuquerque NM 87185 USA

ISBN: (纸本)0769516866

Information services are an integral part of the grid architecture. It is the foundation of how resources are defined and their state known. More importantly, the user of the Grid gets a perspective of what a grid looks like, how it performs and what capabilities it has from information services. the Accelerated Strategic computing Initiative(1) (ASCI) has designed and deployed a set of grid services within the context of the ASCI program. We deploy information services by augmenting the Globus toolkit in order to meet the unique aspects of the ASCI grid. In this paper we describe the decisions made and processes developed to run a grid information service in the ASCI grid.

关键词： Acceleration Access control computer architecture computer networks Context-aware services Distributed computing Filters Grid computing Laboratories Resource management

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Minimally-skewed-associative caches 14

Minimally-skewed-associative caches

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14th symposium on computer architecture and high performance computing

作者： Djordjalian, A

ISBN: (纸本)0769517722

Skewed-associativity is a technique that reduces the miss ratios of CPU caches by applying different indexing functions to each way of an associative cache. Even though it showed impressive hit/miss statistics, the scheme has not been welcomed by the industry, presumably because implementation of the original version is complex and might involve access-time penalties among other costs. this work presents a simplified, easy to implement variant that we call 11 niininialli,-skewed-associativity (MSkA). We show that MRA caches, for many cases, should not have penalties in either access time or power consumption when compared to set-associative caches of the same associativity. Hit/miss statistics were obtained by means of trace-driven simulations. Miss ratios are not as good as those for full skewing, but they are still advantageous. Minimal-skewing is thus proposed as a way to improve the hit/miss performance of caches, often without producing access-time delays or increases in power consumption as other techniques do (for example, using higher associativities).

关键词： Bandwidth Cache memory computer architecture Costs Delay Energy consumption Energy efficiency Indexing Statistics Visualization

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CLITE: Efficient and QoS-Aware Co-location of Multiple Latency-Critical Jobs for Warehouse Scale computers 26

CLITE: Efficient and QoS-Aware Co-location of Multiple Laten...

引用

26th IEEE International symposium on high performance computer architecture (HPCA)

作者： Patel, Tirthak Tiwari, Devesh Northeastern Univ Boston MA 02115 USA

ISBN: (纸本)9781728161495

Large-scale data centers run latency-critical jobs with quality-of-service (QoS) requirements, and throughput-oriented background :jobs, which need to achieve high performance. Previous works have proposed methods which cannot co-locate multiple latency-critical jobs with multiple backgrounds jobs while: (I) meeting the QoS requirements of all latency-critical jobs, and (2) maximizing the performance of the background jobs. this paper proposes CLITE, a Bayesian Optimization-based, multi-resource partitioning technique which achieves these goals.

关键词： Latency Critical Jobs Multi Tenancy QoS Delivery Warehouse Scale computing

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high performance floating-point unit with 116 bit wide divider

High performance floating-point unit with 116 bit wide divid...

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16th IEEE symposium on computer Arithmetic

作者： Gerwig, G Wetter, H Schwarz, EM Haess, J IBM Corp Server Div Armonk NY 10504 USA

ISBN: (纸本)076951894X

the next generation zSeries floating-point unit is unveiled which is the first IBM mainframe with a fused multiply-add dataflow. It supports both S/390 hexadecimal floating-point architecture and the IEEE 754 binary floating-point architecture which was first implemented in S/390 on the 1998 S/390 G5 floating-point unit. the new floating-point unit supports a total of 6 formats including single, double, and quadword formats implemented in hardware. the floating-point pipeline is 5 cycles with a throughput of 1 multiply-add per cycle. Both hexadecimal and binary floating-point instructions are capable of this performance due to a novel way of handling both formats. Other key developments include new methods for handling denormalized numbers and quad precision divide engine dataflow. this divider uses a radix-4 SRT algorithm and is able to handle quad precision divides in multiple floating-point and fixed-point formats. the number of iterations for fixed-point divisions depend on the effective number of quotient bits. It uses a reduced carry-save form for the partial remainder, with only 1 carry bit for every 4 sum bits, to save area and power.

关键词： Digital arithmetic

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