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Applying scheduling by edge reversal to constraint partitioning 15

Applying scheduling by edge reversal to constraint partition...

引用

15th symposium on computer architecture and high performance computing

作者： Pereira, MR Vargas, PK França, FMG de Castro, MCS Dutra, ID Univ Fed Rio de Janeiro COPPE BR-21945 Rio De Janeiro Brazil

ISBN: (纸本)0769520464

Scheduling by Edge Reversal (SER) is a fully distributed scheduling mechanism based on the manipulation of acyclic orientations of a graph. this work uses SER to perform constraint partitioning of Constraint Satisfaction Problems (CSP). In order to apply the SER mechanism, the graph representing the constraints must receive an acyclic orientation. Since obtaining an optimal acyclic orientation is an NP-hard problem, this work studies three non-deterministic strategies known in the literature: Alg-Neigh, Alg-Edges, and Alg-Colour. We implemented the three algorithms and the SER scheduling mechanism, applying them to the CSP constraint networks generated from 3 applications. Our results show that SER has a great potential to perform a good partitioning of the constraint graphs.

关键词： Concurrent computing Distributed algorithms Distributed computing NP-hard problem Partitioning algorithms Processor scheduling Programming environments Scheduling algorithm System recovery Time factors

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high-performance Diagnostic Fault Simulation on GPUs

High-Performance Diagnostic Fault Simulation on GPUs

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16th IEEE European Test symposium (ETS)

作者： Li, Min Hsiao, Michael S. Virginia Tech Bradley Dept Elect & Comp Engn Blacksburg VA 24061 USA

ISBN: (纸本)9780769544335

In this paper, we present an efficient diagnostic fault simulator based on a state-of-the-art graphics processing unit (GPU). Diagnostic fault simulation plays an important role to identify and locate the causes of circuit failures. However, today's complex VLSI circuits pose ever higher computational demand for such simulators. Our GPU based diagnostic fault simulator (GDSim) is based on a novel two-stage simulation framework which exploits high computation efficiency on the GPU. the fault pair based simulation is proposed to overcome the limited capacity of GPU memory as well as achieve a substantial fine-grained parallelism. Multi-fault-signature and dynamic load balancing techniques are introduced for the best usage of computing resources on-board. Experimental results demonstrate a speedup of up to 121x (with average speedup of 38.43x) compared to a state-of-the-art CPU-based diagnostic fault simulator.

关键词： compute unified device architecture (CUDA) diagnostic faut simulation general-purpose computing on graphics processing unit (GPGPU) parallel algorithm

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Flexible high-performance access to distributed storage resources 9

Flexible high-performance access to distributed storage reso...

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9th IEEE International symposium on high performance Distributed computing

作者： Patten, CJ Hawick, KA Univ Adelaide Dept Comp Sci Distributed & High Performance Comp Grp Adelaide SA 5005 Australia

ISBN: (纸本)0769507840

We describe a software architecture for storage services in computational grid environments. Based upon a lightweight message-passing paradigm, the architecture enables the provision and composition of active, distributed storage services. these services can then cooperatively provide access to distributed storage in a manner potentially optimized for dataset and resource environments. We report on the design and implementation of a distributed file system and a dataset-specific satellite imagery service using the architecture. We discuss data movement and storage issues and implications for future work with the architecture.

关键词： computer architecture Distributed computing File servers File systems Grid computing Memory Network servers Peer to peer computing Prefetching Satellites

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performance issues of bandwidth reservations for grid computing 15

Performance issues of bandwidth reservations for grid comput...

引用

15th symposium on computer architecture and high performance computing

作者： Burchard, LO Heiss, HU De Rose, CAF Tech Univ Berlin Commun & Operating Syst Grp D-1000 Berlin Germany

ISBN: (纸本)0769520464

In general, two types of resource reservations in computer networks can be distinguished: immediate reservations which are made in a just-in-time manner and advance reservations which allow to reserve resources a long time before they are actually used. Advance reservations are especially useful for grid computing but also for a variety of other applications that require network quality-of-service, such as content distribution networks or even mobile clients, which need advance reservation to support handovers for streaming video. With the emerged MPLS standard, explicit routing can be implemented also in IP networks, thus overcoming the unpredictable routing behavior which so far prevented the implementation of advance reservation services. the impact of such advance reservation mechanisms on the performance of the network with respect to the amount of admitted requests and the allocated bandwidth has so far not been examined in detail. In this paper we show that advance reservations can lead to a reduced performance of the network with respect to both metrics. the analysis of the reasons shows a fragmentation of the network resources. In advance reservation environments, additional new services can be defined such as malleable reservations which are introduced in this paper and can lead to an increased performance of the network. Four strategies for scheduling malleable reservations are presented and compared. the results of the comparisons show that some strategies increase the resource fragmentation and are therefore unsuitable in the considered environment while others lead to a significantly better performance of the network. Besides discussing the performance issue, in this paper the software architecture of a management system for advance reservations is presented.

关键词： Application software Bandwidth computer networks Grid computing IP networks Mobile computing Multiprotocol label switching Quality of service Software architecture Streaming media

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BRIM: Bistable Resistively-Coupled Ising Machine 27

BRIM: Bistable Resistively-Coupled Ising Machine

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27th IEEE International symposium on high-performance computer architecture (HPCA)

作者： Afoakwa, Richard Zhang, Yiqiao Vengalam, Uday Kumar Reddy Ignjatovic, Zeljko Huang, Michael Univ Rochester Dept Elect & Comp Engn Rochester NY 14627 USA

ISBN: (纸本)9781665422352

Physical Ising machines rely on nature to guide a dynamical system towards an optimal state which can be read out as a heuristical solution to a combinatorial optimization problem. Such designs that use nature as a computing mechanism can lead to higher performance and/or lower operation costs. Quantum annealers are a prominent example of such efforts. However, existing Ising machines are generally bulky and energy intensive. Such disadvantages may be acceptable if these designs provide some significant intrinsic advantages at a much larger scale in the future, which remains to be seen. But for now, integrated electronic designs of Ising machines allow more immediate applications. We propose one such design that uses bistable nodes, coupled with programmable and variable strengths. the design is fully CMOS compatible for on-chip applications and demonstrates competitive solution quality and significantly superior execution time and energy.

关键词： Ising machine optimization CMOS accelerators nature-based computing quantum annealing

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CADS 2012 - 16th CSI International symposium on computer architecture and Digital Systems

CADS 2012 - 16th CSI International Symposium on Computer Arc...

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16th CSI International symposium on computer architecture and Digital Systems, CADS 2012

ISBN: (纸本)9781467314824

the proceedings contain 32 papers. the topics discussed include: an applicable high-efficient CNTFET-based full adder cell for practical environments;ParSA: parallel simulated annealing placement algorithm for multi-core systems;improved performance and power consumption of three-dimensional FPGAs using carbon nanotube interconnects;modeling, evaluation and mitigation of SEU error in three-dimensional FPGAs;value-aware low-power register file architecture;a 0.7-to-1.1-GHz all-digital phase-locked loop with a new phase frequency detector AND controlled oscillator with body-biasing;extracting one-way quantum computation patterns from quantum circuits;soft-error-immune communication network using unbalanced protection selection;a high performance, race eliminated, two phase nonoverlapping clocked all-n-logic for both strong and subthreshold designs;and fault-tolerant assessment and enhancement in the reconfigurable network-on-chip.

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Local discovery of system architecture - Application parameter sensitivity: An empirical technique for adaptive grid applications 11

Local discovery of system architecture - Application paramet...

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11th IEEE International symposium on high performance Distributed computing (HPDC-11)

作者： Corey, IR Johnson, JR Vetter, JS Lawrence Livermore Natl Lab Comp Applicat & Res Dept Livermore CA USA

ISBN: (纸本)0769516866

this study presents a technique that can significantly improve the performance of a distributed application by allowing the application to locally adapt to architectural characteristics of distinct resources in a distributed system. Application performance is sensitive to system architecture-application parameter pairings. In a distributed or Grid enabled application, a single parameter configuration for the whole application will not always be optimal for every participating resource. In particular, some configurations can significantly degrade performance. Furthermore, the behavior of a system may change during the course of the run. the technique described here provides an automated mechanism for run-time adaptation of application parameters to the local system architecture. Using a scaled-down simulation of a Monte Carlo physics code, we demonstrate that this technique can conservatively achieve speedups up to 65% on individual resources and may even provide order of magnitude speedup in the extreme case.

关键词： Application software computer applications computer architecture Degradation Distributed computing Laboratories Monte Carlo methods performance evaluation Processor scheduling Runtime

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Power Struggles: Revisiting the RISC vs. CISC Debate on Contemporary ARM and x86 architectures

Power Struggles: Revisiting the RISC vs. CISC Debate on Cont...

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19th IEEE International symposium on high performance computer architecture (HPCA)

作者： Blem, Emily Menon, Jaikrishnan Sankaralingam, Karthikeyan Univ Wisconsin Madison WI 53706 USA

ISBN: (纸本)9781467355872

RISC vs. CISC wars raged in the 1980s when chip area and processor design complexity were the primary constraints and desktops and servers exclusively dominated the computing landscape. Today, energy and power are the primary design constraints and the computing lands cape is significantly different: growth in tablets and smartphones running ARM (a RISC ISA) is surpassing that of desktops and laptops running x86 (a CISC ISA). Further, the traditionally low-power ARM ISA is entering the high-performance server market, while the traditionally high-performance x86 ISA is entering the mobile low-power device market. thus, the question of whether ISA plays an intrinsic role in performance or energy efficiency is becoming important, and we seek to answer this question through a detailed measurement based study on real hardware running real applications. We analyze measurements on the ARM Cortex-A8 and Cortex-A9 and Intel Atom and Sandybridge i7 microprocessors over workloads spanning mobile, desktop, and server computing. Our methodical investigation demonstrates the role of ISA in modern microprocessors' performance and energy efficiency. We find that ARM and x86 processors are simply engineering design points optimized for different levels of performance, and there is nothing fundamentally more energy efficient in one ISA class or the other. the ISA being RISC or CISC seems irrelevant.

关键词： computational complexity integrated circuit design microprocessor chips parallel architectures reduced instruction set computing

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proceedings of the 5th IEEE Workshop on Challenges of Large Applications in Distributed Environments, CLADE'07

Proceedings of the 5th IEEE Workshop on Challenges of Large ...

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16th International symposium on high performance Distributed computing 2007, HPDC'07 and Co-Located Workshops

ISBN: (纸本)1595937145

the proceedings contain 5 papers. the topics discussed include: enabling rapid development of parallel tree search applications;challenges in executing large parameter sweep studies across widely distributed computing environments;hyperscaling of plasma turbulence simulations in DEISA;WISDOM-II: a large in silico docking effort for finding novel hits against malaria using computational grid infrastructure;and efficient processing of pathological images using the grid: computer-aided prognosis of neuroblastoma.

关键词： Distributed computer systems

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Mobile computers as scientific computing machines 16

Mobile computers as scientific computing machines

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16th IEEE International Conference on high performance computing and Communications, HPCC 2014, 11th IEEE International Conference on Embedded Software and Systems, ICESS 2014 and 6th International symposium on Cyberspace Safety and Security, CSS 2014

作者： Smit, W.A. Herbst, B.M. Stellenbosch University Stellenbosch South Africa

ISBN: (纸本)9781479961238

As pervasive mobile computing becomes more of areality the question arises whether a mobile device such as atablet can be sufficient to serve as the sole personal computingdevice of a scientist. To this end the performance of an Androidbased tablet computer is compared to that of a Notebook. Due toits prevalence within the scientific community and its availabilityon both platforms, Python is used as the basis of the *** conclusion is that the basic tablet hardware platformcompares well to that of the Notebook. the software alsocompares well in terms of usability and features but lacksperformance where floating-point computations are *** notebook-to-tablet ratio of performance varied from 3x forInt32 variables to 100x for float32 and float64. the slowfloating-point computations were found not to be due tohardware limitations but most likely to be the result of incorrectcompiler switches used when compiling the Python applicationfor the tablet. © 2014 IEEE.

关键词： Mobile computing

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