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检索条件"任意字段=Proceedings - 16th Symposium on Computer Architecture and High Performance Computing"

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Opac: A Floating-point Coprocessor Dedicated to Compute-bound Kernels

Opac: A Floating-point Coprocessor Dedicated to Compute-boun...

引用

Annual International symposium on computer architecture, ISCA

作者： A. Seznec K. Courtel IRISA Anglet Aquitaine France

In many applications, the main part of the computations may be encapsulated in compute-bounds kernels. Achieving high performance on compute-bound primitives at a low hardware cost has became an important challenge. OPAC was designed as the basic cell of a floating-point coprocessor dedicated to the execution of compute-bound kernels. Due to efficient hardware mechanisms for controlling and sequencing a pipeline performance close to a floating-point multiply-add per cycle per cell is reached on applications such as solving linear systems, FFTs or correlations in a microprocessor environment.

关键词： Coprocessors Kernel Knowledge based systems Hardware high performance computing Costs Control systems Pipelines Linear systems Flexible printed circuits

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An Efficient architecture For Loop Based Data Preloading

An Efficient Architecture For Loop Based Data Preloading

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IEEE/ACM International symposium on Microarchitecture (MICRO)

作者： W.Y. Chen R.A. Bringmann S.A. MahIke R.E. Hank J.E. Sicolo Center for Reliable and High-Performance Computing University of Illinois Urbana IL USA Intel Corporation Santa Clara CA USA

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Hiding Memory Latency using Dynamic Scheduling in Shared-Memory Multiprocessors

Hiding Memory Latency using Dynamic Scheduling in Shared-Mem...

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Annual International symposium on computer architecture, ISCA

作者： K. Gharachorloo A. Gupta J. Hennessy Computer Systems Laboratory University of Stanford CA USA

the large latency of memory accesses is a major impediment to achieving high performance in large scale shared-memory multi- processors. Relaxing the memory consistency model is an attractive technique for hiding this latency by allowing the overlap of memory accesses with other computation and memory accesses. Previous studies on relaxed models have shown that the latency of write accesses can be hidden by buffering writes and allowing reads to bypass pending writes. Hiding the latency of reads by exploiting the overlap allowed by relaxed models is inherently more difficult, however, simply because the processor depends on the return value for its future computation. this paper explores the use of dynamically scheduled processors to exploit the overlap allowed by relaxed models for hiding the latency of reads. Our results are based on detailed simulation studies of several parallel applications. the results show that a substantial fraction of the read latency can be hidden using this technique. However, the major improvements in performance are achieved only at large instruction window sizes.

关键词： Delay Dynamic scheduling Yarn Permission Large-scale systems computer architecture high performance computing Laboratories Impedance Processor scheduling

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Dynamic Dependency Analysis of Ordinary Programs

Dynamic Dependency Analysis of Ordinary Programs

引用

Annual International symposium on computer architecture, ISCA

作者： T.M. Austin G.S. Sohi Computer Sciences Department University of Wisconsin Madison Madison WI USA

A quantitative analysis of program execution is essential to the computer architecture design process. With the current trend in architecture of enhancing the performance of uniprocessors by exploiting fine-grain parallelism, first-order metrics of program execution, such as operation frequencies, are not sufficient; characterizing the exact nature of dependencies between operations is essential. this paper presents a methodology for constructing the dynamic execution graph that characterizes the execution of an ordinary program (an application program written in an imperative language such as C or FORTRAN) from a serial execution trace of the program. It then uses the methodology to study parallelism in the SPEC benchmarks. We see that the parallelism can be bursty in nature (periods of lots of parallelism followed by periods of little parallelism), but the average parallelism is quite high, ranging from 13 to 23,302 operations per cycle. Exposing this parallelism requires renaming of both registers and memory, though renaming registers alone exposes much of this parallelism. We also see that fairly large windows of dynamic instructions would be required to expose this parallelism from a sequential instruction stream.

关键词： Parallel processing computer architecture Frequency Permission Process design Delay Registers computer aided instruction Concurrent computing Distributed computing

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Processor Coupling: Integrating Compile Time and Runtime Scheduling for Parallelism

Processor Coupling: Integrating Compile Time and Runtime Sch...

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Annual International symposium on computer architecture, ISCA

作者： S.W. Keckler W.J. Dally Artificial Intelligence Laboratory and Laboratory for Computer Science Massachusetts Institute of Technology Cambridge MA USA

the technology to implement a single-chip node composed of 4 high-performance floating-point ALUs will be available by 1995. this paper presents processor coupling, a mechanism for controlling multiple ALUs to exploit both instruction-level and inter- thread parallelism, by using compile time and runtime scheduling. the compiler statically schedules individual threads to discover available inter-thread instruction-level parallelism. the runtime scheduling mechanism interleaves threads, exploiting inter-thread parallelism to maintain high ALU utilization. ALUs are assigned to threads on a cycle by cycle basis, and several threads can be active concurrently. We provide simulation results demonstrating that, on four simple numerical benchmarks, processor coupling achieves better performance than purely statically scheduled or multi-processor machine organizations. We examine how performance is affected by restricted communication between ALUs and by long memory latencies. We also present an implementation and feasibility study of a processor coupled node.

关键词： Runtime Processor scheduling Parallel processing Yarn Concurrent computing Permission Laboratories Delay Artificial intelligence computer science

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Cache Replacement with Dynamic Exclusion

Cache Replacement with Dynamic Exclusion

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Annual International symposium on computer architecture, ISCA

作者： S. McFarling DEC Western Research Laboratory Palo Alto CA USA

Most recent cache designs use direct-mapped caches to pro- vide the fast access time required by modern high speed CPU's. Unfortunately, direct-mapped caches have higher miss rates than set-associative caches, largely because direct mapped caches are more sensitive to conflicts between items needed frequently in the same phase of program execution. this paper presents a new technique for reducing direct-mapped cache misses caused by conflicts for a particular cache line. A small finite state machine recognizes the common instruction reference patterns where storing an instruction in the cache actually harms performance. Such instructions are dynamically excluded, that is they are passed directly through the cache without being stored. this reduces misses to the instructions that would have been replaced. the effectiveness of dynamic exclusion is dependent on the severity of cache conflicts and thus on the particular program and cache size of interest. However, across the SPEC benchmarks, simulation results show an average reduction in miss rate of 33% for a 32KB instruction cache with 16B lines. In addition, applying dynamic exclusion to one level of a cache hierarchy can improve the performance of the next level since instructions do not need to be stored on both levels. Finally, dynamic exclusion also improves combined instruction and data cache miss rates.

关键词： Pattern recognition Permission Modems Automata Laboratories System performance Distributed computing Machinery Bandwidth Hardware

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Improved Multithreading Techniques for Hiding Communication Latency in Multiprocessors

Improved Multithreading Techniques for Hiding Communication ...

引用

Annual International symposium on computer architecture, ISCA

作者： B. Boothe A. Ranade Computer Science Division University of California Berkeley CA USA

Shared memory multiprocessors are considered among the easiest parallel computers to program. However building shared memory machines with thousands of processors has proved difficult because of the inevitably long memory latencies. Much previous research has focused on cache coherency techniques, but it remains unclear if caches can obtain sufficiently high hit rates. In this paper we present improved multithreading techniques that can easily tolerate latencies of hundreds of cycles, and yet only require a small number of threads per processor. high performance is achieved by introducing an explicit context switch instruction that can be used by a simple optimizing compiler to group together several shared accesses. this grouping of shared accesses dramatically reduces the frequency of context switches compared to simpler multithreading models. the combination of our techniques achieves efficiencies of 80% or higher on a broad set of applications.

关键词： Multithreading Delay Switches Prefetching Yarn Permission computer science Concurrent computing Optimizing compilers Frequency

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the DASH Prototype: Implementation and performance

The DASH Prototype: Implementation and Performance

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Annual International symposium on computer architecture, ISCA

作者： D. Lenoski J. Laudon T. Joe D. Nakahira L. Stevens A. Gupta J. Hennessy Computer Systems Laboratory University of Stanford Stanford CA USA

the fundamental premise behind the DASH project is that it is feasible to build large-scale shared-memory multiprocessors with hardware cache coherence. While paper studies and software simulators are useful for understanding many high-level design tradeoffs, prototypes are essential to ensure that no critical details are overlooked. A prototype provides convincing evidence of the feasibility of the design, allows one to accurately estimate both the hardware and the complexity cost of various features, and provides a platform for studying real workloads. A 16-processor prototype of the DASH multiprocessor has been operational for the last six months. In this paper, the hardware overhead of directory-based cache coherence in the prototype is examined. We also discuss the performance of the system, and the speedups obtained by parallel applications running on the prototype. Using a sophisticated hardware performance monitor, we characterize the effectiveness of coherent caches and the relationship between an application's reference behavior and its speedup.

关键词： Prototypes Large-scale systems Hardware Costs Logic Monitoring Permission Software prototyping Parallel architectures Delay

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Instruction-level Parallelism in Prolog: Analysis and Architectural Support

Instruction-level Parallelism in Prolog: Analysis and Archit...

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Annual International symposium on computer architecture, ISCA

作者： A. De Gloria P. Faraboschi Department of Biophysical anJElFtronic Engineering University of Genoa Genoa Italy

the demand of increasing computation power for symbolic processing has given a strong impulse to the development of ASICs dedicated to the execution of Prolog. Unlike past microcoded implementation based on the Warren Machine model, novel trends in high performance Prolog processors suggest the implementation of PJSC-based processors committed to Prolog only through the adoption of a few basic dedicated features, like the Berkeley Abstract Machine (BAM) processor. Following the idea of using a smart compiler for a simple instruction set, the SYMBOL project represents an experiment in applying global compaction techniques and VLIW design philosophy to the static exploitation of instruction-level parallelism in Prolog. this paper presents code analysis results and shows how we can approach the theoretical speed-up limit (about 3) imposed by Amdahl's law on shared memory models, by means of global code optimizations and a suitable architectural support. In addition, we show implemetation details and some preliminary data of a VLSI prototype architecture.

关键词： Magnesium compounds Parallel processing Permission Compaction Very large scale integration Prototypes Data analysis Hardware Concurrent computing Power engineering and energy

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Alternative Implementations of Two-Level Adaptive Branch Prediction

Alternative Implementations of Two-Level Adaptive Branch Pre...

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Annual International symposium on computer architecture, ISCA

作者： Tse-Yu Yeh Y.N. Patt Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

As the issue rate and depth of pipelining of high performance Superscalar processors increase, the importance of an excellent branch predictor becomes more vital to delivering the potential performance of a wide-issue, deep pipelined microarchitecture. We propose a new dynamic branch predictor (Two-Level Adaptive Branch Prediction) that achieves substantially higher accuracy than any other scheme reported in the literature. the mechanism uses two levels of branch history information to make predictions, the history of the last k branches encountered, and the branch behavior for the last s occurrences of the specific pattern of these k branches. We have identified three variations of the Two-Level Adaptive Branch Prediction, depending on how finely we re- solve the history information gathered. We compute the hardware costs of implementing each of the three variations, and use these costs in evaluating their relative effectiveness. We measure the branch prediction accuracy of the three variations of Two-Level Adaptive Branch Prediction, along with several other popular proposed dynamic and static prediction schemes, on the SPEC benchmarks. We show that the average prediction accuracy for Two-Level Adaptive Branch Prediction is 97 percent, while the other known schemes achieve at most 94.4 percent average prediction accuracy. We measure the effectiveness of different prediction algorithms and different amounts of history and pattern information. We measure the costs of each variation to obtain the same prediction accuracy.

关键词： History Pipeline processing Costs Accuracy Permission Runtime Microarchitecture Hardware Prediction algorithms Distributed computing

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