the replication of data objects in a large computer network is a difficult task which cannot be approached by simply employing the techniques used in small networks, because the high replication factors possible raise...
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the replication of data objects in a large computer network is a difficult task which cannot be approached by simply employing the techniques used in small networks, because the high replication factors possible raise new issues which must be addressed. the paper presents a solution to the problem of managing replicas in a large scale environment. the solution is based on a multi-level quorum algorithm for maintaining the consistency of replicas, a probabilistic addressing mechanism for efficiently locating replicas in the system and an efficient scheme for handling dynamic changes in the number of replicas. the feasibility of this approach is demonstrated by presenting performance measurements in a simulated network.< >
this paper presents the modeling and simulation of a multiprocessor architecture. the methodology included cycle-by-cycle uniprocessor simulation, trace driven multiprocessor simulation, and high-level simulation in a...
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this paper presents the modeling and simulation of a multiprocessor architecture. the methodology included cycle-by-cycle uniprocessor simulation, trace driven multiprocessor simulation, and high-level simulation in an architecture design and assessment system (ADAS). the multiprocessor was designed for digital signal processing (DSP) and used single-chip Intel i860 processors with a shared global memory. the ADAS simulations were found to be most useful for initial simulations, scheduling, and feasibility assessment. the trace driven simulations were found to be very useful for predicting exact performance and for evaluating changes to the DSP algorithms.< >
Analyzing the tonality of a melody is a sophisticated problem in music theory but this work may be done by a computer. this paper outlines the architecture and design principles of an experimental system for analyzing...
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the issue of I/O device access in HARTS (Hexagonal architecture for Real-Time Systems)--a distributed real-time computer system under construction at the University of Michigan--is explicitly addressed. Several candid...
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ISBN:
(纸本)0818620471
the issue of I/O device access in HARTS (Hexagonal architecture for Real-Time Systems)--a distributed real-time computer system under construction at the University of Michigan--is explicitly addressed. Several candidate solutions are introduced, explored, and evaluated according to cost, complexity, reliability, and performance: (1) 'node-direct' distribution withthe intranode bus and a local I/O bus;(2) use of dedicated I/O nodes, which are placed in the hexagonal mesh as regular applications nodes, but which provide I/O services rather than computing services;and (3) use of a separate I/O network;which has led to the proposal of an 'interlaced' I/O network. the interlaced I/O network is intended to provide bothhighperformance without burdening node processors with I/O overhead and a high degree of reliability. Both static and dynamic multiownership protocols are developed for managing I/O device access in this I/O network. the relative merits of the two protocols are explored, and the performance and accessibility which each provides are simulated.
Multiprocessor system are envisaged for use in applications requiring highcomputing power, fault tolerance, and time critical areas. Designs of such system are qualified using modeling and simulations. the developmen...
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the performance evaluation, workload characterization, and trace-driven simulation of a hypercube multicomputer running realistic workloads are presented. Six representative parallel applications were selected as benc...
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the performance evaluation, workload characterization, and trace-driven simulation of a hypercube multicomputer running realistic workloads are presented. Six representative parallel applications were selected as benchmarks. Software monitoring techniques were then used to collect execution traces. On the basis of the measurement results, the authors investigated boththe computation and communication behavior of these parallel programs, including CPU utilization, computation task granularity, message interarrival distribution, the distribution of waiting times in receiving messages, and message length and destination distributions. the localities in communication were also studied. A trace-driven simulation environment was developed to study the behavior of the communication hardware under real workloads. Simulation results on DMA and link utilizations are reported.< >
the issue of I/O device access in HARTS (Hexagonal architecture for Real-Time Systems)-a distributed real-time computer system under construction at the University of Michigan-is explicitly addressed. Several candidat...
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the issue of I/O device access in HARTS (Hexagonal architecture for Real-Time Systems)-a distributed real-time computer system under construction at the University of Michigan-is explicitly addressed. Several candidate solutions are introduced, explored and evaluated according to cost, complexity, reliability, and performance: (1) 'node-direct' distribution withthe intranode bus and a local I/O bus; (2) use of dedicated I/O nodes, which are placed in the hexagonal mesh as regular applications nodes, but which provide I/O services rather than computing services; and (3) use of a separate I/O network; which has led to the proposal of an 'interlaced' I/O network. the interlaced I/O network is intended to provide bothhighperformance without burdening node processors with I/O overhead and a high degree of reliability. Both static and dynamic multiownership protocols are developed for managing I/O device access in this I/O network. the relative merits of the two protocols are explored, and the performance and accessibility which each provides are simulated.< >
the MIPS R6000 microprocessor relies on a new type of translation lookaside buffer, called a TLB slice, which is less than one-tenththe size of a conventional TLB and as fast as one multiplexer delay, yet has a high ...
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the MIPS R6000 microprocessor relies on a new type of translation lookaside buffer, called a TLB slice, which is less than one-tenththe size of a conventional TLB and as fast as one multiplexer delay, yet has a high enough hit rate to be practical. the fast translation makes it possible to use a physical cache without adding a translation stage to the processor's pipeline. the small size makes it possible to include address translation on-chip, even in a technology with a limited number of devices. the key idea behind the TLB slice is to have both a virtual tag and a physical tag on a physically indexed cache.< >
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