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A study of I/O behavior of Perfect benchmarks on a multiprocessor

A study of I/O behavior of Perfect benchmarks on a multiproc...

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Annual International symposium on computer architecture, ISCA

作者： A.L.N. Reddy P. Banerjee Center for Reliable and High Performance Computing University of Illinois Urbana IL USA

the I/O behavior of some scientific applications, a subset of Perfect benchmarks, executing on a multiprocessor is studied. the aim of this study is to explore the various patterns of I/O access of large scientific applications, and to understand the impact of this observed behavior on the I/O subsystem architecture. I/O behavior of the program is characterized by the demands it imposes on the I/O subsystem. It is observed that implicit I/O or paging is not a major problem for the applications considered and the I/O problem is mainly manifest in the explicit I/O done in the program. Various characteristics of I/O accesses are studied, and their impact on architecture design is discussed.< >

关键词： Read-write memory Benchmark testing Atmospheric modeling Samarium Strontium Navier-Stokes equations Time measurement Emulation Parallel machines Supercomputers

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Generation and analysis of very long address traces

Generation and analysis of very long address traces

引用

Annual International symposium on computer architecture, ISCA

作者： A. Borg R.E. Kessler D.W. Wall Western Research Laboratory Digital Equipment Corporation Palo Alto CA USA Computer Sciences Department University of Wisconsin Madison Madison WI USA

Existing methods of generating and analyzing traces suffer from a variety of limitations, including complexity, inaccuracy, short length, inflexibility, or applicability only to CISC (complex-instruction-set-computer) machines. the authors use a trace-generation mechanism based on link-time code modification which is simple to use, generates accurate long traces of multiuser programs, runs on a RISC (reduced-instruction-set-computer) machine, and can be flexibly controlled. Accurate performance data for large second-level caches can be obtained by on-the-fly analysis of the traces. A comparison is made of the performance of systems with 512 K to 16 M second-level caches, and it is show that, for today's large programs, second-level caches of more than 4 MB may be unnecessary. It is also shown that set associativity in second-level caches of more than 1 MB does not significantly improve system performance. In addition, the experiments provide insights into first-level and second-level cache line size.< >

关键词： Reduced instruction set computing performance analysis System performance Computational modeling Laboratories Adders Pattern analysis Drives Analytical models computer simulation

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Strategies for predictability in real-time data-flow architectures

Strategies for predictability in real-time data-flow archite...

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Real-Time Systems symposium (RTSS)

作者： S. Som R.R. Mielke J.W. Stoughton Department of Electrical & Computer Engineering Old Dominion University Norfolk VA USA

Consideration is given to the development of strategies for predictable performance in homogeneous multicomputer data-flow architectures operating in real-time. Algorithms are restricted to the class of large-grained, decision-free algorithms. the mapping of such algorithms onto the specified class of data-flow architectures is realized by a new marked graph model called ATAMM (algorithm to architecture mapping model). Algorithm performance and resource needs are determined for predictable periodic execution of algorithms, which is achieved by algorithm modification and input data injection control. performance is gracefully degraded to adapt to decreasing numbers of resources. the realization of the ATAMM model on a VHSIC four processor testbed is described. A software design tool for prediction of performance and resource requirements is described and is used to evaluate the performance of a space surveillance algorithm.< >

关键词： Signal processing algorithms Military computing computer architecture Application software Computational modeling Prediction algorithms Process control Very high speed integrated circuits Aerospace control Algorithm design and analysis

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An empirical evaluation of two memory-efficient directory methods

An empirical evaluation of two memory-efficient directory me...

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Annual International symposium on computer architecture, ISCA

作者： B.W. O'Krafka A.R. Newton Department of Electrical Engineering & Computer Sciences University of California Berkeley USA

the authors present an empirical evaluation of two memory-efficient directory methods for maintaining coherent caches in large shared-memory multiprocessors. Both directory methods are modifications of a scheme proposed by L.M. Censier and P. Feautrier (1978) that does not rely on a specific interconnection network and can be readily distributed across interleaved main memory. the schemes considered here overcome the large amount of memory required for tags in the original scheme in two different ways. In the first scheme each main memory block is sectored into sub-blocks for which the large tag overhead is shared. In the second scheme a limited number of large tags are stored in an associative cache and shared among a much larger number of main memory blocks. Simulations show that in terms of access time and network traffic both directory methods provide significant performance improvements over a memory system in which shared-writable data are not cached. the large block sizes required for the sectored scheme, however, promote sufficient false sharing for its performance to be markedly worse than when a tag cache is used.< >

关键词： Hardware Multiprocessor interconnection networks Computational modeling Circuit simulation Telecommunication traffic Traffic control Acceleration computer aided instruction high performance computing Costs

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Real-time communication in multiple token ring networks

Real-time communication in multiple token ring networks

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Real-Time Systems symposium (RTSS)

作者： Y.-H. Lee L.-T. Shen Department of Computer & Information Science University of Florida FL USA

A communication architecture and a dynamic control protocol are presented for real-time communication in multiple token ring networks. the network can be formed by multiple channels through bandwidth subdivision of a high-speed ring. A flexible preemption and dynamic load allocation scheme is developed which can reduce the lost percentage of critical packets and can maintain a high channel utilization at the same time. this performance improvement is demonstrated with extensive simulation results.< >

关键词： Intelligent networks Token networks Protocols FDDI Communication system control Bandwidth Real time systems Delay Distributed computing Communication networks

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A multiprocessor computer system for integrated numeric and symbolic computation

A multiprocessor computer system for integrated numeric and ...

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IEEE International symposium on Intelligent Control (ISIC)

作者： T.J. Goblick P.G. Harmon J.I. Leivent J.J. Olsen D.S. Cogen J.J. DiTuri P.G. McHugh R.L. Walton Lincoln Laboratory Massachusetts Institute of Technology Lexington MA USA

A class of problems, called signal understanding (SU) systems, that involves intensive numeric, as well as symbolic testing, is considered. A shared-memory multiprocessor computer system designed specifically to facilitate the development and evaluation of parallel SU algorithms, which would be a basic tool for developing real-time SU systems, is described. this machine, called the MX-1, runs Common LISP, which has been augmented with extensions for user-directed parallelism. It is, in essence, a parallel LISP machine with digital signal processors (DSPs) integrated into the architecture to provide powerful numeric computational capability. the MX-1 has 16 crossbar interconnected processing nodes, each with a Motorola 68020 CPU operating at 16 MHz, 8 Mbytes of dynamic random-access memory and its own Weitek DSP coprocessor that can do 10 million multiply-accumulate operations per second. high-speed I/O ports are provided for direct entry of sensor data into the DSPs. Two 4-node systems and a 16-node system have been fabricated, and several applications have been run on the systems.< >

关键词： Digital signal processing Concurrent computing System testing Algorithm design and analysis Signal processing algorithms Real time systems Parallel processing Digital signal processors computer architecture Power system interconnection

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the pixel machine: A parallel image computer 89

The pixel machine: A parallel image computer

引用

16th Annual Conference on computer Graphics and Interactive Techniques, SIGGRAPH 1989

作者： Potmesil, Michael Hoffert, Eric M. AT and T Bell Laboratories HolmdelNJ United States

ISBN: (纸本)0897913124

We describe the system architecture and the programming environment of the Pixel Machine -A parallel image computer with a distributed frame buffer. the architecture of the computer is based on an array of asynchronous MIMD nodes with parallel access to a large frame buffer. the machine consists of a pipeline of pipe nodes which execute sequential algorithms and an array of m x n pixel nodes which execute parallel algorithms. A pixel node directly accesses every m-th pixel on every n-th scan line of an interleaved frame buffer. Each processing node is based on a high-speed, floating-point programmable processor. the programmability of the computer allows all algorithms to be implemented in software. We present the mappings of a number of geometry and image-computing algorithms onto the machine and analyze their performance.

关键词： Pixels

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high performance Prolog processor with multiple function units.

High performance Prolog processor with multiple function uni...

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16th Annual International symposium on computer architecture

作者： Singhal, Ashok Patt, Yale N. Univ of California Berkeley CA USA

A description is given of the Parallel Unification Machine (PLUM), a Prolog processor that exploits fine-grain parallelism using multiple function units executing in parallel. In most cases the execution of bookkeeping instruction is almost completely overlapped by unification, and the performance of the processor is limited only by the available unification parallelism. Measurements from a register transfer level simulator of PLUM are presented. the results show that PLUM with three unification units achieves an average speedup of approximately 3.4 over the Berkeley VLSI-PLM, which is usually regarded as the current highest-performance special-purpose, pipelined Prolog processor. Measurements that show the effects of multiple unification units and memory access time on performance are also presented.

关键词： computers, Digital

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high performance communications in processor networks. 89

High performance communications in processor networks.

引用

16th Annual International symposium on computer architecture

作者： Jesshope, C.R. Miller, P.R. Yantchev, J.T. Univ of Southampton Southampton Engl

ISBN: (纸本)9780897913195

To provide an arbitrary and fully dynamic connectivity in a network of processors, transport mechanisms must be implemented to provide the propagation of data from processor to processor, on the basis of addresses contained within a packet of data. Such data transport mechanisms must satisfy a number of requirements - deadlock and livelock freedom, good hot-spot performance, high throughput, and low latency. the authors propose a solution of these problems that allows deadlock-free, adaptive, high-throughput packet routing to be implemented on networks of processors. Examples that illustrate the technique for 2-D array and toroidal networks are given. An implementation of this scheme on arrays of transputers is described. the scheme also serves as a basis for a very low latency routing strategy named the mad postman, a detailed implementation of which is described here as well.

关键词： computers, Digital

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Ε psilon dataflow processor.

Ε psilon dataflow processor.

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16th Annual International symposium on computer architecture

作者： Grafe, V.G. Davidson, G.S. Hoch, J.E. Holmes, V.P. Sandia Natl Lab Albuquerque NM USA

the Εpsilon dataflow architecture is designed for high-speed uniprocessor execution as well as for parallel operation in a multiprocessor system. the Εpsilon architecture directly matches ready operands, thus eliminating the need for associative matching stores. Εpsilon also supports low-cost data fanout and critical sections. A 10-MFLOPS (millions of floating-point operations per second) CMOS/TTL processor prototype is running, and its performance has been measured with several benchmarks. the prototype has demonstrated sustained performance exceeding that of comparable control-flow processors running at high clock rates (three times faster than a 20-MHz transputer and 24 times faster than a Sun on a suite of arithmetic tests, for example).

关键词： computer systems, Digital

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