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New architectures for a new biology

New architectures for a new biology

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12th International symposium on high-performance computer architecture

作者： Shaw, David E. Columbia Univ Ctr Computat Biol & Bioinformat New York NY 10027 USA

ISBN: (纸本)0780393686

Some of the most important outstanding questions in the fields of biology, chemistry, and medicine remain unsolved as a result of our limited understanding of the structure, behavior and interaction of biologically significant molecules. the laws of physics that determine the form and function of these biomolecules are well understood. Current technology, however, does not allow us to simulate the effect of these laws with sufficient accuracy, and for a sufficient period of time, to answer many of the questions that biologists, biochemists, and biomedical researchers are most anxious to answer. this talk will describe the current state of the art in biomolecular simulation and explore the potential role of high-performance computing technologies in extending current capabilities. Efforts within our own lab to develop novel architectures and algorithms to accelerate molecular dynamics simulations by several orders of magnitude will be described, along with work by other researchers pursuing alternative approaches. If such efforts ultimately prove successful, one might imagine the emergence of an entirely new paradigm in which computational experiments take their place alongside those conducted in "wet" laboratories as central tools in the quest to understand living organisms at a molecular level, and to develop safe, effective, precisely targeted medicines capable of relieving suffering and saving human lives. © 2006 IEEE.

关键词： computer architecture

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Runtime system support for running applications with dynamic and. asynchronous task parallelism in software DSM systems

Runtime system support for running applications with dynamic...

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18th International symposium on computer architecture and high performance computing

作者： Mendes, Rafael Whately, Lauro de Castro, Maria Clicia Bentes, Cristiana Amorim, Claudio Luis Univ Fed Rio de Janeiro COPPE Rio de Janeiro Brazil Univ Estado Rio De Janeiro IME Rio De Janeiro Brazil Univ Estado Rio De Janeiro DESC Rio De Janeiro Brazil

ISBN: (纸本)0769527043

State-of-the-art software distributed shared-memory systems (SDSMs) provide a cost-effective solution to run single-program-multiple-data (SPMD) applications on clusters of distributed memory computers. However, SDSMs are unsuitable for running applications with dynamic, highly asynchronous task parallelism (ATP), such as graphics, simulators, and decision support systems. In ATP-based applications, the execution of tasks depends not only on the input data but also on the variable amount of data that each task produces at runtime, which generates high load imbalance and communication traffic that degrades performance of SDSM systems drastically. In this work, we propose a new load balancing (LB) mechanism to enable SDSM systems to support dynamic task scheduling as required by ATP applications. To evaluate the benefits of our LB mechanism, we developed Clik a new multithreaded SDSM system with automatic load balancing. Our preliminary performance results of Clik running on a 16-node Linux SMP cluster for five ATP applications showed that Clik attained significant speedups. For four of our five applications, the speedups varied from 7.2 up to 13.8 on 16 processors.

关键词： Storage allocation (computer)

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the pixel machine: A parallel image computer 89

The pixel machine: A parallel image computer

引用

16th Annual Conference on computer Graphics and Interactive Techniques, SIGGRAPH 1989

作者： Potmesil, Michael Hoffert, Eric M. AT and T Bell Laboratories HolmdelNJ United States

ISBN: (纸本)0897913124

We describe the system architecture and the programming environment of the Pixel Machine -A parallel image computer with a distributed frame buffer. the architecture of the computer is based on an array of asynchronous MIMD nodes with parallel access to a large frame buffer. the machine consists of a pipeline of pipe nodes which execute sequential algorithms and an array of m x n pixel nodes which execute parallel algorithms. A pixel node directly accesses every m-th pixel on every n-th scan line of an interleaved frame buffer. Each processing node is based on a high-speed, floating-point programmable processor. the programmability of the computer allows all algorithms to be implemented in software. We present the mappings of a number of geometry and image-computing algorithms onto the machine and analyze their performance.

关键词： Pixels

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high-performance traffic classification on GPU 26

High-performance traffic classification on GPU

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26th International symposium on computer architecture and high performance computing, SBAC-PAD 2014

作者： Zhou, Shijie Nittoor, Prashant Rao Prasanna, Viktor K. Ming Hsieh Department of Electrical Engineering University of Southern California Los AngelesCA90089 United States

ISBN: (纸本)9781479969043

Traffic classification is an essential task in network management. Recently, there has been a new trend in exploring Graphics Processing Unit (GPU) for network applications. these applications typically do not perform floating point operations and obtaining speedup can be challenging. In this paper, we design a high-performance traffic classifier based on an alternate representation of the C4.5 decision-tree algorithm and implement it using Compute Unified Device architecture (CUDA). To remedy the unbalanced nature of the decision-trees arising in traffic classification, we convert the C4.5 decision-tree into a set of completely balanced range-trees. Classification is performed by searching the range-trees and merging the search results. We optimize our design by storing the range-trees using compact arrays without explicit pointers in shared memory. By exploiting thread level parallelism, we develop throughput-optimized as well as latency-optimized designs. Experimental results show that for a typical decision-tree containing 128 leaf nodes and 6 features, our design achieves a throughput of over 1600 million classifications per second (MCPS). Compared with the state-of the-art multi-core implementation, our design demonstrates 16x improvement with respect to throughput. We also demonstrate similar performance improvements on a variety of decision-trees with respect to number of leaf nodes, structure of the tree and number of features. © 2014 IEEE.

关键词： Graphics processing unit

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Fiber optic backplane for reducing HIRF effects in fault tolerant computing platforms

Fiber optic backplane for reducing HIRF effects in fault tol...

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proceedings of the 1997 16th AIAA/IEEE Digital Avionics Systems, DASC. Part 1 (of 2)

作者： Malekpour, Mahyar NASA Langley Research Cent

the design and development of a fault-tolerant fiber-optic backplane to reduce the effects of electromagnetic environments (EME) on flight critical computing platforms is presented. the backplane was developed at the NASA Langley Research Center, and is currently undergoing analysis, simulation, and tests. the simulation results of tests on the backplane in the advent of simulated high Intensity Radiated Fields (HIRF) induced faults are presented, and the fault recovery capability of the architecture is demonstrated. the architecture was designed, developed, and implemented using the Very high Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL). the architecture was synthesized and implemented in hardware using Field Programmable Gate Arrays (FPGA) on multiple Personal computer (PC) boards.

关键词： Fault tolerant computer systems

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Benefits of alternate XML serialization formats in scientific computing

Benefits of alternate XML serialization formats in scientifi...

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16th International symposium on high performance Distributed computing 2007, HPDC'07 and Co-Located Workshops

作者： Kangasharju, Jaakko Tarkoma, Sasu Helsinki Institute for Information Technology PO Box 9800 FIN-02015 TKK Finland

ISBN: (纸本)159593717X

XML is a widely-used technology for interoperable data representation, and its scope of usage has widened even more in recent years. However, this expansion of XML's application areas has identified limitations and inefficiencies that seem inherent in XML due to its verbosity and redundancy. Because of this, various industry groups and standardization organizations have undertaken to define alternate representations of XML data to better address their needs while still retaining compatibility with XML. this paper provides an overview of the arguments in favor of a binary format in scientific computing, of work done in this area by the W3C, and some benchmarks comparing XML with various processing techniques available with binary formats. Copyright 2007 ACM.

关键词： XML

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A fast topology inference: A building block for network-aware parallel processing 07

A fast topology inference: A building block for network-awar...

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16th International symposium on high performance Distributed computing 2007, HPDC'07 and Co-Located Workshops

作者： Shirai, Tatsuya Saito, Hideo Taura, Kenjiro University of Tokyo 7-3-1 Hongo Bunkyo-ku Tokyo Japan

ISBN: (纸本)1595936734

Adapting to the network is the key to achieving high performance for communication-intensive applications, including scientific computing,data intensive computing, and multicast, especially in Grid environments. this paper investigates an approach of representing network as a tree of participating hosts and switches matching or approximating their physical topology, and describes a fast, non-intrusive, and portable algorithm for inferring such a topology. this representation and the proposed inference algorithm serves as a key to building network-aware applications in a portable manner. the algorithm is based solely on RTTs of small packets between end hosts;it does not rely on popular but not universally available protocols such as trace route and SNMP. Another benefit is that it can handle all layers of network uniformly without any a priori knowledge of cluster configurations. the required number of measurements is O(Nd) in certain idealizing assumptions made for the purpose of analysis, where N is the number of participating processes and d the diameter of the network, which is usually small in real networks. In our experimental environment, the inference algorithm built a topology of 64 hosts in a single cluster in 4 seconds and and that of 256 hosts across 4 clusters in 15 seconds. It is able to not only identify clusters within a Grid, but also to partially identify the Layer 2 topology within a cluster. this is important for optimizing bandwidth-limited operations such as broadcast. We built several network-aware applications upon the inference system, including efficient bandwidth measurements and long message broadcasts. the topology is used to schedule as many measurements as possible in parallel without competing on shared links. We were able to build a bandwidth map of 256 hosts across 4 clusters in 27 seconds. Copyright 2007 ACM.

关键词： computer networks

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Adaptive compressed caching: Design and implementation 15

Adaptive compressed caching: Design and implementation

引用

15th symposium on computer architecture and high performance computing

作者： de Castro, RS do Lago, AP Da Silva, D Univ Sao Paulo Dept Comp Sci BR-05508 Sao Paulo Brazil

ISBN: (纸本)0769520464

In this paper, we reevaluate the use of adaptive compressed caching in order to improve system performance through reduction of accesses to the backing stores. We propose a new and simple adaptability policy that adjusts the compressed cache size on-the-fly, and evaluate a compressed caching system with this policy through an implementation in a widely used operating system, Linux. We also redesign compressed caching in order to provide performance improvements for all tested workloads and address the problems faced in previous works and implementations that led to non-conclusive results. Among these fundamental modifications, our compressed cache is the first one to also compress file cache pages, to adaptively disable compression of clean pages when necessary and to address applications with poor compressibility. We tested a system with our adaptive compressed cache under many applications and benchmarks, each one with different memory pressures. the results showed performance improvements (up to 171.4%) in all of them if under memory pressure, and minimal overhead (up to 0.39%) when there is very light memory pressure. We believe this work shows that this adaptive compressed cache design should be actually considered as an effective mechanism for improvement in system performance.

关键词： Adaptive systems Benchmark testing computer science Data compression Hard disks Kernel Linux Operating systems System performance System testing

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Design and Evaluation of AWGR-based Photonic NoC architectures for 2.5D Integrated high performance computing Systems 23

Design and Evaluation of AWGR-based Photonic NoC Architectur...

引用

23rd IEEE International symposium on high performance computer architecture (HPCA)

作者： Grani, Paolo Proietti, Roberto Akella, Venkatesh Ben Yoo, S. J. Univ Calif Davis Dept Elect & Comp Engn Davis CA 95616 USA

ISBN: (纸本)9781509049851

In future performance improvement of the basic building block of supercomputers has to come through increased integration enabled by 3D (vertical) and 2.5D (horizontal) die-stacking. But to take advantage of this integration we need an interconnection network between the memory and compute die that not only can provide an order of magnitude higher bandwidth but also consume an order of magnitude less power than today's state of the art electronic interconnects. We show how Arrayed Waveguide Grating Router-based photonic interconnects implemented on the silicon interposer can be used to realize a 16 x 16 photonic Network-on-Chip (NoC) with a bisection bandwidth of 16 Tb/s. We propose a baseline network, which consumes 2.57 pJ/bit assuming 100% utilization. We show that the power is dominated by the electro-optical interface of the transmitter, which can be reduced by a more aggressive design that improves the energy per bit to 0.454 pJ/bit at 100% utilization. Compared to recently proposed interposer-based electrical NoC's we show an average performance improvement of 25% on the PARSEC benchmark suite on a 64-core system using the Gem5 simulation framework.

关键词： Bandwidth Photonics Arrayed waveguide gratings Ports (computers) Multiprocessor interconnection Topology

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VIA: A Smart Scratchpad for Vector Units with Application to Sparse Matrix Computations 27

VIA: A Smart Scratchpad for Vector Units with Application to...

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27th IEEE International symposium on high-performance computer architecture (HPCA)

作者： Pavon, Julian Valdivieso, Ivan Vargas Barredo, Adrian Marimon, Joan Moreto, Miquel Moll, Francesc Unsal, Osman Valero, Mateo Cristal, Adrian Barcelona Supercomp Ctr Barcelona Spain Univ Politecn Cataluna Barcelona Spain

ISBN: (纸本)9781665422352

Sparse matrix operations are critical kernels in multiple application domains such as high performance computing, artificial intelligence and big data. Vector processing is widely used to improve performance on mathematical kernels with dense matrices. Unfortunately, existing vector architectures do not cope well with sparse matrix computations, achieving much lower performance in comparison with their dense counterparts. To overcome this limitation, we present the Vector Indexed architecture (VIA), a novel hardware vector architecture that accelerates applications with irregular memory access patterns such as sparse matrix computations. there are two main bottlenecks when computing with sparse matrices: irregular memory accesses and index matching. VIA addresses these two bottlenecks with a smart scratchpad that is tightly coupled to the Vector Functional Units within the core. thanks to this structure, VIA improves locality for sparse-dense computations and improves the index matching search process for sparse computations. As a result, VIA achieves significant performance speedup over highly optimized state-of-the-art C++ algebra libraries. On average, VIA outperforms sparse matrix vector multiplication, sparse matrix addition and sparse matrix matrix multiplication kernels by 4.22 x, 6.14x and 6.00 x, respectively, when evaluated over a thousand sparse matrices that arise in real applications. In addition, we prove the generality of VIA by showing that it can accelerate histogram and stencil applications by 4.5x and 3.5x, respectively.

关键词： Sparse Algebra Vector computing Scratchpad Memory

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