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ARRG: Real-world gossiping 07

ARRG: Real-world gossiping

引用

16th International symposium on high performance Distributed computing 2007, HPDC'07 and Co-Located Workshops

作者： Drost, Niels Ogston, Elth Van Nieuwpoort, Rob V. Bal, Henri E. Department of Computer Science Vrije Universiteit Amsterdam Netherlands

ISBN: (纸本)1595936734

Gossiping is an effective way of disseminating information in large dynamic systems. Until now, most gossiping algorithms have been designed and evaluated using simulations. However, these algorithms often cannot cope with several real-world problems that tend to be overlooked in simulations, such as node failures, message loss, non-atomicity ofinformation exchange, and firewalls. We explore the problems in designing and applying gossiping algorithms in real systems. Next to identifying the most prominent real-world problems and their current solutions, we introduce Actualized Robust Random Gossiping (ARRG), an algorithm specifically designed to take all of these real-world problems into account simultaneously. To address network connectivity problems such as firewalls we introduce a novel technique, the Fallback Cache. this cache can be applied to existing gossiping algorithms to improve their resilience against connectivity problems. We introduce a new metric, Perceived Network Size to measure a gossiping algorithm's effectiveness. In contrast to existing metrics, our new metric does not require global knowledge. Evaluation of ARRG and the Fallback Cache in a number of realistic scenarios shows that the proposed techniques significantly improve the performance of gossiping algorithms in networks with limited connectivity. Even in pathological situations, with 50% message loss and with 80% of the nodes behind a NAT, ARRG continues to work well. Existing algorithms fail in these circumstances. Copyright 2007 ACM.

关键词： Information dissemination

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InfoGram:: A grid service that supports both information queries and job execution 11

InfoGram:: A grid service that supports both information que...

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11th IEEE International symposium on high performance Distributed computing (HPDC-11)

作者： von Laszewski, G Gawor, J Peña, CJ Foster, I Argonne Natl Lab Argonne IL 60439 USA

ISBN: (纸本)0769516866

the research described in this paper is performed as part of the Globus Project. It introduces a new Grid service called InfoGram that combines the ability of serving as information service and as a job execution service. Previously, both services were architected and implemented within the Globus Toolkit as two different services with different wire protocols. Our service demonstrates a significant simplification of the architecture while treating job submissions and information queries alike. the advantage of our service is that it provides backwards compatibility to existing Grid services, while at the same time providing forwards compatibility to the emerging Web services world. Part of the work conducted within this effort is already reused by the current Open Grid Services architecture prototype implementation.

关键词： computer architecture computer science Information security Laboratories Project management Protocols Prototypes Resource management Web services Wire

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thin, high performance computing over the Internet

Thin, high performance computing over the Internet

引用

8th International symposium on Modeling, Analysis and Simulation of computer and Telecommunication Systems

作者： Keeley, T Sun Microsyst Inc Informat Technol Palo Alto CA 94303 USA

ISBN: (纸本)076950728X

this talk is an exploration of the genesis, methods, and futures of thin, high-performance business computing over the Internet, as referenced in Sun's invention and experience in this field. the presentation will delve into why and how this computing method will become increasingly important in the evolution of technologies to satisfy a global workforce that is becoming increasingly mobile while interacting across geographic boundaries.

关键词： Internet

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A new multi-processor architecture for parallel lazy cyclic reference counting

A new multi-processor architecture for parallel lazy cyclic ...

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17th International symposium on computer architecture and high performance computing, SBAC-PAD 2005

作者： Lins, Rafael Dueire Departamento de Eletrônica e Sistemas Universidade Federal de Pernambuco Recife PE Brazil

Reference counting is the memory management technique of most widespread use today. this paper presents a new multi-processor architecture for parallel cyclic reference counting. In this architecture, there is no dire... 详细信息

ISBN: (纸本)076952446X

关键词： computer architecture

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A Study of APIs for Graph Analytics Workloads 16

A Study of APIs for Graph Analytics Workloads

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16th IEEE International symposium on Workload Characterization (IISWC)

作者： Lee, Hochan Wong, David Hoang, Loc Dathathri, Roshan Gill, Gurbinder Jatala, Vishwesh Kuck, David Pingali, Keshav Univ Texas Austin Austin TX 78712 USA Intel Corp Santa Clara CA 95051 USA

ISBN: (纸本)9781728176451

Traditionally, parallel graph analytics workloads have been implemented in systems like Pregel, GraphLab, Galois, and Ligra that support graph data structures and graph operations directly. An alternative approach is to express graph workloads in terms of sparse matrix kernels such as sparse matrix-vector and matrix-matrix multiplication. An API for these kernels has been defined by the GraphBLAS project. the SuiteSparse project has implemented this API on shared-memory platforms, and the LAGraph project is building a library of graph algorithms using this API. How does the matrix-based approach perform compared to the graph-based approach? Our experiments on a 56 core CPU show that for representative graph workloads, LAGraph/SuiteSparse solutions are 5x slower on the average than Galois solutions. We argue that this performance gap arises from inherent limitations of a matrix-based API: regardless of which architecture a matrixbased algorithm is run on, it is subject to the same inherent limitations of the matrix-based API.

关键词： graph analytics performance study Graph-BLAS high performance computing

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Balancing DRAM Locality and Parallelism in Shared Memory CMP Systems

Balancing DRAM Locality and Parallelism in Shared Memory CMP...

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18th IEEE International symposium on high-performance computer architecture (HPCA)

作者： Jeong, Min Kyu Yoon, Doe Hyun Sunwoo, Dam Sullivan, Mike Lee, Ikhwan Erez, Mattan Univ Texas Austin Dept Elect & Comp Engn Austin TX 78712 USA Hewlett Packard Labs Intelligent Infrastruct Lab Palo Alto CA USA ARM Inc Cambridge England

ISBN: (纸本)9781467308243;9781467308267

Modern memory systems rely on spatial locality to provide high bandwidth while minimizing memory device power and cost. the trend of increasing the number of cores that share memory, however, decreases apparent spatial locality because access streams from independent threads are interleaved. Memory access scheduling recovers only a fraction of the original locality because of buffering limits. We investigate new techniques to reduce inter-thread access interference. We propose to partition the internal memory banks between cores to isolate their access streams and eliminate locality interference. We implement this by extending the physical frame allocation algorithm of the OS such that physical frames mapped to the same DRAM bank can be exclusively allocated to a single thread. We compensate for the reduced bank-level parallelism of each thread by employing memory sub-ranking to effectively increase the number of independent banks. this combined approach, unlike memory bank partitioning or sub-ranking alone, simultaneously increases overall performance and significantly reduces memory power consumption.

关键词： parallelism spatial locality Memory shared memory core Memory Bank DRAM1 gene Synclitism high-bandwidth thREADS Memory Power consumption Banks Access new technique

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Designing high performance Heterogeneous Broadcast for Streaming Applications on GPU Clusters 28

Designing High Performance Heterogeneous Broadcast for Strea...

引用

28th IEEE International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Chu, C. -H. Hamidouche, K. Subramoni, H. Venkatesh, A. Elton, B. Panda, D. K. Ohio State Univ Dept Comp Sci & Engn Columbus OH 43210 USA Engility Corp Dayton OH USA

ISBN: (纸本)9781509061082

high-performance streaming applications are beginning to leverage the compute power offered by graphics processing units (GPUs) and high network throughput offered by high performance interconnects such as InfiniBand (IB) to boost their performance and scalability. these applications rely heavily on broadcast operations to move data, which is stored in the host memory, from a single source-typically live-to multiple GPU-based computing sites. While homogeneous broadcast designs take advantage of IB hardware multicast feature to boost their performance, their heterogeneous counter-part requires an explicit data movement between Host and GPU, which significantly hurts the overall performance. there is a dearth of efficient heterogeneous broadcast designs for streaming applications especially on emerging multi-GPU configurations. In this work, we propose novel techniques to fully and conjointly take advantage of NVIDIA GPUDirect RDMA ( GDR), CUDA inter-process communication (IPC) and IB hardware multicast features to design high-performance heterogeneous broadcast operations for modern multi-GPU systems. We propose intra-node, topology-aware schemes to maximize the performance benefits while minimizing the utilization of valuable PCIe resources. Further, we optimize the communication pipeline by overlapping the GDR + IB hardware multicast operations with CUDA IPC operations. Compared to existing solutions, our designs show up to 3X improvement in the latency of a heterogeneous broadcast operation. Our designs also show up to 67% improvement in execution time of a streaming benchmark on a GPU-dense Cray CS-Storm system with 88 GPUs.

关键词： Graphics processing unit

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Comparison of genomes using high-performance parallel computing 15

Comparison of genomes using high-performance parallel comput...

引用

15th symposium on computer architecture and high performance computing

作者： Almeida, NF Alves, CER Caceres, EN Song, SW Univ Fed Mato Grosso do Sul Cuiaba MT Brazil

ISBN: (纸本)0769520464

Comparison of the DNA sequences and genes of two genomes can be useful to investigate the common functionalities of the corresponding organisms and get a better understanding of how the genes or groups of genes are organized and involved in several functions. In this paper we use high-performance parallel computing to compare the whole genomes of two organisms, namely Xanthomonas axonopodis pv. citri and Xanthomonas campestris pv. campestris, each with more than five million base-pairs. Our purpose is two-fold. First we intend to exploit the high-performance power of a cluster of low-cost microcomputers, propose a parallel solution to this problem, and show its feasibility with implementation and performance results. Second we do additional comparisons of the two genomes by locating and compare not only the homologous genes (expressed in terms of the 20-letter amino acids) but also compare the regions or gaps (in terms of the 4-letter DNA nucleotides) between the corresponding homologous genes. We have implemented the proposed comparison strategy to compare the two genomes Xanthomonas axonopodis pv. citri (Xac) and Xanthomonas campestris pv. campestris (Xcc). the parallel platform used is a Beowulf cluster of 64 nodes consisting of low cost microcomputers. Xac has 5,175,554 base pairs and 4,313 protein-coding genes while Xcc has 5,076,187 base pairs and 4,182 protein-coding genes. the parallel solution is based on the dynamic programming approach and presents not only less processing time, but also better quality results as compared to approaches based on Blast and EGG.

关键词： Amino acids Bioinformatics Costs DNA Genomics Microcomputers Organisms Parallel processing Proteins Sequences

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Hybrid Latency Tolerance for Robust Energy-Efficiency on 1000-Core Data Parallel Processors

Hybrid Latency Tolerance for Robust Energy-Efficiency on 100...

引用

19th IEEE International symposium on high performance computer architecture (HPCA)

作者： Crago, Neal C. Azizi, Omid Lumetta, Steven S. Patel, Sanjay J. Intel Corp Santa Clara CA 95051 USA

ISBN: (纸本)9781467355872

Currently, GPUs and data parallel processors leverage latency tolerance techniques such as multithreading and prefetching to maximize performance per Watt. However, choosing a technique that provides energy-efficiency on a wide variety of workloads is difficult, as the type of latency to tolerate, required hardware complexity, and energy consumption is directly related to application behavior. After qualitatively evaluating five commonly used latency tolerance techniques, we develop a hybrid technique utilizing multithreading and decoupled execution to maximize performance while minimizing hardware complexity and energy consumption across a wide variety of workloads. We compare our hybrid technique with the five commonly used techniques on a 1024-core data parallel processor by performing a comprehensive design space exploration, leveraging detailed performance and physical design models. By intelligently leveraging both decoupled execution and multithreading, our hybrid latency tolerance technique is able to improve energy-efficiency by 28% to 89% over any single technique on data parallel benchmarks. Compared to other combinations of latency tolerance techniques, we find that our hybrid latency tolerance technique provides the highest energy-efficiency by over 26%.

关键词： fault tolerant computing microprocessor chips multi-threading power aware computing

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Architectural Contesting

Architectural Contesting

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15th International symposium on high-performance computer architecture

作者： Najaf-abadi, Hashem H. Rotenberg, Eric N Carolina State Univ Dept Elect & Comp Engn Raleigh NC 27695 USA

ISBN: (纸本)9781424429325

this paper presents results showing that workload behavior tends to vary considerably at granularities of less than a thousand instructions. If it were possible to adjust the microarchitecture to suit the workload behavior at such rates, significant single-thread performance enhancement would be achievable. However, previous techniques are too sluggish to be able to effectively respond to such fine-grain change. An approach is proposed that exploits the multi-core trend to enable swift adjustment in the employed microarchitecture upon variation in workload behavior. A number of cores that are each custom-designed for optimum performance under a class of workloads concurrently execute code in a leader-follower arrangement. In this manner, effective execution automatically and fluidly transfers to the most suitable microarchitecture as the workload behavior varies. We refer to this approach as architectural contesting. Two-way contesting yields an average speedup of 15% (maximum speedup of 25%) over a benchmark's own customized core. the paper also explores the interplay between contesting and the number of core types available in the heterogeneous multi-core. this exposes the broader issue of constrained heterogeneous multi-core design and how it influences, and may be influenced by, contesting.

关键词： computer architecture

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