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architecture of the Entropia distributed computing system 16

Architecture of the Entropia distributed computing system

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16th International Parallel and Distributed Processing symposium, IPDPS 2002

作者： Chien, A.A. Entropia Inc. 10145 Pacific Heights Suite 800 San DiegoCA92121 United States University of California San Diego 9500 Gilman Drive San DiegoCA92093 United States

ISBN: (纸本)0769515738

Distributed computing, the exploitation of idle cycles on pervasive desktop PC systems, offers the opportunity to increase the available computing power by orders of magnitude (10-1,000 times). However, for desktop PC distributed computing to be widely accepted within enterprises, the systems much achieve high levels of robustness, security, scalability, unobtrusiveness and manageability. We describe the Entropia distributed computing system as a case study, detailing its internal architecture and philosophy in attacking these key problems. In particular, key aspects of the Entropia system include the use of (1) scalable Web/database technology for system management, (2) network tunneling and application name-spaces for logical connectivity, (3) binary sand-boxing technology for security and unobtrusiveness, and (4) an open integration model to allow applications from many sources to be incorporated. these technologies are combined to produce a robust, flexible, high-performance system which is now in use in numerous enterprises, supporting a wide range of applications. © 2002 IEEE.

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Near-Stream computing: General and Transparent Near-Cache Acceleration 28

Near-Stream Computing: General and Transparent Near-Cache Ac...

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28th Annual IEEE International symposium on high-performance computer architecture (HPCA)

作者： Wang, Zhengrong Weng, Jian Liu, Sihao Nowatzki, Tony Univ Calif Los Angeles Los Angeles CA 90095 USA

ISBN: (纸本)9781665420273

Data movement and communication have become the primary bottlenecks in large multicore systems. the near-data computing paradigm provides a solution: move computation to where the data resides on-chip. Two challenges keep near-data computing from the mainstream: lack of programmer transparency and applicability. Programmer transparency requires providing sequential memory semantics with distributed computation, which requires burdensome coordination. Broad applicability requires support for combinations of address patterns (e.g. affine, indirect, multi-operand) and computation types (loads, stores, reductions, atomics). We find that streams - coarse grain memory access patterns - are a powerful ISA abstraction for near data offloading. Tracking data access at stream-granularity heavily reduces the burden of coordination for providing sequential semantics. Decomposing the problem using streams means that arbitrary combinations of address and computation patterns can be combined for broad generality. With this insight, we develop a paradigm called near-stream computing, comprising a compiler, CPU ISA extension, and a microarchitecture that facilitate programmer transparent computation offloading to shared caches. We evaluate our system on OpenMP kernels that stress broad addressing and compute behavior, and find that 46% of dynamic instructions can be offloaded to remote banks, reducing the network traffic by 76%. Overall it achieves 2.13x speedup over a state-of-the-art near-data computing technique, with a 1.90x energy efficiency gain.

关键词： Stream-Based ISAs Programmer-Transparent Acceleration Near-Data computing

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ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based architectures for Sustainable VLSI 30

ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based Ar...

引用

30th IEEE International symposium on high-performance computer architecture (HPCA)

作者： Sudarshan, Chetan Choppali Matkar, Nikhil Vrudhula, Sarma Sapatnekar, Sachin S. Chhabria, Vidya A. Arizona State Univ Tempe AZ 85287 USA Univ Minnesota Minneapolis MN 55455 USA

ISBN: (纸本)9798350393132;9798350393149

Decades of progress in energy-efficient and low-power design have successfully reduced the operational carbon footprint in the semiconductor industry. However, this has led to increased embodied emissions, arising from design, manufacturing, and packaging. While existing research has developed tools to analyze embodied carbon for traditional monolithic systems, these tools do not apply to near-mainstream heterogeneous integration (HI) technologies. HI systems offer significant potential for sustainable computing by minimizing carbon emissions through two key strategies: "reducing" computation by "reusing" pre-designed chiplet IP blocks and adopting hierarchical approaches to system design. the reuse of chiplets across multiple designs, even spanning multiple generations of ICs, can substantially reduce carbon emissions throughout the lifespan. this paper introduces ECO-CHIP, a carbon analysis tool designed to assess the potential of HI systems toward sustainable computing by considering scaling, chiplet, and packaging yields, design complexity, and even overheads associated with advanced packaging techniques. Experimental results from ECO-CHIP demonstrate that HI can reduce embodied carbon emissions by up to 30% compared to traditional monolithic systems. ECO-CHIP is integrated with other chiplet simulators and is applied to chiplet disaggregation considering other metrics such as power, area, and cost. ECO-CHIP suggests that HI can pave the way for sustainable computing practices.

关键词： carbon footprint chiplets computer architecture embodied carbon heterogeneous integration manufacturing operational carbon silicon lifecycle sustainable computing

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Experimenting with exception propagation mechanisms in service-oriented architecture

Experimenting with exception propagation mechanisms in servi...

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4th International Workshop on Exception Handling, Co-located with the 16th ACM SIGSOFT International symposium on the Foundations of Software Engineering, WEH '08

作者： Gorbenko, Anatoliy Romanovsky, Alexander Kharchenko, Vyacheslav Mikhaylichenko, Alexey Department of Computer Systems and Networks National Aerospace University Kharkiv Ukraine School of Computing Science Newcastle University Newcastle upon Tyne United Kingdom

ISBN: (纸本)9781605582290

Exception handling is one of the popular means used for improving dependability and supporting recovery in the Service-Oriented architecture (SOA). this practical experience paper presents the results of error and fault injection into Web Services. We summarize our experiments with the SOA-specific exception handling features provided by the two development kits: the Sun Microsystems JAX-RPC and the IBM WebSphere Software Developer Kit for Web Services. the main focus of the paper is on analyzing exception propagation and performance as the major factors affecting fault tolerance (in, particular, error handling, and fault diagnosis) in Web Services. Copyright 2008 ACM.

关键词： Web services

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Improved Computation of Database Operators via Vector Processing Near-Data 35

Improved Computation of Database Operators via Vector Proces...

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35th IEEE International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Santos, Sairo Kepe, Tiago R. Alves, Marco A. Z. Fed Rural Univ Semiarid Angicos Brazil Fed Inst Parana Curitiba Parana Brazil

ISBN: (纸本)9798350305487

Data-centric applications are increasingly more common, causing issues brought on by the discrepancy between processor and memory technologies to be increasingly more apparent. Near-Data Processing (NDP) is an approach to mitigate this issue. It proposes moving some of the computation close to the memory, thus allowing for reduced data movement and aiding data-intensive workloads. Analytical database queries are very commonly used in NDP research due to their intrinsics usage of very large volumes of data. In this paper, we investigate the migration of most time-consuming database operators to VIMA, a novel 3D-stacked memory-based NDP architecture. We consider the selection, projection, and bloom join database query operators, commonly used by data analytics applications, comparing Vector-In-Memory architecture (VIMA) to a highperformance x86 baseline. We pitch VIMA against both a single-thread baseline and a modern 16-thread x86 system to evaluate its performance. Against a single-thread baseline, our experiments show that VIMA is able to speed up execution by up to 5x for selection, 2.5x for projection, and 16x for join while consuming up to 99% less energy. When considering a multi-thread baseline, VIMA matches the execution time performance even at the largest dataset sizes considered. In comparison to existing state-of-the-art NDP platforms, we find that our approach achieves superior performance for these operators.

关键词： near-data processing high performance computing database operators

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Lock-free GaussSieve for linear speedups in parallel high performance SVP calculation 26

Lock-free GaussSieve for linear speedups in parallel high pe...

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26th International symposium on computer architecture and high performance computing, SBAC-PAD 2014

作者： Mariano, Artur Timnat, Shahar Bischof, Christian Institute for Scientific Computing Technische Universität Darmstadt Darmstadt Germany Department of Computer Science Technion - Israel Institute of Technology Haifa Israel

ISBN: (纸本)9781479969043

Lattice-based cryptography became a hot-topic in the past years because it seems to be quantum immune, i.e., resistant to attacks operated with quantum computers. the security of lattice-based cryptosystems is determined by the hardness of certain lattice problems, such as the Shortest Vector Problem (SVP). thus, it is of prime importance to study how efficiently SVP-solvers can be implemented. this paper presents a parallel shared-memory implementation of the GaussSieve algorithm, a well known SVP-solver. Our implementation achieves almost linear and linear speedups with up to 64 cores, depending on the tested scenario, and delivers better sequential performance than any other disclosed GaussSieve implementation. In this paper, we show that it is possible to implement a highly scalable version of GaussSieve on multi-core CPU-chips. the key features of our implementation are a lock-free singly linked list, and hand-tuned, vectorized code. Additionally, we propose an algorithmic optimization that leads to faster convergence. © 2014 IEEE.

关键词： Quantum computers

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A Study of Power-performance Modeling using a Domain-Specific Language 28

A Study of Power-Performance Modeling using a Domain-Specifi...

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28th IEEE International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Umar, Mariam Meredith, Jeremy S. Vetter, Jeffrey S. Cameron, Kirk W. Virginia Tech Dept Comp Sci Blacksburg VA 24061 USA Oak Ridge Natl Lab Oak Ridge TN 37831 USA

ISBN: (纸本)9781509061082

Energy use is now a first-class design constraint in high-performance systems and applications. Improving our understanding of application energy consumption in diverse, heterogeneous systems will be essential to efficient operation. For example, power limits in large scale parallel and distributed systems will require optimizing performance under energy constraints. However, with increased levels of parallelism, complex memory hierarchies, hardware heterogeneity, and diverse programming models and interfaces, improving performance and energy efficiency simultaneously is exceedingly difficult. Our thesis is that estimating energy use, either a priori or as soon as possible at runtime, will be essential to future systems. Such estimates must adapt with changes in applications across hardware configurations. Existing approaches offer insight and detail, but typically are too cumbersome to enable adaptation at runtime or lack portability or accuracy. To overcome these limitations, we propose two energy estimation techniques which use the Aspen domain specific language for performance modeling: ACEE (Algorithmic and Categorical Energy Estimation), a combination of analytical and empirical modeling techniques embedded in a runtime framework that leverages Aspen, and AEEM (Aspen's Embedded Energy Modeling), a system level coarse-grained energy estimation technique that uses performance modeling from Aspen to generate energy estimations at runtime. this paper presents methodology of the models and examines their accuracy as well as their advantages and challenges in several use cases.

关键词： Domain specific language Energy estimation high-performance computing performance modeling

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Is Intel high performance Analytics Toolkit a good alternative to Apache Spark? 16

Is Intel High Performance Analytics Toolkit a good alternati...

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IEEE 16th International symposium on Network computing and Applications (NCA)

作者： de Carvalho, Rafael Aquino Goldman, Alfredo Cavalheiro, Gerson Geraldo H. Univ Sao Paulo Inst Math & Stat IME Sao Paulo Brazil Univ Fed Pelotas UFPel Grad Program Comp Sci PPGC Pelotas Brazil

ISBN: (纸本)9781538614655

this paper compares the performance and stability of two Big Data processing tools: the Apache Spark and the high performance Analytics Toolkit (HPAT). the comparison was performed using two applications: a unidimensional vector sum and the K-means clustering algorithm. the experiments were performed in distributed and shared memory environments with different numbers and configurations of virtual machines. By analyzing the results we are able to conclude that HPAT has performance improvements in relation to Apache Spark in our case studies. We independently validated the results and potential presented by the HPAT developers. We also provide an analysis of both frameworks in the presence of failures.

关键词： performance comparison big data frameworks HPAT Apache Spark

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Skinflint DRAM System: Minimizing DRAM Chip Writes for Low Power

Skinflint DRAM System: Minimizing DRAM Chip Writes for Low P...

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19th IEEE International symposium on high performance computer architecture (HPCA)

作者： Lee, Yebin Kim, Soontae Hong, Seokin Lee, Jongmin Korea Adv Inst Sci & Technol Dept Comp Sci Seoul South Korea

ISBN: (纸本)9781467355872

DRAMs are one of the main players of computer system energy consumption due to their large capacities and frequent accesses. Consequently, many schemes have been proposed to reduce DRAM power/energy consumption. Some of them propose new DRAM system and chip organizations, which are effective in reducing power consumption but intrusive. In contrast, we minimize DRAM write accesses at chip level with minimal modification of the conventional DRAM system organization and small addition to caches. When all data going to the same DRAM chips are not modified, the chips are not accessed. Consequently, chips are accessed selectively in our scheme while all chips are accessed simultaneously in the conventional DRAM system. Our chip-based selective DRAM write scheme is shown to reduce DRAM power and energy consumptions by 17% and 14%, respectively, on average. the overheads of our scheme are small in terms of performance, area, and energy consumption.

关键词： DRAM chips energy conservation low-power electronics minimisation power aware computing

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performance and Power of Cache-Based Reconfigurable computing

Performance and Power of Cache-Based Reconfigurable Computin...

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36th Annual International symposium on computer architecture

作者： Putnam, Andrew Eggers, Susan Bennett, Dave Dellinger, Eric Mason, Jett Styles, Henry Sundararajan, Prasanna Wittig, Ralph Univ Washington CSE Seattle WA 98195 USA

ISBN: (纸本)9781605585260

Many-cache is a memory architecture that efficiently supports caching in commercially available FPGAs. It facilitates FPGA programming for high-performance computing (HPC) developers by providing them with memory performance that is greater and power consumption that is less than, their current CPU platforms, but without sacrificing their familiar, C-based programming environment. Many-cache creates multiple, multi-banked caches on top of an FGPA's small, independent memories, each targeting a particular data structure or region of memory in an application and each customized for the memory operations that access it. the caches are automatically generated from C source by the CHiMPS C-to-FPGA compiler. this paper presents the analyses and optimizations of the CHiMPS compiler that construct many-cache caches. An architectural evaluation of CHiMPS-generated FPGAs demonstrates a performance advantage of 7.8x (geometric mean) over CPU-only execution of the same source code, FPGA power usage that is on average 4.1x less, and consequently performance per watt that is also greater, by a geometric mean of 21.3x.

关键词： C-to-gates C-to-hardware caches co-processor accelerator FPGA many-cache synthesis compiler

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