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SEDA4SC: A Staged Event-Driven architecture for Adaptive Service computing Runtime

SEDA4SC: A Staged Event-Driven Architecture for Adaptive Ser...

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16th IEEE symposium on computers and Communications (lSCC)

作者： Li, Zhuqing Ma, Dianfu Sun, Dou Liu, Jian Beihang Univ Inst Adv Comp Technol Beijing Peoples R China

ISBN: (纸本)9781457706783

the rapid development of web service technology brings up a number of crucial requirements for designing service computing runtime, such as supporting multiple message exchange patterns, switching among different transports, integrating various extended web service protocols and achieving robust performance under high concurrency. Based on staged event-driven architecture, we propose a novel architecture for an adaptive web-service-centric service computing runtime, named SEDA4SC. In SEDA4SC, the process of basic and extended web service protocols is divided into four primary event-driven stages to enable system independence and module isolation. Moreover, this architecture allows messages to be handled in two independent pipelines: the input pipeline and the output pipeline. Arbitrary message exchange patterns can be supported through a combination of the two pipelines. With SEDA4SC, we design and implement a service computing runtime system. the performance evaluation results show that our system exhibits robust performance under high concurrency.

关键词： Web Services Service computing SEDA Service Execution Environemnt high Concurrency

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the common case transactional behavior of multithreaded programs

The common case transactional behavior of multithreaded prog...

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12th International symposium on high-performance computer architecture

作者： Chung, JaeWoong Chafi, Hassan Minh, C. Cao McDonald, Austen Carlstrom, Brian Kozyrakis, Christos Olukotun, Kunle Stanford Univ Comp Syst Lab Stanford CA 94305 USA

ISBN: (纸本)0780393686

Transactional memory (TM) provides an easy-to-use and high-performance parallel programming model for the upcoming chip-multiprocessor systems. Several researchers have proposed alternative hardware and software TM implementations. However, the lack of transaction-based programs makes it difficult to understand the merits of each proposal and to tune future TM implementations to the common case behavior of real application. this work addresses this problem by analyzing the common case transactional behavior for 35 multithreaded programs from a wide range of application domains. We identify transactions within the source code by mapping existing primitives for parallelism and synchronization management to transaction boundaries. the analysis covers basic characteristics such as transaction length, distribution of read-set and write-set size, and the frequency of nesting and I/O operations. the measured characteristics provide key insights into the design of efficient TM systems for both nonblocking synchronization and speculative parallelization.

关键词： computer software

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Acceleration of Electromagnetic Launchers Modeling by Using Graphic Processing Units

Acceleration of Electromagnetic Launchers Modeling by Using ...

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16th IEEE International symposium on Electromagnetic Launch (EML) Technology

作者： Musolino, Antonino Rizzo, Rocco Toni, Michele Tripodi, Ernesto Univ Pisa Dept Energy & Syst Engn I-56100 Pisa Italy

ISBN: (纸本)9781467303057;9781467303064

the solution of large and complex coupled electromechanical problems requires high performance computing resources. In the last years the use of Graphic Processing Units (GPUs) has gained increasing popularity in scientific computing because of their low cost and parallel architecture. In this paper the authors report the main results of the GPU approach to the parallelization of a research code for the electromagnetic launcher analysis. Programming a GPU - based environment poses a number of critical issues that have to be carefully addressed in order to fully exploit the potentiality of the system. Data have to be properly organized in order to fit the Single Instruction Multiple Data scheme;the data transfer between the host and the device, as well as the memory management of the GPU deserve accurate programming. Two examples of application of the parallelized code have been reported to show the performance improvements that can be obtained in the numerical analysis of both rail and induction launchers.

关键词： electromagnetic launchers Graphics Processing Unit Store management Graphics processing acceleration single instruction multiple datastream high performance computing Parallel architectures Scientific computing parallelization

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Machine Learning and high-performance computing Hybrid Systems, a New Way of performance Acceleration in Engineering and Scientific Applications 16

Machine Learning and High-Performance Computing Hybrid Syste...

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16th Conference on computer Science and Intelligence Systems (FedCSIS)

作者： Gepner, Pawel Warsaw Tech Univ Ul Narbutta 86 PL-02524 Warsaw Poland

ISBN: (纸本)9788395918384

Machine learning is one of the hottest topics in IT industry as well as in academia. Some of the IT leaders and scientists believe that this is going to totally revolutionise the industry. this transformation is happening on both fronts, one is the application and software paradigm, the other is at the hardware and system level. At the same time, the high-performance computing segment is striving to achieve the level of Exascale performance. It is not debatable that to meet such level of performance and keep the cost of system and power consumption on reasonable level is not a trivial task. In this article, we try to look at a potential solution to these problems and discuss a new approach to building systems and software to meet these challenges and the growing needs of the computing power for HPC systems on the one hand, but also be ready for a new type of workload including Artificial Intelligence type of applications.

关键词： Machine Learning high-performance computing Exascale performance HPC systems IPU

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FPGA-Accelerated for Constrained high Dispersal Network 15

FPGA-Accelerated for Constrained High Dispersal Network

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15th IEEE International symposium on Parallel and Distributed Processing with Applications (ISPA) / 16th IEEE International Conference on Ubiquitous computing and Communications (IUCC)

作者： Chen, Yanliang Zhu, Minghua Xiao, Bo Meng, Dan East China Normal Univ MOE Res Ctr Software Hardware Codesign Engn & App Shanghai Peoples R China

ISBN: (纸本)9781538637906

In recent years, the Deep Neural Network (DNN) has been successfully used in image classification. Most of existing DNN often need to learn a very large set of parameters, which require a huge amount of computational resources and time to train these model parameters using the gradient descent and back-propagation procedure. To solve this issue, the PCANet has been developed for high efficient design and training of the DNN. Compared with traditional DNN, PCANet has simpler structure and better performance, which makes it attractive for hardware design. To overcome the limitations of PCANet and significantly improve its performance, we have proposed a novel model named Constrained high Dispersal Network (CHDNet) which is a variant of PCANet. In this paper, we implement the CHDNet on the Xilinx ZYNQ FPGA to ensure the instantaneity of the system with lower power than personal computer needed by taking advantage of the algorithmic parallelism and ZYNQ architecture. Our experimental results over two major datasets, the MNIST dataset for handwritten digits recognition, and the Extended Yale B dataset for face recognition, demonstrate that our model of implementation on FPGA is more than 15x faster than software implementation on PC (Intel i7-4720HQ, 2.6GHz).

关键词： Image classification Deep neural network FPGA high-level Synthesis

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Clustering-based query result authentication for encrypted databases in cloud 16

Clustering-based query result authentication for encrypted d...

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16th IEEE International Conference on high performance computing and Communications, HPCC 2014, 11th IEEE International Conference on Embedded Software and Systems, ICESS 2014 and 6th International symposium on Cyberspace Safety and Security, CSS 2014

作者： Jang, Miyoung Yoon, Min Youn, Deulnyeok Chang, Jae Woo Department of Computer Engineering Chonbuk National University Jeonju Korea Republic of

ISBN: (纸本)9781479961238

Due to advancement in cloud computing technology, the research on the outsourced database has been spotlighted. Consequently, it is becoming more important to guarantee the correctness and completeness of query result in this environment. the existing data encryption schemes do not consider data distribution when encrypting original data. And existing query result integrity methods have limitation of verification object transmission overheads. To resolve these problems, we propose a clustering-based data transformation technique and a privacy-aware query authentication index. Our clustering-based data transformation scheme is designed to select anchors based on data distribution. For the integrity of query results, our query result authentication index stores an encrypted signature for each anchor and compares the anchor signature with the verification data from the data owner. through performance evaluation, we show that our method outperforms the existing method up to 15 times in terms of query processing time and verification. © 2014 IEEE.

关键词： Authentication

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Efficient virtual channel organization and congestion avoidance in multicore NoC systems 26

Efficient virtual channel organization and congestion avoida...

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26th IEEE International symposium on computer architecture and high performance computing Workshops, SBAC-PADW 2014

作者： Oveis-Gharan, Masoud Khan, Gul N. Electrical and Computer Engineering Ryerson University 350 Victoria St TorontoONM5B 2K3 Canada

ISBN: (纸本)9781479970148

Dynamically Allocated Multi Queues (DAMQ) is an effective mechanism to achieve Virtual Channel (VC) based flow control with maximum buffer utilization in multi-core Network-on-Chip (NoC) systems. We present a new methodology to remedy some of the drawbacks of DAMQ technique. the architectural design of a DAMQ router inputport that uses minimal hardware is introduced. Our input-port design saves 70% of combinational-logic and 14.7% register hardware as compared to conventional Link-List input-port. We also present an efficient mechanism to remove traffic congestion in on-chip communication for NoC systems. It improves latency and throughput by 30% and 23% respectively as compared to conventional dynamic Virtual Channel design. © 2014 IEEE.

关键词： Traffic congestion

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Improving signature behavior by irrevocability in transactional memory systems 26

Improving signature behavior by irrevocability in transactio...

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26th International symposium on computer architecture and high performance computing, SBAC-PAD 2014

作者： Quislant, Ricardo Gutierrez, Eladio Zapata, Emilio L. Plata, Oscar Dept. of Computer Architecture University of Malaga Spain

ISBN: (纸本)9781479969043

Signatures have been proposed in Hardware Transactional Memory (HTM) to represent read and write sets of transactions and decouple transaction conflict detection from private caches. Generally, signatures are implemented as Bloom filters that allow unbounded read/write sets to be summarized in bounded hardware, at the cost of address aliasing that causes false conflict detection. Such conflicts rises exponentially as signature fills so they can lead a parallel program to perform worse than its sequential counterpart (we say that signature saturates). In this work, irrevocability is proposed to address the signature saturation problem. When a transaction is near to saturate its signature, the transaction enters an irrevocable state that prevents it from being aborted. then, such a transaction keeps running while the others are either stalled or allowed to run concurrently. Two variants of irrevocability are analyzed in this paper. Experimental evaluation on an HTM simulator shows the benefits in performance and power consumption of the proposed irrevocability mechanisms. © 2014 IEEE.

关键词： Storage allocation (computer)

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Grid-based knowledge discovery services for high throughput informatics 11

Grid-based knowledge discovery services for high throughput ...

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11th IEEE International symposium on high performance Distributed computing (HPDC-11)

作者： Ghanem, M Guo, Y Rowe, A Wendel, P Univ London Imperial Coll Sci Technol & Med London England

ISBN: (纸本)0769516866

Discovery Net is an application layer for providing grid-based knowledge discovery services. these services allow scientists to create and manage complex knowledge discovery workflows that integrate data and analysis routines provided as remote services. they also allow scientists to store, share and execute these workflows as well as publish them as new services. Discovery Net provides a higher level of abstraction of the Grid for knowledge discovery activities, thus separating the end-users from resource management issues already handled by existing and emerging standards.

关键词： Biomedical informatics computer architecture Data analysis Data mining Educational institutions Knowledge management Prototypes Remote sensing Resource management throughput

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high performance Prolog processor with multiple function units.

High performance Prolog processor with multiple function uni...

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16th Annual International symposium on computer architecture

作者： Singhal, Ashok Patt, Yale N. Univ of California Berkeley CA USA

A description is given of the Parallel Unification Machine (PLUM), a Prolog processor that exploits fine-grain parallelism using multiple function units executing in parallel. In most cases the execution of bookkeeping instruction is almost completely overlapped by unification, and the performance of the processor is limited only by the available unification parallelism. Measurements from a register transfer level simulator of PLUM are presented. the results show that PLUM with three unification units achieves an average speedup of approximately 3.4 over the Berkeley VLSI-PLM, which is usually regarded as the current highest-performance special-purpose, pipelined Prolog processor. Measurements that show the effects of multiple unification units and memory access time on performance are also presented.

关键词： computers, Digital

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