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Optical interconnects in next generation data centers;an end to end view

Optical interconnects in next generation data centers;an end...

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16th Annual IEEE symposium on high-performance Interconnects

作者： Glick, Madeleine Intel Res Pittsburgh PA 15217 USA

ISBN: (纸本)9780769533803

Bandwidth hungry applications such as real-time video processing are expected to strain data center networking infrastructure. Optics enables massive data transmission rates: in telecom settings researchers have demonstrated rates in excess of 20Tbps, however, the data center presents a different set of challenges. Low cost, low power dissipation, low latency, small physical size, and the ability to integrate with mainstream silicon electronics are more important than the ability to transmit signals over long distances, the traditional telecoms focus. We seek to directly link challenges in upcoming bandwidth hungry applications through to research exploiting high bandwidth optics. By linking the end to end research areas we intend to identify critical technology gaps and enable design of forward looking, efficient, cost effective, higher bandwidth data centers that can take optimal advantage of advances in multicore processors.

关键词： computer networks optical interconnections optical switches

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Using attribute certificates with mobile policies in electronic commerce applications 16

Using attribute certificates with mobile policies in electro...

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16th Annual computer Security Applications Conference (ACSAC 00)

作者： Doshi, V Fayad, A Jajodia, S MacLean, R Mitre Corp Mclean VA 22102 USA

ISBN: (纸本)076950860X

Many electronic commerce applications including those developed for business-to-consumer (B2C) and business-to-business (B2B) uses, require operations in computing environments that are truly distributed that is, users can request data access from multiple locations within a distributed computing system. To complicate this type of operation, however, data can be distributed and represented in multiple forms. As a result system administrators are encountering increasing difficulty in developing and managing application-specific policies for users and data. A multi-tier (N-tier) architecture can provide a powerful solution for meeting the diverse needs of the electronic commerce applications. However, a drawback to multi-tier architectures is that they require that a user's credentials and the policy-to-data mapping context must be available in the middle tier of the system architecture. this paper addresses the management of users and data by presenting a framework for combining attribute certificates with mobile policy for effective application-specific control specification and administration in a distributed computing environment. Attribute certificates provide mobility to credentials and also provide fine-grained information about security principals. Mobile policy allows application-specific policies to move along with the data to other elements of the distributed computing system. Herein we propose a high-level definition language to specify policies that are application-specific and mobile, and present an algorithm for enforcing attribute-based mobile policies.

关键词： Access control Authorization computer architecture Data security Databases Distributed computing Electronic commerce Information security Logic Mobile computing

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Using Balanced Data Placement to Address I/O Contention in Production Environments 28

Using Balanced Data Placement to Address I/O Contention in P...

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28th IEEE International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Neuwirth, Sarah Wang, Feiyi Oral, Sarp Vazhkudai, Sudharshan Rogers, James H. Bruening, Ulrich Heidelberg Univ Inst Comp Engn D-69115 Heidelberg Germany Oak Ridge Natl Lab Natl Ctr Computat Sci Oak Ridge TN USA

ISBN: (纸本)9781509061082

Designed for capacity and capability, HPC I/O systems are inherently complex and shared among multiple, concurrent jobs competing for resources. Lack of centralized coordination and control often render the end-to-end I/O paths vulnerable to load imbalance and contention. With the emergence of data-intensive HPC applications, storage systems are further contended for performance and scalability. this paper proposes to unify two key approaches to tackle the imbalanced use of I/O resources and to achieve an end-to-end I/O performance improvement in the most transparent way. First, it utilizes a topology-aware, Balanced Placement I/O method (BPIO) for mitigating resource contention. Second, it takes advantage of the platform-neutral ADIOS middle-ware, which provides a flexible I/O mechanism for scientific applications. By integrating BPIO with ADIOS, referred to as Aequilibro, we obtain an end-to-end and per job I/O performance improvement for ADIOS-enabled HPC applications without requiring any code changes. Aequilibro can be applied to almost any HPC platform and is mostly suitable for systems that lack a centralized file system resource manager. We demonstrate the effectiveness of our integration on the Titan system at the Oak Ridge National Laboratory. Our experiments with a synthetic benchmark and real-world HPC workload show that, even in a noisy production environment, Aequilibro can improve large-scale application performance significantly.

关键词： Parallel File System high performance computing Load Balancing performance Evaluation

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WiDGET: Wisconsin Decoupled Grid Execution Tiles 10

WiDGET: Wisconsin Decoupled Grid Execution Tiles

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37th International symposium on computer architecture

作者： Watanabe, Yasuko Davis, John D. Wood, David A. Univ Wisconsin Dept Comp Sci Madison WI 53706 USA

ISBN: (纸本)9781450300520

the recent paradigm shift to multi-core systems results in high system throughput within a specified power budget. However, future systems still require good single thread performance no longer the predominant design priority to mitigate sequential bottlenecks and/or to guarantee service-level agreements. Unfortunately, near saturation in voltage scaling necessitates a long-term alternative to dynamic voltage and frequency scaling. We propose an energy-proportional computing infrastructure, called WiDGET, that decouples thread context management from a sea of simple execution units (EUs). WiDGET's decoupled design provides flexibility to alter resource allocation for a particular power-performance target while turning off unallocated resources. In other words, WiDGET enables dynamic customization of different combinations of small and/or powerful cores on a single chip, consuming power in proportion to the delivered performance. Over all SPEC CPU2006 benchmarks, WiDGET provides average per-thread performance that is 26% better than a Xeon-like processor while using 8% less power. WiDGET can also scale down to a level comparable to an Atom-like processor, turning off resources to reduce average power by 58%. WiDGET achieves high power efficiency (BIPS3/W), exceeding Xeon-like and Atom-like processors by up to 2x and 21x, respectively.

关键词： Power proportional computing power efficiency hardware performance instruction steering

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high-performance GPU Transactional Memory via Eager Conflict Detection 24

High-performance GPU Transactional Memory via Eager Conflict...

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24th IEEE International symposium on high performance computer architecture (HPCA)

作者： Ren, Xiaowei Lis, Mieszko Univ British Columbia Vancouver BC Canada

ISBN: (纸本)9781538636596

GPUs transactional memory (TM) proposals to date have relied on lazy, value-based conflict detection, assuming that GPUs can amortize the latency by executing other warps. In practice, however, concurrency must be throttled to a few warps per core to avoid high abort rates, and TM performance has remained far below that of fine-grained locks. We trace this to the latency cost of validating transactions: two round trips across the crossbar required for most commits and aborts. With limited concurrency, the warp scheduler cannot amortize this, and leaves the core idle most of the time. In this paper, we show that value-based validation does not scale to high thread counts, and eager conflict detection becomes more efficient as the number of threads grows. We leverage this insight to propose GETM, a GPU TM with eager conflict detection. GETM relies on a novel distributed logical clock scheme to implement eager conflict detection without the need for cache coherence or signature broadcasts. GETM is up to 2.1 times faster than the state-of-the art prior work WarpTM (gmean 1.2 times), with 3.6 times lower silicon area overheads and 2.2 times lower power overheads.

关键词： Graphics processing units Proposals Concurrent computing Clocks Coherence Hardware Message systems

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A novel approach to on-line status authentication of public-key certificates 16

A novel approach to on-line status authentication of public-...

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16th Annual computer Security Applications Conference (ACSAC 00)

作者： Faldella, E Prandini, M Univ Bologna Dept Elect Comp Sci & Syst Bologna Italy

ISBN: (纸本)076950860X

the widespread use of public networks, such as the Internet, for the exchange of sensitive data, like legally valid documents and business transactions, poses severe security constraints. the approach relying on public-key certificates certainly represents a valuable solution from the viewpoint of data integrity and authentication the effectiveness of the approach, however, may be arguable, especially when a trivial strategy is adopted within a Public-Key Infrastructure (PKI) to deal with the problem of revoked certificates. this paper presents a novel certificate status handling scheme, based on a purposely-conceived extension of the One-Way Accumulator (OWA) cryptographic primitive. the distinguishing characteristic of the devised Owa-based Revocation Scheme (ORS) is that it exploits a single directory-signed proof to collectively authenticate the status of all the certificates handled by a Certification Authority (CA) within a PKI. A thorough investigation on the performance attainable shows that ORS exhibits the same features of the well-known On-line Certificate Status Protocol (OCSP) as regards security, scalability and certificate status-updating timeliness, at the same time drastically reducing the directory computational load that, in a high-traffic context, could be nearly unbearable when OCSP is applied.

关键词： Authentication Certification Data security high performance computing IP networks Open wireless architecture Protocols Public key Public key cryptography Scalability

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A parallel approximation hitting set algorithm for gene expression analysis 14

A parallel approximation hitting set algorithm for gene expr...

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14th symposium on computer architecture and high performance computing

作者： Ruchkys, DP Song, SW Univ Sao Paulo Inst Matemat & Estatist Dept Ciencia Computacao BR-05508090 Sao Paulo Brazil

ISBN: (纸本)0769517722

With the recent DNA-microarray technology, it is possible to measure the expression levels of thousands of genes simultaneously in the same experiment. A genetic network is a model that describes how the expression level of each gene is affected by the expression levels of other genes in the network. Given, the results of an experiment with n genes and m measures over time (m << n), we consider the problem of finding a subset of genes (k genes, where k << n) that explain the expression level of a given target gene under study. We consider the coarse-grained multicomputer (CGM) model, with p processors. In this paper we first present a sequential approximation algorithm of O(m(4) n) time and O(m(2)n) space. the main result is a new parallel approximation algorithm that determines the k genes in O(m(4) n/p) local computing time plus O(k) communication rounds, and with space requirement of O(m(2) n/p). the p factor in the parallel time and space complexities indicates a,good parallelization. We also show preliminary, promising,experimental results on a Beowulf machine. To our knowledge there are no CGM algorithms for the problem considered in this paper.

关键词： Algorithm design and analysis Approximation algorithms computer networks DNA computing Gene expression Genetics Monitoring Space technology Time measurement User-generated content

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Active-Routing: Compute on the Way for Near-Data Processing 25

Active-Routing: Compute on the Way for Near-Data Processing

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25th IEEE International symposium on high performance computer architecture (HPCA)

作者： Huang, Jiayi Puli, Ramprakash Reddy Majumder, Pritam Kim, Sungkeun Boyapati, Rahul Yum, Ki Hwan Kim, Eun Jung Texas A&M Univ College Stn TX 77843 USA NVIDIA Santa Clara CA USA Intel Corp Santa Clara CA 95051 USA

ISBN: (纸本)9781728114446

the explosion of data availability and the demand for faster data analysis have led to the emergence of applications exhibiting large memory footprint and low data reuse rate. these workloads, ranging from neural networks to graph processing, expose compute kernels that operate over myriads of data. Significant data movement requirements of these kernels impose heavy stress on modern memory subsystems and communication fabrics. To mitigate the worsening gap between high CPU computation density and deficient memory bandwidth, solutions like memory networks and near-data processing designs are being architected to improve system performance substantially. In this work, we examine the idea of mapping compute kernels to the memory network so as to leverage in-network computing in data-flow style, by means of near-data processing. We propose Active-Routing, an in-network compute architecture that enables computation on the way for near-data processing by exploiting patterns of aggregation over intermediate results of arithmetic operators. the proposed architecture leverages the massive memory-level parallelism and network concurrency to optimize the aggregation operations along a dynamically built Active-Routing Tree. Our evaluations show that Active-Routing can achieve upto 7x speedup with an average of 60% performance improvement, and reduce the energy-delay product by 80% across various benchmarks compared to the state-of-the-art processing-in-memory architecture.

关键词： memory network data-flow in-network computing near-data processing processing-in-memory

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SCOC: high-Radix Switches Made of Bufferless Clos Networks 21

SCOC: High-Radix Switches Made of Bufferless Clos Networks

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IEEE 21st International symposium on high performance computer architecture (HPA)

作者： Chrysos, Nikolaos Minkenberg, Cyriel Rudquist, Mark Basso, Claude Vanderpool, Brian IBM Res Zurich Zurich Switzerland IBM Syst & Technol Grp Rochester MN USA

ISBN: (纸本)9781479989300

In today's datacenters handling big data and for exascale computers of tomorrow, there is a pressing need for high-radix switches to economically and efficiently unify the computing and storage resources that are dispersed across multiple racks. In this paper, we present SCOC, a switch architecture suitable for economical IC implementation that can efficiently replace crossbars for high-radix switch nodes. SCOC is a multi-stage bufferless network with O(N-2/m) cost, where m is a design parameter, practically ranging between 4 - 16. We identify and resolve more than five fairness violations that are pertinent to hierarchical scheduling. Effectively, from a performance perspective, SCOC is indistinguishable from efficient flat crossbars. computer simulations show that it competes well or even outperforms flat crossbars and hierarchical switches. We report data from our ASIC implementation at 32 nm of a SCOC 136x136 switch, with shallow buffers, connecting 25 Gb/s links. In this first incarnation, SCOC is used at the spines of a server-rack, fat-tree network. Internally, it runs at 9.9 Tb/s, thus offering a speedup of 1.45x, and provides a fall-through latency of just 61 ns.

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Scalability of a distributed neural information retrieval system 11

Scalability of a distributed neural information retrieval sy...

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11th IEEE International symposium on high performance Distributed computing (HPDC-11)

作者： Weeks, M Hodge, VJ Austin, J Univ York Dept Comp Sci York YO1 5DD N Yorkshire England

ISBN: (纸本)0769516866

Summary form only given. AURA (Advanced Uncertain Reasoning architecture) is a generic family of techniques and implementations intended for high-speed approximate search and match operations on large unstructured datasets. AURA technology is fast, economical, and offers unique advantages for finding near-matches not available with other methods. AURA is based upon a high-performance binary neural network called a correlation matrix memory (CMM). Typically, several CMM elements are used in combination to solve soft or fuzzy pattern-matching problems. AURA takes large volumes of data and constructs a special type of compressed index. AURA finds exact and near-matches between indexed records and a given query, where the query itself may have omissions and errors. the degree of nearness required during matching can be varied through thresholding techniques. the PCI-based PRESENCE (Parallel Structured Neural computing Engine) card is a hardware-accelerator architecture for the core CMM computations needed in AURA-based applications. the card is designed for use in low-cost workstations and incorporates 128 MByte of low-cost DRAM for CMM storage. To investigate the scalability of the distributed AURA system, we implement a word-to-document index of an AURA-based information retrieval system, called MinerTaur, over a distributed PRESENCE CMM. © 2002 IEEE.

关键词： Aircraft Artificial neural networks computer architecture computer science Concurrent computing Coordinate measuring machines Environmental economics Information retrieval Neural networks Scalability

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