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57th IEEE International Midwest symposium on Circuits and Systems (MWSCAS)

作者： Boussadi, Mohamed Amine Tixier, thierry Landrault, Alexis Derutin, Jean-Pierre UBP IFMA Inst Pascal UMR CNRS 6602 F-63171 Aubiere France

ISBN: (纸本)9781479941322

For many image processing systems, the computing power required can not be provided by a single sequential processor, this is why many designers appeal to multiprocessor systems (parallelism). this article proposes an original flexible MP-SoC (Multi-Processors System on Chip) architecture for image processing applications. Developing processors network systems tailored to a particular application domain is critical and design-time consuming in order to achieve high-performance customized solutions. this paper introduces a 16-core MP-SoC ASIC with a software configuration. In particular, each tile of the network can configure its communication links depending on the most relevant overall parallelism scheme for a targeted application. Results are shown in term of power, area and timing performance for a 65 nm CMOS technology ASIC design. A case study (grey scale histogram analyzes) is presented to illustrate the proposed flexible MP-SoC design methodology and enables to focus on architecture exploration, instantiated scheme of parallelization and timing performance.

关键词： Application specific integrated circuits Clocks computer architecture Field programmable gate arrays Hardware Skeleton Topology

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Experience Report State-Replication-based Matching System 16

Experience Report State-Replication-based Matching System

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16th IEEE International Conference on high performance computing and Communications HPCC 2014\11th IEEE International Conference on Embedded Software and Systems ICESS 2014\6th International symposium on Cyberspace Safety and Security CSS 2014

作者： Ding, Yiqun Li, Fan Zhou, Bo Li, Wei Wang, Xinyu Wu, Tong Zhejiang Univ Coll Comp Sci Hangzhou Zhejiang Peoples R China China Foreign Exchange Trade Syst Technol R&D Dept Shanghai Peoples R China

ISBN: (纸本)9781479961238

Traditional financial trading systems were developed in database-based standalone model years ago. Given that there exist some evident drawbacks like high latency and low availability in such architecture, it is imperative to design a new model which can meet the requirements of time-sensitive financial transactions. therefore, in this paper we design and implement a state-replication-based matching system which includes the critical technical points like order sequencing and asynchronous data persistence. the performance experiment indicates that this new model can dramatically increase the throughput by three times and the latency only accounts for nearly 10% compared with the conventional architecture. high availability and robustness can be guaranteed as well.

关键词： high performance state replication virtual synchrony fault tolerance

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Exploring high-performance and Energy Proportional Interface for Phase Change Memory Systems

Exploring High-Performance and Energy Proportional Interface...

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19th IEEE International symposium on high performance computer architecture (HPCA)

作者： Li, Zhongqi Zhou, Ruijin Li, Tao Univ Florida Dept Elect & Comp Engn Intelligent Design Efficient Architectures Lab Gainesville FL 32611 USA

ISBN: (纸本)9781467355872

Phase change memory is emerging as a promising candidate for building up future energy efficient memory systems. To achieve high-performance and energy proportional design, phase change memory devices need to be reorganized so that (1) the relatively long latency of phase change memory devices should be hidden;(2) unnecessary power waste of phase change memory need to be preserved. Previous studies show that conventional memory ranks could be broken down into multiple smaller ranks for increased concurrency and lower power consumption. Nevertheless, the conventional electrical bus is incapable of supporting a large number of memory chips due to its insufficient load capacity and signal traversing speed. In this paper, we propose a phase change memory system design that leverages the state-of-art photonic links to overcome this issue. Moreover, thanks to the flexibility of photonic links, it is possible to amortize the small-rank penalty (e. g. the rank-to-rank switch overhead) by partitioning the channels either statically or dynamically. Our experimental results show that photonically interconnected phase change memory can increase the system performance (IPC) by up to 19% while saving 35% memory system power.

关键词： performance evaluation phase change memories power aware computing semiconductor storage system buses

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Bridging the Semantic Gap: Emulating Biological Neuronal Behaviors with Simple Digital Neurons

Bridging the Semantic Gap: Emulating Biological Neuronal Beh...

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19th IEEE International symposium on high performance computer architecture (HPCA)

作者： Nere, Andrew Hashmi, Atif Lipasti, Mikko Tononi, Giulio Univ Wisconsin Madison WI 53706 USA

ISBN: (纸本)9781467355872

the advent of non von Neumann computational models, specifically neuromorphic architectures, has engendered a new class of challenges for computer architects. On the one hand, each neuron-like computational element must consume minimal power and area to enable scaling up to biological scales of billions of neurons;this rules out direct support for complex and expensive features like floating point and transcendental functions. On the other hand, to fully benefit from cortical properties and operations, neuromorphic architectures must support complex non-linear neuronal behaviors. this semantic gap between the simple and power-efficient processing elements and complex neuronal behaviors has rekindled a RISC vs. CISC-like debate within the neuromorphic hardware design community. In this paper, we address the aforementioned semantic gap for a recently-described digital neuromorphic architecture that constitutes simple Linear-Leak Integrate-and-Fire (LLIF) spiking neurons as processing primitives. We show that despite the simplicity of LLIF primitives, a broad class of complex neuronal behaviors can be emulated by composing assemblies of such primitives with low area and power overheads. Furthermore, we demonstrate that for the LLIF primitives without built-in mechanisms for synaptic plasticity, two well-known neural learning rules-spike timing dependent plasticity and Hebbian learning-can be emulated via assemblies of LLIF primitives. By bridging the semantic gap for one such system we enable neuromorphic system developers, in general, to keep their hardware design simple and power-efficient and at the same time enjoy the benefits of complex neuronal behaviors essential for robust and accurate cortical simulation.

关键词： Hebbian learning biocomputing neural net architecture power aware computing reduced instruction set computing

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In-Network Traffic Regulation for Transactional Memory

In-Network Traffic Regulation for Transactional Memory

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19th IEEE International symposium on high performance computer architecture (HPCA)

作者： Zhao, Lihang Choi, Woojin Chen, Lizhong Draper, Jeffrey Univ So Calif Inst Informat Sci Los Angeles CA 90089 USA

ISBN: (纸本)9781467355872

Hardware Transactional Memory (HTM) promises to simplify parallel programming on shared-memory chip multiprocessors by providing atomic execution of code blocks. Concurrently, Networks-On-Chip (NOCs) have emerged as an efficient on-chip communication infrastructure but have been largely neglected in HTM designs. In this work, we explore the interaction between the HTM paradigm and NOCs. In the process, we find a huge source of unnecessary network traffic incurred by transactional requests that are unsuccessful. this problem is identified as false forwarding that adversely affects network performance and energy efficiency. Surprisingly, 39% (up to 79% for a specific workload) of the transactional requests have incurred false forwarding over a wide spectrum of workloads. To combat this problem, we propose TMNOC, a novel approach that exploits the co-design of HTM and NOCs to mitigate false forwarding. Transactional requests that have a high probability to fail are filtered out in-network as early as possible to save energy and improve concurrency in the memory system. Experimental results show that our design reduces total network traffic by 20% on average (up to 40%) for a set of high-contention benchmarks representative of future TM workloads, thereby reducing energy consumption by an average of 24% (up to 39%). Meanwhile, the contention in the coherence directory is reduced by 66% on average. these improvements are achieved with only 5% area overhead added to a conventional on-chip router design.

关键词： energy conservation memory architecture network routing network-on-chip parallel programming performance evaluation power aware computing shared memory systems

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high performance communications in processor networks. 89

High performance communications in processor networks.

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16th Annual International symposium on computer architecture

作者： Jesshope, C.R. Miller, P.R. Yantchev, J.T. Univ of Southampton Southampton Engl

ISBN: (纸本)9780897913195

To provide an arbitrary and fully dynamic connectivity in a network of processors, transport mechanisms must be implemented to provide the propagation of data from processor to processor, on the basis of addresses contained within a packet of data. Such data transport mechanisms must satisfy a number of requirements - deadlock and livelock freedom, good hot-spot performance, high throughput, and low latency. the authors propose a solution of these problems that allows deadlock-free, adaptive, high-throughput packet routing to be implemented on networks of processors. Examples that illustrate the technique for 2-D array and toroidal networks are given. An implementation of this scheme on arrays of transputers is described. the scheme also serves as a basis for a very low latency routing strategy named the mad postman, a detailed implementation of which is described here as well.

关键词： computers, Digital

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A Quantitative performance Analysis Model for GPU architectures

A Quantitative Performance Analysis Model for GPU Architectu...

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17th IEEE International symposium on high-performance computer architecture (HPCA)

作者： Zhang, Yao Owens, John D. Univ Calif Davis Dept Elect & Comp Engn Davis CA 95616 USA

ISBN: (纸本)9781424494354

We develop a microbenchmark-based performance model for NVIDIA GeForce 200-series GPUs. Our model identifies GPU program bottlenecks and quantitatively analyzes performance, and thus allows programmers and architects to predict the benefits of potential program optimizations and architectural improvements. In particular, we use a microbenchmark-based approach to develop a throughput model for three major components of GPU execution time: the instruction pipeline, shared memory access, and global memory access. Because our model is based on the GPU's native instruction set, we can predict performance with a 5-15% error. To demonstrate the usefulness of the model, we analyze three representative real-world and already highly-optimized programs: dense matrix multiply, tridiagonal systems solver, and sparse matrix vector multiply. the model provides us detailed quantitative analysis on performance, allowing us to understand the configuration of the fastest dense matrix multiply implementation and to optimize the tridiagonal solver and sparse matrix vector multiply by 60% and 18% respectively. Furthermore, our model applied to analysis on these codes allows us to suggest architectural improvements on hardware resource allocation, avoiding bank conflicts, block scheduling, and memory transaction granularity.

关键词： ANALYSIS MODELS GRAPPER PICK UP Graphics Processing Unit Multiplication execution time Tridiagonal Sparse matrix computer personnel

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Parallel implementation of a Lagrangian stochastic model for pollutant dispersion

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INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING 2005年第5期33卷 485-498页

作者： Roberti, DR Souto, RP Velho, HFD Degrazia, GA Anfossi, D Natl Inst Space Res INPE Lab Comp & Appl Math Sao Jose Dos Campos Brazil Univ Fed Santa Maria Dept Phys BR-97119900 Santa Maria RS Brazil CNR Italian Natl Res Council Inst Atmospher Sci & Climate I-10126 Turin Italy

Lagrangian dispersion models have shown to be effective and reliable tools for simulating the airborne pollutant dispersion. However, the main drawback for their use as regulatory models is the associated high computational costs. Consequently, in this paper a parallel version of a Lagrangian particle model-LAMBDA-is developed using the MPI message passing communication library. performance tests were executed in a distributed memory parallel machine, a multicomputer based on IA-32 architecture. Portions of the pollutant in the air emitted from its source are simulated as fictitious particles whose trajectories evolve under stochastic forcing. this yields independent evolution equations for each particle of the model that can be computed by a different processor in a parallel implementation. Speed-up results show that the parallel implementation is suitable for the used architecture.

关键词： high performance application MPI pollutant dispersion

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computing hardware for the PBX-M plasma control system

Computing hardware for the PBX-M plasma control system

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16th IEEE/NPSS symposium on Fusion Engineering - Seeking a New Energy Era (SOFE 95)

作者： Sichta, P Bell, R Hatcher, R Lagin, L Okabayashi, M PRINCETON PLASMA PHYS LAB PRINCETONNJ 08543

ISBN: (纸本)0780329708

this paper describes architectural and performance aspects of the digital computer control system used for the PBX-M Plasma Control System (PPCS). the goal of the PPCS is to achieved integrated and improved plasma control. Integration consists of replacing control functions presently served by several analog systems with a realtime digital control system. the inherently dynamic control capabilities of a high performance digital system foster exploration of advanced plasma control concepts to serve future tokamaks. the PPCS will run concurrent multiple feedback control loops, with input, processing, and output times ranging from 100 μS to 10 milliseconds. the initial control loop for plasma shaping was expected to complete in approximately 300 μS. the VME-based realtime computing hardware will be described. In addition, measurements of the system's performance such as data i/o rates and computing performance will be shown. the information presented herein covers the results of the computer system's design, configuration, and laboratory testing. Actual plasma control has not been accomplished to date.

关键词： Digital control systems

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A Case for Random Shortcut Topologies for HPC Interconnects

A Case for Random Shortcut Topologies for HPC Interconnects

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39th Annual International symposium on computer architecture (ISCA)

作者： Koibuchi, Michihiro Matsutani, Hiroki Amano, Hideharu Hsu, D. Frank Casanova, Henri Natl Inst Informat SOKENDAI Chiyoda Ku 2-1-2 Hitotsubashi Tokyo 1018430 Japan Keio Univ Yokohama Kanagawa 2238522 Japan Fordham Univ New York NY 10023 USA Univ Hawaii Manoa Honolulu HI 96822 USA

ISBN: (纸本)9781467304764

As the scales of parallel applications and platforms increase the negative impact of communication latencies on performance becomes large. Fortunately, modern high performance computing (HPC) systems can exploit low-latency topologies of high-radix switches. In this context, we propose the use of random shortcut topologies, which are generated by augmenting classical topologies with random links. Using graph analysis we find that these topologies, when compared to non-random topologies of the same degree, lead to drastically reduced diameter and average shortest path length. the best results are obtained when adding random links to a ring topology, meaning that good random shortcut topologies can easily be generated for arbitrary numbers of switches. Using flit-level discrete event simulation we find that random shortcut topologies achieve throughput comparable to and latency lower than that of existing non-random topologies such as hypercubes and tori. Finally, we discuss and quantify practical challenges for random shortcut topologies, including routing scalability and larger physical cable lengths.

关键词： Topology interconnection networks high performance computing high-radix switches diameter

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