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Evaluation Model and performance Analysis of NIC Aggregations in Containerized Private Clouds 35

Evaluation Model and Performance Analysis of NIC Aggregation...

引用

35th IEEE International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Maliszewski, Anderson M. Griebler, Dalvan Roloff, Eduardo Righi, Rodrigo da Rosa Navaux, Philippe O. A. Fed Univ Rio Grande Sul UFRGS Informat Inst Porto Alegre RS Brazil Tres de Maio Fac SETREM Lab Adv Res Cloud Comp LARCC Tres De Maio Brazil Pontifical Catholica Univ Rio Grande Sul PUCRS Sch Technol Porto Alegre RS Brazil Univ Vale Rio Sinos UNISINOS Software Innovat Lab SoftwareLab Sao Leopoldo Brazil

ISBN: (纸本)9798350381603

the availability of computational resources changed significantly due to cloud computing. In addition, we have witnessed efforts to execute high-performance computing (HPC) applications in the cloud attracted by the advantages of cost savings and scalable/elastic resource allocation. Allocating more powerful hardware and exclusivity allocating resources such as memory, storage, and CPU can improve performance in the cloud. For network interconnection, significant noise, and other inferences are generated by several simultaneous instances (multitenants) communicating using the same network. As increasing the network bandwidth may be an alternative, we designed an evaluation model, and performance analysis of NIC aggregation approaches in containerized private clouds. the experiments using NAS Parallel Benchmarks revealed that NIC aggregation approach outperforms the baseline up to similar to 98% of the executions with applications characterized by intensive network use. Also, the Balance Round-Robin aggregation mode performed better than the 802.3ad aggregation mode in most assessments.

关键词： Cloud computing Private Cloud high performance computing Network performance NIC Aggregation performance Analysis

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A monitoring sensor management system for grid environments 9

A monitoring sensor management system for grid environments

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9th IEEE International symposium on high performance Distributed computing

作者： Tierney, B Crowley, B Gunter, D Holding, M Lee, J thompson, M Univ Calif Berkeley Lawrence Berkeley Lab Comp Sci Directorate Berkeley CA 94720 USA

ISBN: (纸本)0769507840

Large distributed systems such as Computational Grids require a large amount of monitoring data be collected for a variety of tasks such as fault detection, performance analysis, performance tuning, performance prediction, and scheduling. Ensuring that all necessary monitoring is turned on and that data is being collected can be a very tedious and error-prone task. We have developed an agent-based system to automate the execution of monitoring sensors and the collection of event darn.

关键词： computer architecture computerized monitoring Distributed computing Environmental management Grid computing Jamming Java performance analysis Remote monitoring Sensor systems

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high-performance and Energy-Efficient Mobile Web Browsing on Big/Little Systems

High-Performance and Energy-Efficient Mobile Web Browsing on...

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19th IEEE International symposium on high performance computer architecture (HPCA)

作者： Zhu, Yuhao Reddi, Vijay Janapa Univ Texas Austin Dept Elect & Comp Engn Austin TX 78712 USA

ISBN: (纸本)9781467355872

Internet web browsing has reached a critical tipping point. Increasingly users rely more on mobile web browsers to access the Internet than desktop browsers. Meanwhile, webpages over the past decade have grown in complexity by more than tenfold. the fast penetration of mobile browsing and ever-richer webpages implies a growing need for high-performance mobile devices in the Mare to ensure continued end-user browsing experience. Failing to deliver webpages meeting hard cut-off constraints could directly translate to webpage abandonment or fir e-commerce websites, great revenue loss. However mobile devices' limited battery capacity limits the degree of performance that mobile web browsing can achieve. In this paper, we demonstrate the benefits of heterogeneous systems with big/little cores each with different frequencies to achieve the ideal trade-off between high performance and energy efficiency through detailed characterizations of different webpage primitives based on the hottest 5,000 webpages, we build statistical inference models that estimate webpage load time and energy consumption. We show that leveraging such predictive models lets us identify and schedule webpages us he ideal core and frequency configuration that minimizes energy consumption while still meeting stringent cut-off constraints. Real hardware and software evaluations show that our scheduling scheme achieves 83.0% energy savings, while only violating the cut-off latency for 4.1% more webpages as compared with a performance-oriented hardware strategy Against a more intelligent, OS-driven, dynamic voltage and frequency scaling scheme, it achieves 8.6% energy savings and 4.0% performance improvement simultaneously.

关键词： Internet mobile computing online front-ends performance evaluation power aware computing

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Cross-layer self-adaptive/self-aware system software for exascale systems 26

Cross-layer self-adaptive/self-aware system software for exa...

引用

26th International symposium on computer architecture and high performance computing, SBAC-PAD 2014

作者： Gioiosa, Roberto Kestor, Gokcen Kerbyson, Darren J. Hoisie, Adolfy High Performance Computing Pacific Northwest National Laboratory RichlandWA United States

ISBN: (纸本)9781479969043

the extreme level of parallelism coupled with the limited available power budget expected in the exascale era brings unprecedented challenges that demand optimization of performance, power and resiliency in unison. Scalability on such systems is of paramount importance, while power and reliability issues may change the execution environment in which a parallel application runs. To solve these challenges exascale systems will require an introspective system software that combines system and application observations across all system stack layers with online feedback and adaptation mechanisms. In this paper we propose the design of a novel self-aware, selfadaptive system software in which a kernel-level Monitor, which continuously inspects the evolution of the target system through observation of Sensors, is combined with a user-level Controller, which reacts to changes in the execution environment, explores opportunities to increase performance, save power and adapts applications to new execution scenarios. We show that the monitoring system accurately monitors the evolution of parallel applications with a runtime overhead below 1-2%. As a test case, we design and implement a runtime system that aims at optimizing application's performance and system power consumption on complex hierarchical architectures. Our results show that our adaptive system reaches 98% of performance efficiency of manually-tuned applications. © 2014 IEEE.

关键词： Budget control

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Ε psilon dataflow processor.

Ε psilon dataflow processor.

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16th Annual International symposium on computer architecture

作者： Grafe, V.G. Davidson, G.S. Hoch, J.E. Holmes, V.P. Sandia Natl Lab Albuquerque NM USA

the Εpsilon dataflow architecture is designed for high-speed uniprocessor execution as well as for parallel operation in a multiprocessor system. the Εpsilon architecture directly matches ready operands, thus eliminating the need for associative matching stores. Εpsilon also supports low-cost data fanout and critical sections. A 10-MFLOPS (millions of floating-point operations per second) CMOS/TTL processor prototype is running, and its performance has been measured with several benchmarks. the prototype has demonstrated sustained performance exceeding that of comparable control-flow processors running at high clock rates (three times faster than a 20-MHz transputer and 24 times faster than a Sun on a suite of arithmetic tests, for example).

关键词： computer systems, Digital

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Probabilistic quorum systems 97

Probabilistic quorum systems

引用

proceedings of the 1997 16th Annual ACM symposium on Principles of Distributed computing

作者： Malkhi, Dahlia Reiter, Michael Wright, Rebecca AT&T Labs Florham Park NJ United States

ISBN: (纸本)9780897919524

Services replicated using a quorum system allow operations to be performed at only a subset (quorum) of the servers, and ensure consistency among operations by requiring that any two quorums intersect. In this paper we explore the consequences of requiring this intersection property to hold only with very high probability. We show that doing so can offer dramatic improvements in the performance and availability of the service, both for services tolerant of benign server failures and services tolerant of arbitrary (Byzantine) ones. We also prove a lower bound on the performance that can be achieved with this technique.

关键词： Distributed computer systems

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Grid infrastructure monitoring system based on Nagios

Grid infrastructure monitoring system based on Nagios

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16th International symposium on high performance Distributed computing 2007, HPDC'07 and Co-Located Workshops

作者： Imamagic, Emir Dobrenic, Dobrisa University Computing Centre University of Zagreb J. Marohnica 5 10 000 Zagreb Croatia

ISBN: (纸本)1595937161

Monitoring in distributed environment such as a grid is crucial for normal operation of all subsystems. Constant gathering of information enables efficient security auditing, failure detection, maintenance, job scheduling, accounting, resource performance tuning, debugging, etc. In this paper we focus on monitoring of resources in the grid with the purpose of failure detection, notifications and automatic recovery. We introduce our system based on open source monitoring framework Nagios that achieves these functionalities. We describe grid specific features we implemented in order to achieve efficient grid monitoring system, namely sensors for various grid services, advanced sensor hierarchy and certificate-based authorization on web interface. Finally, we give overview of the implementation of our system for monitoring EGEE grid infrastructure. Copyright 2007 ACM.

关键词： Grid computing

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Evaluation of memory system for integrated Prolog processor IPP. 89

Evaluation of memory system for integrated Prolog processor ...

引用

16th Annual International symposium on computer architecture

作者： Morioka, M. Yamaguchi, S. Bandoh, T. Hitachi Ltd Hitachi Jpn

ISBN: (纸本)9780897913195

An optimal memory system for realizing a high-performance integrated Prolog processor, the IPP, is discussed. First, the memory access characteristics of Prolog are analyzed by a simulator, which simulates the execution of a Prolog program at a microinstruction level. the main findings from this analysis are that the write-access ratio of Prolog is larger than that of procedural language and that performance improvement requires the memory system to process concentrated, large write accesses effectively. the Prolog acceleration strategies for conventional cache memories are discussed. Comparison is made of cache memories (store-swap, store-through) and a stack buffer, regarding not only performance but also reliability, complexity, and effects on procedural languages. It is concluded that the advanced store-through cache is best suited to the IPP.

关键词： computer systems, Digital

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Reducing compiler-inserted instrumentation in unified-parallel-C code generation 26

Reducing compiler-inserted instrumentation in unified-parall...

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26th International symposium on computer architecture and high performance computing, SBAC-PAD 2014

作者： Alvanosl, Michail Amaral, José Nelson Tiotto, Ettore Farreras, Montse Martorell, Xavier Computer Science Barcelona Supercomputing Center Spain Department of Computing Science University of Alberta Edmonton Canada Static Compilation Technology IBM Toronto Laboratory Markham Canada Department of Computer Architecture Universitat Politècnica de Catalunya Spain

ISBN: (纸本)9781479969043

Programs written in Partitioned Global Address Space (PGAS) languages can access any location of the entire address space via standard read/write operations. However, the compiler have to create the communication mechanisms and the runtime system to use synchronization primitives to ensure the correct execution of the programs. However, PGAS programs may have fine-grained shared accesses that lead to performance degradation. One solution is to use the inspector-executor technique to determine which accesses are indeed remote and which accesses may be coalesced in larger remote access operations. A straightforward implementation of the inspector-executor in a PGAS system may result in excessive instrumentation that hinders performance. this paper introduces a shared-data localization transformation based on linear memory descriptors (LMADs) that reduces the amount of instrumentation introduced by the compiler into programs written in the UPC language and describes a prototype implementation of the proposed transformation. A performance evaluation, using up to 2048 cores of a POWER 775 supercomputer, allows for a prediction that applications with regular accesses can achieve up to 180% of the performance of handoptimized versions while applications with irregular accesses yield performance gain from 1.12X up to 6.3X speedup. © 2014 IEEE.

关键词： Linear transformations

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Revisiting HyperDimensional Learning for FPGA and Low-Power architectures 27

Revisiting HyperDimensional Learning for FPGA and Low-Power ...

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27th IEEE International symposium on high-performance computer architecture (HPCA)

作者： Imani, Mohsen Zou, Zhuowen Bosch, Samuel Rao, Sanjay Anantha Salamat, Sahand Kumar, Venkatesh Kim, Yeseong Rosing, Tajana Univ Calif Irvine Dept Comp Sci Irvine CA 92697 USA Univ Calif San Diego Dept Comp Sci & Engn San Diego CA 92093 USA MIT Dept Elect Engn & Comp Sci Cambridge MA 02139 USA Daegu Gyeongbuk Inst Sci & Technol Informat & Commun Engn Daegu South Korea

ISBN: (纸本)9781665422352

Today's applications are using machine learning algorithms to analyze the data collected from a swarm of devices on the Internet of things (IoT). However, most existing learning algorithms are overcomplex to enable real-time learning on IoT devices with limited resources and computing power. Recently, Hyperdimensional computing (HDC) is introduced as an alternative computing paradigm for enabling efficient and robust learning. HDC emulates the cognitive task by representing the values as patterns of neural activity in high-dimensional space. HDC first encodes all data points to high-dimensional vectors. It then efficiently performs the learning task using a well-defined set of operations. Existing HDC solutions have two main issues that hinder their deployments on low-power embedded devices: (i) the encoding module is costly, dominating 80% of the entire training performance, (ii) the HDC model size and the computation cost grow significantly with the number of classes in online inference. In this paper, we proposed a novel architecture, LookHD, which enables real-time HDC learning on low-power edge devices. LookHD exploits computation reuse to memorize the encoding module and simplify its computation with single memory access. LookHD also address the inference scalability by exploiting HDC governing mathematics that compresses the HDC trained model into a single hypervector. We present how the proposed architecture can be implemented on the existing low power architectures: ARM processor and FPGA design. We evaluate the efficiency of the proposed approach on a wide range of practical classification problems such as activity recognition, face recognition, and speech recognition. Our evaluations show that LookHD can achieve, on average, 28.3 x faster and 97.4 x more energy-efficient training as compared to the state-of-the-art HDC implemented on the FPGA. Similarly, in the inference, LookHD is 2.2 x faster, 4.1 x more energy-efficient, and has 6.3 x smaller model siz

关键词： HyprDimensional computing Brain-inspired computing Machine learning Real-time learning FPGA

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