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Experience of Parallelizing cryo-EM 3D Reconstruction on a CPU-GPU Heterogeneous System 11

Experience of Parallelizing cryo-EM 3D Reconstruction on a C...

引用

20th International symposium on high performance Distributed computing

作者： Li, Linchuan Li, Xingjian Tan, Guangming Chen, Mingyu Zhang, Peiheng Chinese Acad Sci Inst Comp Technol Key Lab Comp Syst & Architecture Beijing Peoples R China

ISBN: (纸本)9781450305525

Heterogeneous architecture is becoming an important way to build a massive parallel computer system, i.e. the CPU-GPU heterogeneous systems ranked in Top500 list. However, it is a challenge to efficiently utilize massive parallelism of both applications and architectures on such heterogeneous systems. In this paper we present a practice on how to exploit and orchestrate parallelism at algorithm level to take advantage of underlying parallelism at architecture level. A potential Petaflops application cryo-EM 3D reconstruction is selected as an example. We exploit all possible parallelism in cryo-EM 3D reconstruction, and leverage a self-adaptive dynamic scheduling algorithm to create a proper parallelism mapping between the application and architecture. the parallelized programs are evaluated on a subsystem of Dawning Nebulae supercomputer, whose node is composed of two Intel six-core Xeon CPUs and one Nvidia Fermi CPU. the experiment confirms that hierarchical parallelism is an efficient pattern of parallel programming to utilize capabilities of both CPU and CPU in a heterogeneous system. the CUDA kernels run more than 3 times faster than the OpenMP parallelized ones using 12 cores (threads). Based on the CPU-only version, the hybrid CPU-CPU program further improves the whole application's performance by 30% on the average.

关键词： task parallelism data parallelism high performance computing CUDA cryo-EM

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Optics for Enabling Future HPC Systems

Optics for Enabling Future HPC Systems

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17th symposium on high-performance Interconnects

作者： Shainer, Gilad Gutkind, Eyal Lee, Bill Kagan, Michael Kliteynik, Yevgeny Mellanox Technologies United States

ISBN: (纸本)9781424452026

Increasing demand for computing power in scientific and engineering applications has spurred deployment of high-performance computing clusters. According to the TOP500 list, an industry respected report of the most powerful computer systems, the high-performance computing market entered the Teraflop era in 2005 (the entry point on the list became greater than1 Teraflop) and anticipates entering the Petaflop era in 2015. Future HPC systems that are capable of running large-scale parallel applications will span thousands to tens-of-thousands of nodes;all connected together via high-speed connectivity solutions to form a Peta to multi-Petaflop clusters. there are several architectural approaches to interconnect nodes together to construct an HPC system, such as the use of a Fat-Tree (CBB) or a 3-D Torus. the overall number of communication links grows with the size of the system. the physical medium for those Links have become a growing concern for large-scale platforms, as they tend to impact the system architecture, the system reliability and its cost. In the paper we review the requirements for HPC systems cabling, and in particular Optical cables. Optical cables capabilities will become the main limitation for building systems at any scale according to the CPU, memory and interconnect roadmaps in the next few years.

关键词： high performance computing InfiniBand Networking architecture Communications patterns Optical Connectivity

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Multi-level shared caching techniques for scalability in VMP-MC. 89

Multi-level shared caching techniques for scalability in VMP...

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16th Annual International symposium on computer architecture

作者： Cheriton, David R. Goosen, Hendrik A. Boyle, Patrick D. Stanford Univ Stanford CA USA

ISBN: (纸本)9780897913195

A description is given of the VMP-MC design, a distributed parallel multicomputer based on the VMP multiprocessor design that is intended to provide a set of building blocks for configuring machines from one to several thousand processors. VMP-MC uses a memory hierarchy based on shared caches, ranging from on-chip caches to board-level caches connected by buses to a high-speed fiber-optic ring. In addition to describing the building block components of this architecture, the authors identify the key performance issues associated with the design and provide performance evaluation of these issues using trace-driven simulation and measurements from the VMP.

关键词： computer systems, Digital

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A high performance, Race Eliminated, Two Phase Nonoverlapping Clocked All-N-Logic for both Strong and Subthreshold Designs

A High Performance, Race Eliminated, Two Phase Nonoverlappin...

引用

16th CSI International symposium on computer architectures and Digital Systems (CADS)

作者： Kargar, M. Ghaznavi-Ghoushchi, M. B. Shahed Univ Sch Engn Tehran Iran

ISBN: (纸本)9781467314824;9781467314817

In this paper, a new structure of ANL logic, named TPANL, is presented to achieve higher performance, lower power consumption and eliminating glitches. Different ANL logics suffer from output glitches due to race problem. Our proposed TPANL logic by two phase nonoverlapping clocks eliminates output glitches and reduces glitch power. TPANL logic speedup is mainly due to reduced capacitance at each evaluation node of a dynamic circuit. this logic works in both operational region of strong inversion and subthreshold region, with 1 OGHz to 12.5 MHz respectively. In spite of NonInv./Inv. pipeline in ANL logics, TPANL is based on NonInv./NonInv. pipeline and therefore it solves the voltage drops on NMOS Inv. stages in subthreshold regions. the simulation results of 4-bit CLA adder show 27% and 72.9% power consumption reduction, also, 60% and 50% performance improvement, in strong inversion region rather than ANL and DPANL respectively. the 4-bit CLA adder with TPANL logic in the subthreshold region has about 92nW power consumption.

关键词： Dynamic circuits All-N-Logic (ANL) low power nonoverlapping clocks

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Using grid computing based components in on demand environmental data delivery

Using grid computing based components in on demand environme...

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16th International symposium on high performance Distributed computing 2007, HPDC'07 and Co-Located Workshops

作者： Montella, Raffaele Giunta, Giulio Riccio, Angelo Dpt. of Applied Science University of Naples Parthenope Via De Gasperi 5 80131 - Napoli Italy

ISBN: (纸本)1595937188

the grid computing technology is evolving from the emergence to the stable and production status. In the computational science field the grid computing approach for storage and computing element resource sharing is a common way thanks to middleware as the Globus Toolkit and grid environments as the Condor project. In many domain applications, as environmental science, bioinformatics and interactive multimedia delivery, the shared resource is composed by tagged data and contents instead of hardware components. We provide a grid aware component leveraging on our Resource Broker Service implementing a wrap over the world-wide spread OpenDAP scientific data access protocol, ensuring effective and efficient grid based content distribution, and contributing to the "grand challenge" concerning the development of grid-aware software infrastructure for data intensive environmental applications.

关键词： Grid computing

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architecture requirements for commercializing Grid resources

Architecture requirements for commercializing Grid resources

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11th IEEE International symposium on high performance Distributed computing (HPDC-11)

作者： Kenyon, C Cheliotis, G IBM Corp Zurich Res Lab CH-8803 Ruschlikon Switzerland

ISBN: (纸本)0769516866

Contemporary computing systems, especially large-scale systems such as Grids promise ultra-fast ubiquitous utility computing, always available at the flip of a switch. A major unresolved issue is the organization and efficient usage of such infrastructure in a commercial context where several entities compete for shared resources. this has long been resolved for conventional utility resources such as gas and electricity through commoditization, a variety of market designs, customization, and decision support for the resulting portfolios of assets and commitments. this paper reviews the state of Grid commercialization and compares it to the commercialization of conventional resources. We draw specific lessons for commercialized Grids and detail them as architecture requirements at each level of the architecture stack. We provide an example to illustrate the benefits of commercialized resources in terms of the financial clarity it brings to decisions for different user groups, namely application users and IT managers.

关键词： computer architecture

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Software architecture-based adaptation for grid computing 11

Software architecture-based adaptation for grid computing

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11th IEEE International symposium on high performance Distributed computing (HPDC-11)

作者： Cheng, SW Garlan, D Schmerl, B Steenkiste, P Hu, NN Carnegie Mellon Univ Sch Comp Sci Pittsburgh PA 15213 USA

ISBN: (纸本)0769516866

Grid applications must increasingly self-adapt dynamically to changing environments. In most cases, adaptation has been implemented in an ad hoc fashion, on a per-application basis. this paper describes work which generalizes adaptation so that it can be used across applications by providing an adaptation framework. this framework uses a software architectural model of the system to analyze whether the application requires adaptation, and allows repairs to be written in the context of the architectural model and propagated to the running system. In this paper, we exemplify our framework by applying it to the domain of load-balancing a client-server system. We report on an experiment conducted using our framework, which illustrates that this approach maintains architectural requirements.

关键词： Application software Availability computer networks computer science Grid computing Humans Mechanical factors Monitoring Network servers Runtime

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high performance computing in science and engineering

High performance computing in science and engineering

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17th International symposium on computer architecture and high performance computing, SBAC-PAD 2005

作者： Haas, Peter W. Resch, Michael M. University of Stuttgart HLRS

ISBN: (纸本)076952446X

high performance computing has gradually shifted from the realm of research into development and partially even into the production cycles of industry, high performance computers therefore have to be integrated into production environments that demand the simultaneous solution of multidisciplinary physics problems. Supercomputer centers can learn from these new challenges imposed by industry. the concepts of work flow and production cycle open up a new horizon for integrating systems and software into what is called a distributed 'Teraflop-Workbench' approach. Terascale storage and communication infrastructures eventually will be needed to support such an environment. © 2005 IEEE.

关键词： Computation theory

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high-level dataflow programming for reconfigurable computing 26

High-level dataflow programming for reconfigurable computing

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26th IEEE International symposium on computer architecture and high performance computing Workshops, SBAC-PADW 2014

作者： Sérot, J. Berry, F. Institut Pascal Université Blaise Pascal / CNRS Clermont-Ferrand France

ISBN: (纸本)9781479970148

In many application domains, FPGAS are now promoted as a way of getting round the restrictions of specific CPU designs on system scalability. However, in the current state-of-the art, programming FPGAS remains essentially a hardware-oriented activity, relying on dedicated hardware description languages such as VHDL or Verilog. Using these languages requires expertise in digital design and in practice this limits the applicability of FPGA-based solutions. this is particulary true for stream-processing applications, in which some processing must be carried out "on the fly" on digital data streams. In this context, the dataflow programming model offers a very effective way to reduce the gap between high-level formulations and low-level implementations. To support this claim, the authors have recently introduced CAPH, a domain specific language, offering a fully-automated compilation path from high-level dataflow descriptions to FPGA configuration for stream-processing applications. this paper is a introduction to the CAPH language, giving its motivations and main design principles and exposing the basic features of its syntax, semantics and compilation. It also points to experimental results showing that, at least for stream-processing applications, the dataflow model of computation, used jointly as a programming model and an execution model, can offer a very effective way to conciliate abstraction and efficiency when programming FPGAS. © 2014 IEEE.

关键词： computer hardware description languages

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SnackNoC: Processing in the Communication Layer 26

SnackNoC: Processing in the Communication Layer

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26th IEEE International symposium on high performance computer architecture (HPCA)

作者： Sangaiah, Karthik Lui, Michael Kuttappa, Ragh Taskin, Baris Hempstead, Mark Drexel Univ Dept Elect & Comp Engn Philadelphia PA 19104 USA Tufts Univ Dept Elect & Comp Engn Medford MA 02155 USA

ISBN: (纸本)9781728161495

In this work, we propose and evaluate a Network-on-Chip (NoC) augmented with light-weight processing elements to provide a lean dataflow-style system. We show that contemporary NoC routers can frequently experience long periods of idle time, with less than 10% link utilization in HPC applications. By repurposing the temporal and spatial slack of the NoC, the proposed platform, SnackNoC, is able to compute linear algebra kernels efficiently within the communication layer with minimal additional resource costs. SnackNoC 'Snack' application kernels are programmed with a producer-consumer data model that uses the NoC slack to store and transmit intermediate data between processing elements. SnackNoC is demonstrated in a multi-program environment that continually executes linear algebra kernels on the NoC simultaneously with chip multiprocessor (CMP) applications on the processor cores. Linear algebra kernels are computed up to 6.15x faster on SnackNoC compared to an Intel Haswell EPx86 processing core. the cost of executing 'snack' kernels in parallel to the CMP applications is a minimal runtime impact of 0.01% to 0.83% due to higher link utilization, and an uncore area overhead of 1.1%.

关键词： computer architecture In network processing Network on chip Opportunistic computing

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