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CAT: A high performance, distributed component architecture toolkit for the Grid

CAT: A high performance, distributed component architecture ...

引用

proceedings of the 1999 8th IEEE International symposium on high performance Distributed computing - HPDC-8

作者： Villacis, Juan Govindaraju, Madhusudhan Stern, David Whitaker, Andrew Breg, Fabian Deuskar, Prafulla Temko, Benjamin Gannon, Dennis Bramley, Randall Indiana Univ Bloomington United States

Taking advantage of the Grid for high-performance scientific computing requires a software framework layered above the Grid that supports a new style of programming, component-based programming. the component architecture toolkit (CAT) facilitates such programming by providing a conceptually simple `port-based' component model together with a suite of developer tools for incorporating existing scientific codes into the framework, as well as a set of end user tools for locating, composing, building and running distributed component application over the Grid.

关键词： Distributed computer systems

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In-Network Traffic Regulation for Transactional Memory

In-Network Traffic Regulation for Transactional Memory

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19th IEEE International symposium on high performance computer architecture (HPCA)

作者： Zhao, Lihang Choi, Woojin Chen, Lizhong Draper, Jeffrey Univ So Calif Inst Informat Sci Los Angeles CA 90089 USA

ISBN: (纸本)9781467355872

Hardware Transactional Memory (HTM) promises to simplify parallel programming on shared-memory chip multiprocessors by providing atomic execution of code blocks. Concurrently, Networks-On-Chip (NOCs) have emerged as an efficient on-chip communication infrastructure but have been largely neglected in HTM designs. In this work, we explore the interaction between the HTM paradigm and NOCs. In the process, we find a huge source of unnecessary network traffic incurred by transactional requests that are unsuccessful. this problem is identified as false forwarding that adversely affects network performance and energy efficiency. Surprisingly, 39% (up to 79% for a specific workload) of the transactional requests have incurred false forwarding over a wide spectrum of workloads. To combat this problem, we propose TMNOC, a novel approach that exploits the co-design of HTM and NOCs to mitigate false forwarding. Transactional requests that have a high probability to fail are filtered out in-network as early as possible to save energy and improve concurrency in the memory system. Experimental results show that our design reduces total network traffic by 20% on average (up to 40%) for a set of high-contention benchmarks representative of future TM workloads, thereby reducing energy consumption by an average of 24% (up to 39%). Meanwhile, the contention in the coherence directory is reduced by 66% on average. these improvements are achieved with only 5% area overhead added to a conventional on-chip router design.

关键词： energy conservation memory architecture network routing network-on-chip parallel programming performance evaluation power aware computing shared memory systems

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SmarCo: An Efficient Many-Core Processor for high-throughput Applications in Datacenters 24

SmarCo: An Efficient Many-Core Processor for High-Throughput...

引用

24th IEEE International symposium on high performance computer architecture (HPCA)

作者： Fan, Dongrui Li, Wenming Ye, Xiaochun Wang, Da Zhang, Hao Tang, Zhimin Sun, Ninghui Chinese Acad Sci ICT SKL Comp Architecture Beijing Peoples R China Univ Chinese Acad Sci Sch Comp & Control Engn Beijing Peoples R China SmarCo Co Ltd Beijing Peoples R China

ISBN: (纸本)9781538636596

Fast-growing high-throughput applications, such as web services, are characterized by high-concurrency processing, hard real-time response, and high-bandwidth memory access. the newly-born applications bring severe challenges to processors in datacenters, both in concurrent processing performance and energy efficiency. To offer a satisfactory quality of services, it is of critical importance to meet these newly emerging demands of high-throughput applications in the future datacenters in a more efficient way. In this paper, we propose a novel architecture, called SmarCo, which allows high-throughput applications to be processed more efficiently in datacenters. Based on the dominant characteristics of high-throughput applications, we implement large-scale many-core architecture with in-pair threads to support high-concurrency processing;we also introduce a hierarchical ring topology and laxity-aware task scheduler to guarantee hard real-time response;furthermore, we propose high-throughput datapath to improve memory access efficiency. We verify the efficiency of SmarCo by using simulators, large-scale FPGA and prototype with TSMC 40-nm technology node. the experimental results show that, compared to Intel Xeon E7-8890V4, SmarCo achieves 10.11X performance improvement and 6.95X energy-efficiency improvement with higher throughput and a better guarantee of real-time response.

关键词： Instruction sets Task analysis Indexes Real-time systems Memory management throughput

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Bridging the Semantic Gap: Emulating Biological Neuronal Behaviors with Simple Digital Neurons

Bridging the Semantic Gap: Emulating Biological Neuronal Beh...

引用

19th IEEE International symposium on high performance computer architecture (HPCA)

作者： Nere, Andrew Hashmi, Atif Lipasti, Mikko Tononi, Giulio Univ Wisconsin Madison WI 53706 USA

ISBN: (纸本)9781467355872

the advent of non von Neumann computational models, specifically neuromorphic architectures, has engendered a new class of challenges for computer architects. On the one hand, each neuron-like computational element must consume minimal power and area to enable scaling up to biological scales of billions of neurons;this rules out direct support for complex and expensive features like floating point and transcendental functions. On the other hand, to fully benefit from cortical properties and operations, neuromorphic architectures must support complex non-linear neuronal behaviors. this semantic gap between the simple and power-efficient processing elements and complex neuronal behaviors has rekindled a RISC vs. CISC-like debate within the neuromorphic hardware design community. In this paper, we address the aforementioned semantic gap for a recently-described digital neuromorphic architecture that constitutes simple Linear-Leak Integrate-and-Fire (LLIF) spiking neurons as processing primitives. We show that despite the simplicity of LLIF primitives, a broad class of complex neuronal behaviors can be emulated by composing assemblies of such primitives with low area and power overheads. Furthermore, we demonstrate that for the LLIF primitives without built-in mechanisms for synaptic plasticity, two well-known neural learning rules-spike timing dependent plasticity and Hebbian learning-can be emulated via assemblies of LLIF primitives. By bridging the semantic gap for one such system we enable neuromorphic system developers, in general, to keep their hardware design simple and power-efficient and at the same time enjoy the benefits of complex neuronal behaviors essential for robust and accurate cortical simulation.

关键词： Hebbian learning biocomputing neural net architecture power aware computing reduced instruction set computing

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AMRZone: A Runtime AMR Data Sharing Framework For Scientific Applications 16

AMRZone: A Runtime AMR Data Sharing Framework For Scientific...

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16th IEEE/ACM International symposium on Cluster, Cloud and Grid computing (CCGrid)

作者： Zhang, Wenzhao Tang, Houjun Harenberg, Steve Byna, Surendra Zou, Xiaocheng Devendran, Dharshi Martin, Daniel F. Wu, Kesheng Dong, Bin Klasky, Scott Samatova, Nagiza F. North Carolina State Univ Raleigh NC 27695 USA Lawrence Berkeley Natl Lab Berkeley CA 94720 USA Oak Ridge Natl Lab Oak Ridge TN 37831 USA

ISBN: (纸本)9781509024537

Frameworks that facilitate runtime data sharing across multiple applications are of great importance for scientific data analytics. Although existing frameworks work well over uniform mesh data, they can not effectively handle adaptive mesh refinement (AMR) data. Among the challenges to construct an AMR-capable framework include: (1) designing an architecture that facilitates online AMR data management;(2) achieving a load-balanced AMR data distribution for the data staging space at runtime;and (3) building an effective online index to support the unique spatial data retrieval requirements for AMR data. Towards addressing these challenges to support runtime AMR data sharing across scientific applications, we present the AMRZone framework. Experiments over real-world AMR datasets demonstrate AMRZone's effectiveness at achieving a balanced workload distribution, reading/writing large-scale datasets with thousands of parallel processes, and satisfying queries with spatial constraints. Moreover, AMRZone's performance and scalability are even comparable with existing state-of-the-art work when tested over uniform mesh data with up to 16384 cores;in the best case, our framework achieves a 46% performance improvement.

关键词： Servers Runtime Metadata Distributed databases computer architecture Spatial indexes Runtime Spacial indices distributed databases computer architecture Metadata Servers Frameworks Amphiregulin Antimicrobial Drug Resistance automatic meter reading Data Sharing

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Energy efficient seismic wave propagation simulation on a low-power manycore processor 26

Energy efficient seismic wave propagation simulation on a lo...

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26th International symposium on computer architecture and high performance computing, SBAC-PAD 2014

作者： Castro, Marcio Dupros, Fabrice Francesquini, Emilio Mehautk, Jean-Francois Navaux, Philippe O.A. Informatics Institute Federal University of Rio Grande Do sul Brazil Department of Informatics and Statistics Federal University of Santa Catarina Brazil BRGM Orléans France Institute of Computing University of Campinas Brazil Institute of Mathematics and Statistics University of São Paulo Brazil CEA/DRT University of Grenoble France

ISBN: (纸本)9781479969043

Large-scale simulation of seismic wave propagation is an active research topic. Its high demand for processing power makes it a good match for high performance computing (HPC). Although we have observed a steady increase on the processing capabilities of HPC platforms, their energy efficiency is still lacking behind. In this paper, we analyze the use of a low-power manycore processor, the MPPA-256, for seismic wave propagation simulations. First we look at its peculiar characteristics such as limited amount of on-chip memory and describe the intricate solution we brought forth to deal with this processor's idiosyncrasies. Next, we compare the performance and energy efficiency of seismic wave propagation on MPPA-256 to other commonplace platforms such as general-purpose processors and a GPU. Finally, we wrap up with the conclusion that, even if MPPA-256 presents an increased software development complexity, it can indeed be used as an energy efficient alternative to current HPC platforms, resulting in up to 71% and 81% less energy than a GPU and a general-purpose processor, respectively. © 2014 IEEE.

关键词： Graphics processing unit

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A Quantitative performance Analysis Model for GPU architectures

A Quantitative Performance Analysis Model for GPU Architectu...

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17th IEEE International symposium on high-performance computer architecture (HPCA)

作者： Zhang, Yao Owens, John D. Univ Calif Davis Dept Elect & Comp Engn Davis CA 95616 USA

ISBN: (纸本)9781424494354

We develop a microbenchmark-based performance model for NVIDIA GeForce 200-series GPUs. Our model identifies GPU program bottlenecks and quantitatively analyzes performance, and thus allows programmers and architects to predict the benefits of potential program optimizations and architectural improvements. In particular, we use a microbenchmark-based approach to develop a throughput model for three major components of GPU execution time: the instruction pipeline, shared memory access, and global memory access. Because our model is based on the GPU's native instruction set, we can predict performance with a 5-15% error. To demonstrate the usefulness of the model, we analyze three representative real-world and already highly-optimized programs: dense matrix multiply, tridiagonal systems solver, and sparse matrix vector multiply. the model provides us detailed quantitative analysis on performance, allowing us to understand the configuration of the fastest dense matrix multiply implementation and to optimize the tridiagonal solver and sparse matrix vector multiply by 60% and 18% respectively. Furthermore, our model applied to analysis on these codes allows us to suggest architectural improvements on hardware resource allocation, avoiding bank conflicts, block scheduling, and memory transaction granularity.

关键词： ANALYSIS MODELS GRAPPER PICK UP Graphics Processing Unit Multiplication execution time Tridiagonal Sparse matrix computer personnel

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performance Analysis with high-Level Languages for high-performance Reconfigurable computing

Performance Analysis with High-Level Languages for High-Perf...

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16th Annual IEEE symposium on Field-Programmable Custom computing Machines

作者： Curreri, John Koehler, Seth Holland, Brian George, Alan D. Univ Florida NSF Ctr High Performance Reconfigurable Comp ECE Dept Gainesville FL 32611 USA

ISBN: (纸本)9780769533070

high-Level Languages (HLLS) for FPGAs (Field-Programmable Gate Arrays) facilitate the use of reconfigurable computing resources for application developers by using familiar, higher-level syntax, semantics, and abstractions, typically enabling faster development times than with traditional Hardware Description Languages (HDLs). However, this abstraction is typically accompanied by some loss of performance as well as reduced transparency of application behavior, making it difficult to understand and improve application performance. While runtime tools for performance analysis are often featured in development with traditional HLLS for serial and parallel programming, HLL-based applications for FPGAs have an equal or greater need yet lack these tool. this presents a novel and portable framework for runtime performance analysis of HLL applications for FPGAs, including a prototype tool for performance analysis with Impulse C, a commerical HLL for FPGAs. As a case study, this tool is used to locate performance bottlenecks in a molecular dynamics applications.

关键词： performance analysis profile trace reconfigurable computing FPGA high-level language application mapper Impulse C Carte

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high-performance extendable instruction set computing 6

High-performance extendable instruction set computing

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6th Australasian computer Systems architecture Conference (ACSAC 2001)

作者： Lee, H Beckett, P Appelbe, B Asia Design Corporation Australia RMIT University Australia

ISBN: (纸本)0769509541

In this paper, a new architecture called the extendable instruction set computer (EISC) is introduced that addresses the issues of memory size and performance in embedded microprocessor systems. the architecture exhibits an efficient fixed length 16-bit instruction set with short length offset and immediate operands. the offset and immediate operands can be extended to 32 bits via the operation of an extension flag. the code density of the EISC instruction set and its memory transfer performance is shown to be significantly higher than current architectures making it a suitable candidate for the next generation of embedded computer systems. the compact EISC instruction set introduces data dependencies that seemingly limit deep pipeline and superscalar implementations. this paper suggests a mechanism by which these dependencies might be removed in hardware.

关键词： Bandwidth Central Processing Unit Circuits computer aided instruction computer architecture Embedded computing Microprocessors Personal digital assistants Pipelines Random access memory

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Can dataflow subsume von Neumann computing?.

Can dataflow subsume von Neumann computing?.

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16th Annual International symposium on computer architecture

作者： Rishiyur, S.Nikhil Arvind MIT Cambridge MA USA

the question of what a von Neumann processor can borrow from dataflow to make it more suitable for a multiprocessor is explored. Starting with a simple, RISC (reduced-instruction-self-computer)-like instruction set, the author shows how to change the underlying processor organization to make it multithreaded. then he extends it with three instructions that give it a fine-grained, dataflow capability, and he calls the result P-RISC, for parallel RISC. Finally, the author discusses memory support for such multiprocessors. He compares his approach to existing MIMD (multiple-instruction multiple-data-stream) machines and to other dataflow machines.

关键词： computer architecture

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