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Enabling Fine-Grain Restricted Coset Coding through Word-Level Compression for PCM 24

Enabling Fine-Grain Restricted Coset Coding Through Word-Lev...

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24th IEEE International symposium on high performance computer architecture (HPCA)

作者： Seyedzadeh, Seyed Mohammad Jones, Alex K. Melhem, Rami Univ Pittsburgh Comp Sci Dept Pittsburgh PA 15260 USA Univ Pittsburgh Elect & Comp Engn Dept Pittsburgh PA 15260 USA

ISBN: (纸本)9781538636596

Phase change memory (PCM) has recently emerged as a promising technology to meet the fast growing demand for large capacity memory in computer systems, replacing DRAM that is impeded by physical limitations. Multi-level cell (MLC) PCM offers high density with low per-byte fabrication cost. However, despite many advantages, such as scalability and low leakage, the energy for programming intermediate states is considerably larger than programing single-level cell PCM. In this paper, we study encoding techniques to reduce write energy for MLC PCM when the encoding granularity is lowered below the typical cache line size. We observe that encoding data blocks at small granularity to reduce write energy actually increases the write energy because of the auxiliary encoding bits. We mitigate this adverse effect by 1) designing suitable codeword mappings that use fewer auxiliary bits and 2) proposing a new Word-Level Compression (WLC) which compresses more than 91% of the memory lines and provides enough room to store the auxiliary data using a novel restricted coset encoding applied at small data block granularities. Experimental results show that the proposed encoding at 16-bit data granularity reduces the write energy by 39%, on average, versus the leading encoding approach for write energy reduction. Furthermore, it improves endurance by 20% and is more reliable than the leading approach. Hardware synthesis evaluation shows that the proposed encoding can be implemented on-chip with only a nominal area overhead.

关键词： Encoding Phase change materials computer architecture Microprocessors Programming Resistance Energy states

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Charm: A Language for Closed-form high-level architecture Modeling 18

Charm: A Language for Closed-form High-level Architecture Mo...

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45th ACM/IEEE Annual International symposium on computer architecture (ISCA)

作者： Cui, Weilong Ding, Yongshan Dangwal, Deeksha Holmes, Adam McMahan, Joseph Javadi-Abhari, Ali Tzimpragos, Georgios Chong, Frederic T. Sherwood, Timothy Univ Calif Santa Barbara Santa Barbara CA 93106 USA Univ Chicago Chicago IL 60637 USA IBM Res New York NY USA

ISBN: (纸本)9781538659847

As computer architecture continues to expand beyond software-agnostic microarchitecture to data center organization, reconfigurable logic, heterogeneous systems, application-specific logic, and even radically different technologies such as quantum computing, detailed cycle-level simulation is no longer presupposed. Exploring designs under such complex interacting relationships (e.g., performance, energy, thermal, cost, voltage, frequency, cooling energy, leakage, etc.) calls for a more integrative but higher-level approach. We propose Charm, a domain specific language supporting Closed-form high-level architecture Modeling. Charm enables mathematical representations of mutually dependent architectural relationships to be specified, composed, checked, evaluated and reused. the language is interpreted through a combination of symbolic evaluation (e.g., restructuring) and compiler techniques (e.g., memoization and invariant hoisting), generating executable evaluation functions and optimized analysis procedures. Further supporting reuse, a type system constrains architectural quantities and ensures models operate only in a validated domain. through two case studies, we demonstrate that Charm allows one to define high-level architecture models concisely, maximize reusability, capture unreasonable assumptions and inputs, and significantly speed-up design space exploration.

关键词： abstraction modeling DSL

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Global Distributed Associative Environment - Evolution of Parallel Dataflow computing System "Buran"

Global Distributed Associative Environment - Evolution of Pa...

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IEEE East-West Design and Test symposium (EWDTS)

作者： Ivannikov, A. D. Levchenko, N. N. Okunev, A. S. Stempkovsky, A. L. Zmejev, D. N. Russian Acad Sci Inst Design Problems Microelect IPPM RAS Moscow Russia

ISBN: (纸本)9781538657102

A high-performance parallel dataflow computing system that implements a dataflow computing model solves problems in the field of supercomputing, the main one of which is low real performance when parallelizing tasks for hundreds of thousands of computational cores. In this article, a new architecture for the parallel dataflow computing system is proposed - a global distributed associative environment. the concept of the computing system organization is described, which consists in dividing the system into associative computational cores, which in turn consist of a set of local associative elements. the new architecture demonstrates significant advantages over the previous architecture, primarily due to the increased reliability of the system and the simplification of programming.

关键词： computer architecture Computational modeling Crystals Programming Task analysis Reliability Context modeling

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Multi-Attribute Selection of Maritime Heterogenous Networks Based on SDN and Fog computing architecture 16

Multi-Attribute Selection of Maritime Heterogenous Networks ...

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16th International symposium on Modeling and Optimization in Mobile, Ad Hoc, and Wireless Networks (WiOpt)

作者： Yang, Tingting Wang, Rui Cui, Zhengqi Dong, Jie Xia, Minghua Dalian Maritime Univ Nav Coll Dalian Peoples R China Dalian Univ Technol Sch Software Dalian Peoples R China Sun Yat Sen Univ Sch Elect & Informat Technol Guangzhou Guangdong Peoples R China

ISBN: (纸本)9783903176003

Maritime intelligent transportation system provides intelligent, safe and efficient maritime transport services, which greatly facilitates the applications related to monitoring, safety, infotainment and cargo online management. the Internet of things (IoT) is especially suitable fir the networked communication environment at sea, and drives the development of maritime intelligent transportation on the trend. However, the existing data processing and forwarding methods pose great challenges to Intelligent Transportation Systems (ITS). In particular, real-time multi-type of data adopts different access technologies in wireless communication systems or use the same wireless access technology but belong to different wireless carriers. Utilizing the existing multi-type wireless communication systems, the architecture of the heterogeneous network through inter-system convergence makes multi-system complement to meet the demand of mobile communication services, so as to comprehensively play their respective advantages. In this paper, we consider a multi attribute decision-making method based on Analytic Hierarchy Process (AHP) and Rough Set based on the architecture of maritime wideband communication system with software defined network (SDN) and fog computing architecture. this paper aims to select a feasible network routing scheme for this heterogeneous network, based on multi-attribute of different networks. Finally, we simulate a communication network selection case based on the future maritime communications architecture, and solve the architecture optimization problem through our proposed algorithm. the issue of such network choice necessarily exists in maritime communications architecture, and our tentative assumptions and solutions will be an important basis for such issues.

关键词： Rough sets computer architecture Analytic hierarchy process Satellites Wireless communication Heterogeneous networks

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Crash Consistency in Encrypted Non-Volatile Main Memory Systems 24

Crash Consistency in Encrypted Non-Volatile Main Memory Syst...

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24th IEEE International symposium on high performance computer architecture (HPCA)

作者： Liu, Sihang Kolli, Aasheesh Ren, Jinglei Khan, Samira Univ Virginia Charlottesville VA 22903 USA VMware Res Palo Alto CA USA Penn State Univ University Pk PA 16802 USA Microsoft Res Redmond WA USA

ISBN: (纸本)9781538636596

Non-Volatile Main Memory (NVMM) systems provide high performance by directly manipulating persistent data in memory but require crash consistency support to recover data in a consistent slate in case of a power failure or system crash. In this work, we focus on the interplay between the crash consistency mechanisms and memory encryption. Memory encryption is necessary for these systems to protect data against the attackers with physical access to the persistent main memory. As decrypting data at every memory read access can significantly degrade the performance, prior works propose to use a memory encryption technique, counter-mode encryption, that reduces the decryption overhead by performing a memory read access in parallel with the decryption process using a counter associated with each cache line. therefore, a pair of data and counter value is needed to correctly decrypt data after a system crash. We demonstrate that counter-mode encryption does not readily extend to crash consistent NVMM systems as the system will fail to recover data in a consistent state if the encrypted data and associated counter are not written hack to memory atomically, a requirement we refer to as counter-atomicity. We show that naively enforcing counter-atomicity for all NVMM writes can serialize memory accesses and results in a significant performance degradation. In order to improve the performance, we make an observation that not all writes to NVMM need to be counter-atomic. the crash consistency mechanisms rely on versioning to keep one consistent copy of data intact while manipulating another version directly in memory As the recovery process only relies on the unmodified consistent version, it is not necessary to strictly enforce counter-atomicity for the writes that do not affect data recovery. Based on this insight, we propose selective counter atomicity that allows reordering of writes to data and associated counters when the writes to persistent memory do not alter the recover

关键词： Nonvolatile memory computer crashes Encryption Memory management Hardware Optimization

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Source-to-Source Instrumentation for Profiling Runtime Behavior of C++ Containers 20

Source-to-Source Instrumentation for Profiling Runtime Behav...

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20th International Conference on high performance computing and Communications, 16th IEEE International Conference on Smart City and 4th IEEE International Conference on Data Science and Systems, HPCC/SmartCity/DSS 2018

作者： Jungblut, Pascal Kowalewski, Roger Furlinger, Karl Munich Computer Science Department Oettingenstr. 67 Munich80538 Germany

ISBN: (纸本)9781538666142

With the growing popularity of C++ in the HPC community and increasingly heterogeneous memory layouts it is ever more important to understand the runtime behavior of applications and their data structures. Data locality and access patterns play a central role when identifying potential for optimization. However, C++'s combination of efficient low level features and high level abstractions like STL containers make it difficult to reason about data accesses and the lifetime of objects. We present data-instrumenter, a source-to-source transformation tool that instruments containers as well as application code to efficiently gather runtime data while still preserving static information from the AST. We evaluate the tool with the C++ LULESH implementation and other applications of varying complexity. the gathered metrics are used to identify costly operations while density-based clustering detects outliers in the program execution. We find that data-instrumenter can fully observe the interactions between containers, elements and the application while still being portable and platform-independent. © 2018 IEEE.

关键词： Containers

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FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud 18

FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simul...

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45th ACM/IEEE Annual International symposium on computer architecture (ISCA)

作者： Karandikar, Sagar Mao, Howard Kim, Donggyu Biancolin, David Amid, Alon Lee, Dayeol Pemberton, Nathan Amaro, Emmanuel Schmidt, Colin Chopra, Aditya Huang, Qijing Kovacs, Kyle Nikolic, Borivoje Katz, Randy Bachrach, Jonathan Asanovic, Krste Univ Calif Berkeley Dept Elect Engn & Comp Sci Berkeley CA 94720 USA

ISBN: (纸本)9781538659847

We present FireSim, an open-source simulation platform that enables cycle-exact microarchitectural simulation of large scale-out clusters by combining FPGA-accelerated simulation of silicon-proven RTL designs with a scalable, distributed network simulation. Unlike prior FPGA-accelerated simulation tools, FireSim runs on Amazon EC2 Fl, a public cloud FPGA platform, which greatly improves usability, provides elasticity, and lowers the cost of large-scale FPGA-based experiments. We describe the design and implementation of FireSim and show how it can provide sufficient performance to run modern applications at scale, to enable true hardware-software co-design. As an example, we demonstrate automatically generating and deploying a target cluster of 1,024 3.2 GHz quad-core server nodes, each with 16 GB of DRAM, interconnected by a 200 Gbit/s network with 2 microsecond latency, which simulates at a 3.4 MHz processor clock rate (less than 1,000x slowdown over real-time). In aggregate, this FireSim instantiation simulates 4,096 cores and 16 TB of memory, runs-14 billion instructions per second, and harnesses 12.8 million dollars worth of FPGAs at a total cost of only 1100 per simulation hour to the user. We present several examples to show how FireSim can be used to explore various research directions in warehouse-scale machine design, including modeling networks with high-bandwidth and low-latency, integrating arbitrary RTL designs for a variety of commodity and specialized datacenter nodes, and modeling a variety of datacenter organizations, as well as reusing the scale-out FireSim infrastructure to enable fast, massively parallel cycle-exact single-node microarchitectural experimentation.

关键词： Data centers computer simulation Field programmable gate arrays computer networks Distributed computing performance analysis Scalability computer architecture

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the PACE 2019 parameterized algorithms and computational experiments challenge: the fourth iteration 14

The PACE 2019 parameterized algorithms and computational exp...

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14th International symposium on Parameterized and Exact Computation, IPEC 2019

作者： Ayaz Dzulfikar, M. Fichte, Johannes K. Hecher, Markus University of Indonesia Kota Depok Jawa Barat16424 Indonesia Faculty of Computer Science TU Dresden Dresden01062 Germany Institute of Logic and Computation TU Wien Favoritenstraße 9-11 Wien1040 Austria University of Potsdam Germany

ISBN: (纸本)9783959771290

the organizers of the 4th Parameterized Algorithms and Computational Experiments challenge (PACE 2019) report on the 4th iteration of the PACE challenge. this year, the first track featured the MinVertexCover problem, which asks given an undirected graph G = (V, E) to output a set S ⊆ V of vertices such that for every edge vw ∈ E at least one endpoint belongs to S. the exact decision version of this problem is one of the most discussed problem if not even the prototypical problem in parameterized complexity theory. Another two tracks were dedicated to computing the hypertree width of a given hypergraph, which is a certain generalization of tree decompositions to hypergraphs that has widely been applied to problems in databases, constraint programming, and artificial intelligence. On one track we asked for submissions that compute hypertree decompositions of minimum width (MinHypertreeWidth) and on the other track we asked to heuristically compute hypertree decompositions of small width quickly (HeurHypertreeWidth). We received 28 implementations from 26 teams. this year we asked participants to submit solver descriptions in order to count as a submission for the challenge. We received those from 16 teams with overall 33 participants from 10 countries. One team submitted successful solutions to all three tracks. © Muhammad Ayaz Dzulfikar, Johannes K. Fichte, and Markus Hecher;licensed under Creative Commons License CC-BY.

关键词： Iterative methods

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Dynamic Checkpoint architecture for Reliability Improvement on Distributed Frameworks 37

Dynamic Checkpoint Architecture for Reliability Improvement ...

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37th IEEE International symposium on Reliable Distributed Systems (SRDS)

作者： Cardoso, Paulo Vinicius Barcelos, Patricia Pitthan Univ Fed Santa Maria Post Grad Program Comp Sci Santa Maria RS Brazil Univ Fed Santa Maria Comp Syst Lab Santa Maria RS Brazil

ISBN: (纸本)9781538683019

Fault tolerant mechanisms are essential to provide reliable feature for distributed systems. Checkpoint and Recovery is a widely used technique that consists on saving data states for a fast recovery in case of failure. On Apache Hadoop and Apache Spark - distributed high performance frameworks -, checkpoint aims to help on recovery steps after failures. However, wrong configuration of checkpoint attributes can degrade system performance and reliability, thus losing checkpoint purpose. this work proposes a dynamic architecture for checkpoint based on system monitoring and alerts. In order to avoid checkpoint problems on Hadoop and Spark, one implementation of dynamic mechanism is defined for each framework.

关键词： Sparks Monitoring Cluster computing computer architecture Fault tolerance Fault tolerant systems

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Design Space Exploration for Hardware Acceleration of Machine Learning Applications in MapReduce 26

Design Space Exploration for Hardware Acceleration of Machin...

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26th IEEE Annual International symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Neshatpour, Katayoun Mokrani, Hosein Mohammadi Sasan, Avesta Ghasemzadeh, Hassan Rafatirad, Setareh Homayoun, Houman George Mason Univ Fairfax VA 22030 USA Washington State Univ Pullman WA 99164 USA

ISBN: (纸本)9781538655221

Emerging big data applications heavily rely on machine learning algorithms which are computationally intensive. To meet computational requirements, and power and scalability challenges, FPGA based Hardware accelerators have found their way in data centers and cloud infrastructures. Recent efforts on HW acceleration of big data mainly attempt to accelerate a particular application and deploy it on a specific architecture that fits well its performance and power requirements. Given the diversity of architectures and ML applications, the important research question is which architecture is better suited to meet the performance, power and energy-efficiency requirements of a diverse range of ML-based analytics applications. In this work, we answer this question by investigating how the type of FPGA (low-end vs. high-end), and its integration with the CPU (on-chip vs. off-chip) along with the choice of CPU (high performance big vs. low power little servers) affects the speedup yield and power reduction in a CPU+FPGA architecture for machine learning applications implemented in MapReduce. We show that among the three architectural parameters, the type of CPU is the most dominant factor in determining the execution time and power in a CPU+FPGA architecture for MapReduce applications. the integration technology and FPGA type comes next, with the power and performance least sensitive to the FPGA type.

关键词： Field programmable gate arrays Servers computer architecture System-on-chip Hidden Markov models Space exploration Machine learning"

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