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Design Space Exploration for Hardware Acceleration of Machine Learning Applications in MapReduce 26

Design Space Exploration for Hardware Acceleration of Machin...

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26th IEEE Annual International symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Neshatpour, Katayoun Mokrani, Hosein Mohammadi Sasan, Avesta Ghasemzadeh, Hassan Rafatirad, Setareh Homayoun, Houman George Mason Univ Fairfax VA 22030 USA Washington State Univ Pullman WA 99164 USA

ISBN: (纸本)9781538655221

Emerging big data applications heavily rely on machine learning algorithms which are computationally intensive. To meet computational requirements, and power and scalability challenges, FPGA based Hardware accelerators have found their way in data centers and cloud infrastructures. Recent efforts on HW acceleration of big data mainly attempt to accelerate a particular application and deploy it on a specific architecture that fits well its performance and power requirements. Given the diversity of architectures and ML applications, the important research question is which architecture is better suited to meet the performance, power and energy-efficiency requirements of a diverse range of ML-based analytics applications. In this work, we answer this question by investigating how the type of FPGA (low-end vs. high-end), and its integration with the CPU (on-chip vs. off-chip) along with the choice of CPU (high performance big vs. low power little servers) affects the speedup yield and power reduction in a CPU+FPGA architecture for machine learning applications implemented in MapReduce. We show that among the three architectural parameters, the type of CPU is the most dominant factor in determining the execution time and power in a CPU+FPGA architecture for MapReduce applications. the integration technology and FPGA type comes next, with the power and performance least sensitive to the FPGA type.

关键词： Field programmable gate arrays Servers computer architecture System-on-chip Hidden Markov models Space exploration Machine learning"

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Spreading high performance computing Skills with E-Learning Support 16

Spreading High Performance Computing Skills with E-Learning ...

引用

16th IEEE International Conference on Emerging eLearning Technologies and Applications, ICETA 2018

作者： Melicherčík, M. Siladi, V. Svítek, M. Huraj, L. Faculty of Natural Sciences Department of Computer Science Matej Bel University Banska Bystrica Slovakia Faculty of Natural Sciences Department of Applied Informatics University of SS. Cyril and Methodius Trnava Slovakia

ISBN: (纸本)9781538679142

this paper deals with the topic of education in field of the high performance computing (HPC). According to our survey in Slovak academic institutions, there is lack of the HPC infrastructure users, who are capable of using resources at maximal level. Due to this, we will provide the users with a new e-Learning courses and trainings to improve their parallel programming skills as well as to become more familiar with the HPC infrastructure environment. these courses have also been applied at our university in new or innovated subjects. © 2018 IEEE.

关键词： Parallel programming

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Enabling Scientific computing on Memristive Accelerators 18

Enabling Scientific Computing on Memristive Accelerators

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45th ACM/IEEE Annual International symposium on computer architecture (ISCA)

作者： Feinberg, Ben Vengalam, Uday Kumar Reddy Whitehair, Nathan Wang, Shibo Ipek, Engin Univ Rochester Dept Elect & Comp Engn 601 Elmwood Ave Rochester NY 14627 USA Univ Rochester Dept Comp Sci Rochester NY 14627 USA

ISBN: (纸本)9781538659847

Linear algebra is ubiquitous across virtually every field of science and engineering, from climate modeling to macroeconomics. this ubiquity makes linear algebra a prime candidate for hardware acceleration, which can improve both the run time and the energy efficiency of a wide range of scientific applications. Recent work on memristive hardware accelerators shows significant potential to speed up matrix-vector multiplication (MVM), a critical linear algebra kernel at the heart of neural network inference tasks. Regrettably, the proposed hardware is constrained to a narrow range of workloads: although the eight- to 16-bit computations afforded by memristive MVM accelerators are acceptable for machine learning, they are insufficient for scientific computing where high-precision floating point is the norm. this paper presents the first proposal to enable scientific computing on memristive crossbars. three techniques are explored reducing overheads by exploiting exponent range locality, early termination of fixed-point computation, and static operation scheduling that together enable a fixed-point memristive accelerator to perform high-precision floating point without the exorbitant cost of na ve floating-point emulation on fixed-point hardware. A heterogeneous collection of crossbars with varying sizes is proposed to efficiently handle sparse matrices, and an algorithm for mapping the dense subblocks of a sparse matrix to an appropriate set of crossbars is investigated. the accelerator can be combined with existing GPU-based systems to handle datasets that cannot be efficiently handled by the memristive accelerator alone. the proposed optimizations permit the memristive MVM concept to be applied to a wide range of problem domains, respectively improving the execution time and energy dissipation of sparse linear solvers by 10.3x and 10.9x over a purely GPU-based system.

关键词： Accelerator architectures Resistive RAM

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IoT Devices Hardware Modeling for Executing Blockchain and Smart Contracts Applications

IoT Devices Hardware Modeling for Executing Blockchain and S...

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ACS/IEEE International Conference on computer Systems and Applications

作者： Roland Kromes François Verdier Université Côte d'Azur / LEAT / CNRS UMR 7248 France Université Côte d'Azur

ISBN: (数字)9781728150529

ISBN: (纸本)9781728150536

Today we find several solutions how to adapt IoT applications on blockchain technology. the most of the IoT devices have limited hardware resources to be able to execute a blockchain applications and take a real part of blockchain as a blockchain node. In this paper we analyzed Ethereum "aleth" blockchain and we identified the most called cryptographic functions that were used during the execution. Our aim is to model a low power consumption IoT architecture that can execute this blockchain application. the given architecture is deployed by a SystemC model and we used dedicated hardware accelerators to increase the performance. In addition we would like to deploy an architecture that meets the requirements of our industrial partner Renault. Renault figured out with a new type of use case with blockchain and especially with Smart Contracts applications where every cars are connected on a blockchain. With our IoT device model we could obtain a high gain of performance.

关键词： Blockchain Smart contracts Cryptography Peer-to-peer computing Hardware computer architecture Internet of things

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Delay-aware Resource Allocation for Data Analysis in Cloud-Edge System 16

Delay-aware Resource Allocation for Data Analysis in Cloud-E...

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16th IEEE ISPA / 17th IEEE IUCC / 8th IEEE BDCloud / 11th IEEE SocialCom / 8th IEEE SustainCom

作者： Li, Xin Lian, Zhen Qin, Xiaolin Abawajy, Jemal Nanjing Univ Aeronaut & Astronaut Coll Comp Sci & Technol Nanjing Jiangsu Peoples R China Chinese Acad Sci Inst Comp Technol State Key Lab Comp Architecture Beijing Peoples R China Deakin Univ Sch Informat Technol Geelong Vic Australia

ISBN: (纸本)9781728111414

there is a strong need for data analysis in information systems to support various services. Traditional cloud data centers provide powerful ability to conduct data analysis jobs. However, the data transmission consumes a large amount of time and leads to a long service delay. the QoS (Quality of Service) caused by long service delay is unacceptable for real-time services or applications. the collaboration with edge computing is an opportunity for service delay reduction. In this paper, we investigate the task placement problem for reducing service delay in cloud-edge system. We use the W-DAG (Weighted Directed Acyclic Graph) to model the data-intensive service or business logic. We analyze the data and resource requirements for the tasks, which constitute the integrated service, and make resource allocation between cloud data center and edge nodes. then, we propose the task placement algorithm to achieve shorter service delay. the core idea is to make a tradeoff between data transmission time and data analysis time. the simulation results show that our algorithm has significant performance improvement on service delay reduction.

关键词： delay-aware data-driven edge computing resource allocation task placement

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Redis++: A high performance in-memory database based on segmented memory management and two-level hash index 16

Redis++: A high performance in-memory database based on segm...

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16th IEEE International symposium on Parallel and Distributed Processing with Applications, 17th IEEE International Conference on Ubiquitous computing and Communications, 8th IEEE International Conference on Big Data and Cloud computing, 11th IEEE International Conference on Social computing and Networking and 8th IEEE International Conference on Sustainable computing and Communications, ISPA/IUCC/BDCloud/SocialCom/SustainCom 2018

作者： Zhang, Peng Xing, Lichao Yang, Ninggou Tan, Guolin Liu, Qingyun Zhang, Chuang Institute of Information Engineering Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences China

ISBN: (纸本)9781728111414

Redis is an open source in-memory data structure store, used as a database, cache and message broker. However, there are two problems that will degrade its performance. One is the memory fragmentation problem, another is cache miss problem. For the purpose, this paper presents a highperformance in-memory database Redis++. In the memory management mechanism, Redis++ will allocate and deallocate a fixedsize memory segment from the system. the data in each memory segment are stored continuously, and the memory segment is reclaimed based on the profit evaluation model. Secondly, a twolevel hash index structure is designed, the structure uses twolevel index to complete only one cache mapping per query. In addition, instruction-level parallelism is implemented using the single instruction multiple data instruction set, which speeds up the query efficiency of the secondary index. the experiments prove the effect of Redis++ on memory utilization, response latency and throughput. © 2018 IEEE.

关键词： Profitability

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high-performance and Energy-efficient Fault Tolerance Scheduling Algorithm Based on Improved TMR for Heterogeneous System 16

High-performance and Energy-efficient Fault Tolerance Schedu...

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16th IEEE ISPA / 17th IEEE IUCC / 8th IEEE BDCloud / 11th IEEE SocialCom / 8th IEEE SustainCom

作者： Yu, Shigan Tang, Zhimin Ye, Xiaochun Zhang, Zhimin Fan, Dongrui Jiang, Zhiying Chinese Acad Sci ICT SKL Comp Architecture Beijing Peoples R China Univ Chinese Acad Sci Sch Comp & Control Engn Beijing Peoples R China State Engn Lab Adv Microprocessor Technol Beijing Peoples R China Fuyang Normal Univ Informat Engn Coll Fuyang Anhui Peoples R China

ISBN: (纸本)9781728111414

Traditional TMR (three Mode Redundancy) method based on homogeneous multicore has been used in solving the transient fault of microprocessor and improving reliability, but it is characterized by low performance and high power consumption. this paper proposes an improved TMR method to improve the performance of fault-tolerant scheduling for heterogeneous system (HEFT-ITMR). the tasks are divided into two groups with/without fault-tolerant requirements, which are scheduled by traditional TMR method and by competitive mechanism, respectively. the tasks without fault-tolerant requirements will be re-executed in traditional TMR method if the task reliability fail to meet the requirements. the experimental results demonstrate that the proposed method can achieve a 18.1% improvement in average efficiency over traditional TMR method when running three types of benchmark without injecting errors and yield an average speedup of 15.3% and the power consumption can also be decreased by 20.5% over TMR when 200 errors are injected. In addition, a parallel optimization method P-HEFT-ITMR is proposed to further improve system performance and reduce system power consumption while ensuring system reliability.

关键词： TMR Fault Tolerance Scheduling Heterogeneous System high-performance

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Lazy Persistency: a high-Performing and Write-Efficient Software Persistency Technique 18

Lazy Persistency: a High-Performing and Write-Efficient Soft...

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45th ACM/IEEE Annual International symposium on computer architecture (ISCA)

作者： Alshboul, Mohammad Tuck, James Solihin, Yan North Carolina State Univ Dept Elect & Comp Engn Raleigh NC 27695 USA

ISBN: (纸本)9781538659847

Emerging Non-Volatile Memories (NVMs) are expected to be included in future main memory, providing the opportunity to host important data persistently in main memory. However, achieving persistency requires that programs be written with failure-safety in mind. Many persistency models and techniques have been proposed to help the programmer reason about failure-safety. they require that the programmer eagerly flush data out of caches to make it persistent. Eager persistency comes with a large overhead because it adds many instructions to the program for flushing cache lines and incurs costly stalls at barriers to wait for data to become durable. To reduce these overheads, we propose Lazy Persistency (LP), a software persistency technique that allows caches to slowly send dirty blocks to the NVMM through natural evictions. With LP, there are no additional writes to NVMM, no decrease in write endurance, and no performance degradation from cache line flushes and barriers. Persistency failures are discovered using software error detection (checksum), and the system recovers from them by recomputing inconsistent results. We describe the properties and design of LP and demonstrate how it can be applied to loop-based kernels popularly used in scientific computing. We evaluate LP and compare it to the state-of-the-art Eager Persistency technique from prior work. Compared to it, LP reduces the execution time and write amplification overheads from 9% and 21% to only 1% and 3%, respectively.

关键词： Emerging Memory Technology Memory Systems Multi-core and Parallel architectures

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high performance Dynamic Communication on Reconfigurable Clusters (extended abstract) 26

High Performance Dynamic Communication on Reconfigurable Clu...

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26th IEEE Annual International symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Sheng, Jiayi Yang, Chen Wang, Tianqi Herbordt, Martin C. Boston Univ Dept Elect & Comp Engn Boston MA 02215 USA Univ Sci & Technol China Dept Phys Hefei Anhui Peoples R China

ISBN: (纸本)9781538655221

FPGA clusters with the FPGAs directly linked through their Multi-Gigabit Transceiver (MGT) ports have a proven advantage over other commodity architectures for communication-bound applications. We find that the standard wormhole routers need some modification to be appropriate for clusters with tightly coupled FPGAs, and create such a router. We generalize this router so that it is parameterized by several parameters including routing algorithm, arbitration policy, virtual channels, and buffers. We have evaluated these designs with respect to a number standard communication patterns and packet sizes. these results enable selection of the appropriate router for any resource budget. Finally, We find that the optimality of the router design varies significantly with workload. We observe that for a 512 FPGA cluster, connected in an 8(3) torus, compared with the router configuration with the best average performance, application-aware router configurations reduce average batch latency by 3%, improve the throughput by 6% on average, and improve area consumption by 50%.

关键词： Field programmable gate arrays Switches Standards Routing computer architecture three-dimensional displays Physics"

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PicoDriver: Fast-path Device Drivers for Multi-kernel Operating Systems 18

PicoDriver: Fast-path Device Drivers for Multi-kernel Operat...

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27th ACM International symposium on high-performance Parallel and Distributed computing (HPDC)

作者： Gerofi, Balazs Santogidis, Aram Martinet, Dominique Ishikawa, Yutaka RIKEN Adv Inst Computat Sci Tokyo Japan CERN Geneva Switzerland CEA Paris France

ISBN: (纸本)9781450357852

Lightweight kernel (LWK) operating systems (OS) in high-end supercomputing have a proven track record of excellent scalability. However, the lack of full Linux compatibility and limited availability of device drivers in LWKs have prohibited their wide-spread deployment. Multi-kernels, where an LWK is run side-by-side with Linux on many-core CPUs, have been proposed to address these shortcomings. In a multi-kernel system the LWK implements only performance critical kernel services and the rest of the OS functionality is offloaded to Linux. Access to device drivers is usually attained via offloading. Although high-performance interconnects are commonly driven from user-space, there are networks (e.g., Intel's OmniPath or Cray's Gemini) that require device driver interaction for a number of performance sensitive operations, which in turn can be adversely impacted by system call offloading. In this paper, we propose PicoDriver, a novel device driver architecture for multi-kernels, where only a small part of the driver (i.e., the performance critical piece) is ported to the LWK and access to the rest remains transparent via Linux. Our solution requires no modifications to the original Linux driver, yet it enables optimization opportunities in the lightweight kernel. We implemented this system in the IHK/McKernel multi-kernel OS and demonstrate that on 16,384 Intel Knight's Landing (KNL) CPU cores (interconnected by OmniPath network) we can outperform Linux by up to 30% on various mini-applications.

关键词： high-performance computing operating systems lightweight kernels multi kernels device drivers

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