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Dataflow based Near Data computing Achieves Excellent Energy Efficiency 2017

Dataflow based Near Data Computing Achieves Excellent Energy...

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8th International symposium on highly Efficient Accelerators and Reconfigurable Technologies (HEART)

作者： Shelor, Charles Kavi, Krishna Univ North Texas Dept Comp Sci & Engn Denton TX 76203 USA

ISBN: (纸本)9781450353168

the emergence of 3D-DRAM has rekindled interest in near data computing (NDC) research. this article introduces dataflow processing in memory (DFPIM) which melds near data computing, dataflow architecture, coarse-grained reconfigurable logic (CGRL), and 3D-DRAM technologies to provide high performance and very high energy efficiency for stream oriented and big data application kernels. the application of dataflow architecture with a CGRL implementation provides a flexible, energy efficient computing platform. the initial evaluation presented in this paper shows an average speedup of 5.5 is achieved with an energy efficiency factor of 460.

关键词： Dataflow computer architecture Near Data computing Processing-in-Memory Coarse Grain Reconfigurable Logic energy efficient computing big-data 3D stacked DRAM

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Energy-Efficient Interconnect via Router Parking

Energy-Efficient Interconnect via Router Parking

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19th IEEE International symposium on high performance computer architecture (HPCA)

作者： Samih, Ahmad Wang, Ren Krishna, Anil Maciocco, Christian Tai, Charlie Solihin, Yan Intel Corp Intel Architecture Grp Austin TX USA

ISBN: (纸本)9781467355872

the increase in on-chip core counts in Chip MultiProcessors (CMPs) has led to the adoption of interconnects such as Mesh and Torus, which consume an increasing fraction of the chip power. Moreover, as technology and voltage continue to scale down, static power consumes a larger fraction of the total power;reducing it is increasingly important for energy proportional computing. Currently, processor designers strive to send under-utilized cores into deep sleep states in order to reduce idling power and improve overall energy efficiency. However, even in state-of-the-art CMP designs, when a core goes to sleep the router attached to it remains active in order to continue packet forwarding. In this paper, we propose Router Parking - selectively power-gating routers attached to parked cores. Router Parking ensures that network connectivity is maintained, and limits the average interconnect latency impact of packet detouring around parked routers. We present two Router Parking algorithms - an aggressive approach to park as many routers as possible, and a conservative approach that parks a limited set of routers in order to keep the impact on latency increase minimal. Further, we propose an adaptive policy to choose between the two algorithms at run-time. We evaluate our algorithms using both synthetic traffic as well as real workloads taken from SPEC CPU2006 and PARSEC 2.1 benchmark suites. Our evaluation results show that Router Parking can achieve significant savings in the total interconnect energy (average of 32%, 40% and 41% for the synthetic, SPEC CPU2006, and PARSEC 2.1 workloads, respectively).

关键词： benchmark testing energy conservation integrated circuit design microprocessor chips multiprocessor interconnection networks network routing power aware computing

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proceedings of the 20th Annual International symposium on computer architecture

Proceedings of the 20th Annual International Symposium on Co...

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proceedings of the 20th Annual International symposium on computer architecture

ISBN: (纸本)0818638109

this conference proceedings contain 32 papers. the main topics are architectural characteristics of scientific applications, TLBs and memory management, input/output systems, fault-tolerant computer architecture, multiprocessor caches, high-performance computing from the application perspective, multithreading support, shared memory systems, cache designs,and multiprocessor memory systems and interconnections.

关键词： computer architecture

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BulletProof: A defect-tolerant CMP switch architecture

BulletProof: A defect-tolerant CMP switch architecture

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12th International symposium on high-performance computer architecture

作者： Constantinides, Kypros Plaza, Stephen Blome, Jason Zhang, Bin Bertacco, Valeria Mahlke, Scott Austin, Todd Orshansky, Michael Univ Michigan Adv Comp Architecture Lab Ann Arbor MI 48109 USA Univ Texas Austin Dept Elect & Comp Engn Austin TX 78712 USA

ISBN: (纸本)0780393686

As silicon technologies move into the nanometer regime, transistor reliability is expected to wane as devices become subject to extreme process variation, particle-induced transient errors, and transistor wear-out. Unless these challenges are addressed, computer vendors can expect low yields and short mean-times-to-failure. In this paper, we examine the challenges of designing complex computing systems in the presence of transient and permanent faults. We select one small aspect of a typical chip multiprocessor (CMP) system to study in detail, a single CMP router switch. To start, we develop a unified model of faults, based on the time-tested bathtub curve. Using this convenient abstraction, we analyze the reliability versus area tradeoff across a wide spectrum of CMP switch designs, ranging from unprotected designs to fully protected designs with online repair and recovery capabilities ities. Protection is considered at multiple levels from the entire system down through arbitrary partitions of the design. To better understand the impact of these faults, we evaluate our CMP switch designs using circuit-level timing on detailed physical layouts. Our experimental results are quite illuminating. We find that designs are attainable that can tolerate a larger number of defects with less overhead than naive triple-modular redundancy, using domain-specific techniques such as end-to-end error detection, resource sparing, automatic circuit decomposition, and iterative diagnosis and reconfiguration.

关键词： computer architecture

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Energy efficient seismic wave propagation simulation on a low-power manycore processor 26

Energy efficient seismic wave propagation simulation on a lo...

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26th International symposium on computer architecture and high performance computing, SBAC-PAD 2014

作者： Castro, Marcio Dupros, Fabrice Francesquini, Emilio Mehautk, Jean-Francois Navaux, Philippe O.A. Informatics Institute Federal University of Rio Grande Do sul Brazil Department of Informatics and Statistics Federal University of Santa Catarina Brazil BRGM Orléans France Institute of Computing University of Campinas Brazil Institute of Mathematics and Statistics University of São Paulo Brazil CEA/DRT University of Grenoble France

ISBN: (纸本)9781479969043

Large-scale simulation of seismic wave propagation is an active research topic. Its high demand for processing power makes it a good match for high performance computing (HPC). Although we have observed a steady increase on the processing capabilities of HPC platforms, their energy efficiency is still lacking behind. In this paper, we analyze the use of a low-power manycore processor, the MPPA-256, for seismic wave propagation simulations. First we look at its peculiar characteristics such as limited amount of on-chip memory and describe the intricate solution we brought forth to deal with this processor's idiosyncrasies. Next, we compare the performance and energy efficiency of seismic wave propagation on MPPA-256 to other commonplace platforms such as general-purpose processors and a GPU. Finally, we wrap up with the conclusion that, even if MPPA-256 presents an increased software development complexity, it can indeed be used as an energy efficient alternative to current HPC platforms, resulting in up to 71% and 81% less energy than a GPU and a general-purpose processor, respectively. © 2014 IEEE.

关键词： Graphics processing unit

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high-speed restoration of atomic force microscopy images using tikhonov regularization in GPGPU 26

High-speed restoration of atomic force microscopy images usi...

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26th IEEE International symposium on computer architecture and high performance computing Workshops, SBAC-PADW 2014

作者： Quelhas, Klaus N. Cidade, Geraldo A. G. Farias, Ricardo COPPE/System Engineering Federal University of Rio de Janeiro Rio de Janeiro RJ Brazil Biophysics Institute Carlos Chagas Filho Federal University of Rio de Janeiro Rio de Janeiro RJ Brazil

ISBN: (纸本)9781479970148

the Atomic Force Microscopy (AFM) is a scanning probe technique widely used to produce nanometric scaled images of virtually any kind of non-conductive or biological surface. Depending on the scanning dimensions an expected AFM image structure is subjected to be modified by great amounts of external noise (low Signal/Noise ratios) - electrical or mechanical - and/or blurring due to the geometry of the measuring probe. In order to minimize such effects, image restoration techniques can be employed. the one based on the minimization of the Tikhonov's regularization functional is described, taking into account the characteristics of the measuring probe and the S/N ratio. this work proposes optimizations on both serial and parallel restoration algorithms, using CUDA library on a General Purpose Graphics Processing Unit, GPGPU, in terms of time performance and quality of restoration in regime of high speed imaging, one frame/sec or more. the results obtained are so far very promising, reaching speedups up to 43x over previous implementations. © 2014 IEEE.

关键词： Atomic force microscopy

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Gables: A Roofline Model for Mobile SoCs 25

Gables: A Roofline Model for Mobile SoCs

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25th IEEE International symposium on high performance computer architecture (HPCA)

作者： Hill, Mark D. Reddi, Vijay Janapa Univ Wisconsin Dept Comp Sci Madison WI 53706 USA Harvard Univ Sch Engn & Appl Sci Cambridge MA 02138 USA

ISBN: (纸本)9781728114446

Over a billion mobile consumer system-on-chip (SoC) chipsets ship each year. Of these, the mobile consumer market undoubtedly involving smartphones has a significant market share. Most modern smartphones comprise of advanced SoC architectures that are made up of multiple cores, GPS, and many different programmable and fixed-function accelerators connected via a complex hierarchy of interconnects with the goal of running a dozen or more critical software usecases under strict power, thermal and energy constraints. the steadily growing complexity of a modern SoC challenges hardware computer architects on how best to do early stage ideation. Late SoC design typically relies on detailed full-system simulation once the hardware is specified and accelerator software is written or ported. However, early-stage SoC design must often select accelerators before a single line of software is written. To help frame SoC thinking and guide early stage mobile SoC design, in this paper we contribute the Gables model that refines and retargets the Roofline model-designed originally for the performance and bandwidth limits of a multicore chip-to model each accelerator on a SoC, to apportion work concurrently among different accelerators (justified by our usecase analysis), and calculate a SoC performance upper bound. We evaluate the Gables model with an existing SoC and develop several extensions that allow Gables to inform early stage mobile SoC design.

关键词： Accelerator architectures Mobile computing Processor architecture System-on-Chip

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Robust resource management for metacomputers 9

Robust resource management for metacomputers

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9th IEEE International symposium on high performance Distributed computing

作者： Gehring, J Streit, A Univ Gesamthsch Paderborn Paderborn Ctr Parallel Comp D-33102 Paderborn Germany

ISBN: (纸本)0769507832;0769507840

In this paper we present a robust software infrastructure for metacomputing. the system is intended to be used by others as a building block for large and powerful computational grids. Much effort has been taken to develop a fault tolerant architecture that does nor exhibit a single point of failure. Furthermore, we designed the system to be modular lean, and portable. It is available as open source and has been successfully compiled on POSIX and MS Windows compliant platforms. the system does not origin from a laboratory environment but has proven its robustness within two large metacomputing installations. It embodies a modular concept which allows easy integration of new or modified components. Hence, it is not necessary to buy into the system as whole. We rather encourage others to use only those components that fit into their specific environments.

关键词： computer architecture Fault tolerance Grid computing Metacomputing Parallel processing Programming profession Resource management Robustness Security Testing

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BeaconGNN: Large-Scale GNN Acceleration with Out-of-Order Streaming In-Storage computing 30

BeaconGNN: Large-Scale GNN Acceleration with Out-of-Order St...

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30th IEEE International symposium on high-performance computer architecture (HPCA)

作者： Wang, Yuyue Pan, Xiurui An, Yuda Zhang, Jie Reinman, Glenn Univ Calif Los Angeles Los Angeles CA 90095 USA Peking Univ Beijing Peoples R China

ISBN: (纸本)9798350393132;9798350393149

Prior in-storage computing (ISC) solutions show fundamental drawbacks when applied to GNN acceleration. First, they obey a strict ordering of GNN neighbor sampling. Such serialization fails to utilize flash internal parallelism. Second, the I/O sizes generated by GNN are much smaller than the minimum flash access granularity. the limited channel bandwidth is wasted when serving the requests. third, the prior solutions rely on firmware-based request processing, making the backend I/O throughput constrained by the embedded core processing power. To address these challenges, we propose BeaconGNN, an instorage computing (ISC) design for GNN that supports both large-scale graph structures and feature tables. First, it utilizes a novel graph format to enable out-of-order GNN neighbor sampling, improving flash resource utilization. Second, it deploys near-data processing engines across multiple levels of the flash hierarchy (i.e., controller, channel, and die). Specifically, flashdie-level samplers perform neighbor samplings while reducing channel transfer simultaneously. Flash-channel-level command routers communicate with backend dies without the involvement of flash firmware. Lastly, a spatial accelerator is attached to the device bus to accelerate GNN computation. With our software and hardware co-design, BeaconGNN achieves up to 11.6x higher throughput and 4x better energy efficiency than the stateof-the-art ISC design.

关键词： computational storage Flash SSD GNN acceleration in-storage computing storage system

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Can dataflow subsume von Neumann computing?.

Can dataflow subsume von Neumann computing?.

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16th Annual International symposium on computer architecture

作者： Rishiyur, S.Nikhil Arvind MIT Cambridge MA USA

the question of what a von Neumann processor can borrow from dataflow to make it more suitable for a multiprocessor is explored. Starting with a simple, RISC (reduced-instruction-self-computer)-like instruction set, the author shows how to change the underlying processor organization to make it multithreaded. then he extends it with three instructions that give it a fine-grained, dataflow capability, and he calls the result P-RISC, for parallel RISC. Finally, the author discusses memory support for such multiprocessors. He compares his approach to existing MIMD (multiple-instruction multiple-data-stream) machines and to other dataflow machines.

关键词： computer architecture

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