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Cross-layer self-adaptive/self-aware system software for exascale systems 26

Cross-layer self-adaptive/self-aware system software for exa...

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26th International symposium on computer architecture and high performance computing, SBAC-PAD 2014

作者： Gioiosa, Roberto Kestor, Gokcen Kerbyson, Darren J. Hoisie, Adolfy High Performance Computing Pacific Northwest National Laboratory RichlandWA United States

ISBN: (纸本)9781479969043

the extreme level of parallelism coupled with the limited available power budget expected in the exascale era brings unprecedented challenges that demand optimization of performance, power and resiliency in unison. Scalability on such systems is of paramount importance, while power and reliability issues may change the execution environment in which a parallel application runs. To solve these challenges exascale systems will require an introspective system software that combines system and application observations across all system stack layers with online feedback and adaptation mechanisms. In this paper we propose the design of a novel self-aware, selfadaptive system software in which a kernel-level Monitor, which continuously inspects the evolution of the target system through observation of Sensors, is combined with a user-level Controller, which reacts to changes in the execution environment, explores opportunities to increase performance, save power and adapts applications to new execution scenarios. We show that the monitoring system accurately monitors the evolution of parallel applications with a runtime overhead below 1-2%. As a test case, we design and implement a runtime system that aims at optimizing application's performance and system power consumption on complex hierarchical architectures. Our results show that our adaptive system reaches 98% of performance efficiency of manually-tuned applications. © 2014 IEEE.

关键词： Budget control

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Global grid monitoring: the EGEE/WLCG case

Global grid monitoring: The EGEE/WLCG case

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16th International symposium on high performance Distributed computing 2007, HPDC'07 and Co-Located Workshops

作者： Duarte, Alexandre Nyczyk, Piotr Retico, Antonio Vicinanza, Domenico European Organization for Nuclear Research Geneva Switzerland Federal University of Campina Grande Campina Grande Brazil University of Salerno Salerno Italy

ISBN: (纸本)1595937161

Grids have the potential to revolutionize computing by providing ubiquitous, on demand access to computational services and resources. However, grid systems are extremely large, complex and prone to failures. In this paper we present a tool able to to check if a given grid service works as expected for a given user or set of users on the different resources available on a grid. Our solution deals with the grid services as single components that should produce an expected output to a pre-defined input, what is quite similar to unit testing. Our tool, called Service Availability Monitoring or SAM, is being currently used to monitor some of the largest (maybe the largest) production grids available today. Copyright 2007 ACM.

关键词： Grid computing

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Evaluation Model and performance Analysis of NIC Aggregations in Containerized Private Clouds 35

Evaluation Model and Performance Analysis of NIC Aggregation...

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35th IEEE International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Maliszewski, Anderson M. Griebler, Dalvan Roloff, Eduardo Righi, Rodrigo da Rosa Navaux, Philippe O. A. Fed Univ Rio Grande Sul UFRGS Informat Inst Porto Alegre RS Brazil Tres de Maio Fac SETREM Lab Adv Res Cloud Comp LARCC Tres De Maio Brazil Pontifical Catholica Univ Rio Grande Sul PUCRS Sch Technol Porto Alegre RS Brazil Univ Vale Rio Sinos UNISINOS Software Innovat Lab SoftwareLab Sao Leopoldo Brazil

ISBN: (纸本)9798350381603

the availability of computational resources changed significantly due to cloud computing. In addition, we have witnessed efforts to execute high-performance computing (HPC) applications in the cloud attracted by the advantages of cost savings and scalable/elastic resource allocation. Allocating more powerful hardware and exclusivity allocating resources such as memory, storage, and CPU can improve performance in the cloud. For network interconnection, significant noise, and other inferences are generated by several simultaneous instances (multitenants) communicating using the same network. As increasing the network bandwidth may be an alternative, we designed an evaluation model, and performance analysis of NIC aggregation approaches in containerized private clouds. the experiments using NAS Parallel Benchmarks revealed that NIC aggregation approach outperforms the baseline up to similar to 98% of the executions with applications characterized by intensive network use. Also, the Balance Round-Robin aggregation mode performed better than the 802.3ad aggregation mode in most assessments.

关键词： Cloud computing Private Cloud high performance computing Network performance NIC Aggregation performance Analysis

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2K:: A distributed operating system for dynamic heterogeneous environments 9

2<i>K</i>:: A distributed operating system for dynamic heter...

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9th IEEE International symposium on high performance Distributed computing

作者： Kon, F Campbell, RH Mickunas, MD Nahrstedt, K Ballesteros, FJ Univ Illinois Dept Comp Sci Urbana IL 61801 USA

ISBN: (纸本)0769507832;0769507840

the first decades of the new millennium will witness an explosive growth in the number and diversity of networked devices and portals. We foresee high degrees of mobility, heterogeneity, and interactions among computing devices connected to global networks. While previous research in distributed operating systems solved many problems related to resource management, they seldom addressed the problems of heterogeneity and dynamic adaptability. On the other hand, middleware solutions, like CORBA and Java/Jini, solve part of the heterogeneity problem by permitting seamless communication among different platforms. But, they do not address dynamic resource management and adaptability for applications requiring high-performance distributed computing. this paper presents 2K, an integrated operating system architecture that addresses the problems of resource management in heterogeneous networks, dynamic adaptability, and configuration of component-based distributed applications.

关键词： computer architecture computer science Distributed computing Environmental management Explosives Middleware Operating systems Portals Power system management Resource management

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Reducing compiler-inserted instrumentation in unified-parallel-C code generation 26

Reducing compiler-inserted instrumentation in unified-parall...

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26th International symposium on computer architecture and high performance computing, SBAC-PAD 2014

作者： Alvanosl, Michail Amaral, José Nelson Tiotto, Ettore Farreras, Montse Martorell, Xavier Computer Science Barcelona Supercomputing Center Spain Department of Computing Science University of Alberta Edmonton Canada Static Compilation Technology IBM Toronto Laboratory Markham Canada Department of Computer Architecture Universitat Politècnica de Catalunya Spain

ISBN: (纸本)9781479969043

Programs written in Partitioned Global Address Space (PGAS) languages can access any location of the entire address space via standard read/write operations. However, the compiler have to create the communication mechanisms and the runtime system to use synchronization primitives to ensure the correct execution of the programs. However, PGAS programs may have fine-grained shared accesses that lead to performance degradation. One solution is to use the inspector-executor technique to determine which accesses are indeed remote and which accesses may be coalesced in larger remote access operations. A straightforward implementation of the inspector-executor in a PGAS system may result in excessive instrumentation that hinders performance. this paper introduces a shared-data localization transformation based on linear memory descriptors (LMADs) that reduces the amount of instrumentation introduced by the compiler into programs written in the UPC language and describes a prototype implementation of the proposed transformation. A performance evaluation, using up to 2048 cores of a POWER 775 supercomputer, allows for a prediction that applications with regular accesses can achieve up to 180% of the performance of handoptimized versions while applications with irregular accesses yield performance gain from 1.12X up to 6.3X speedup. © 2014 IEEE.

关键词： Linear transformations

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VIP: A Versatile Inference Processor 25

VIP: A Versatile Inference Processor

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25th IEEE International symposium on high performance computer architecture (HPCA)

作者： Hurkat, Skand Martinez, Jose F. Microsoft Redmond WA 98052 USA Cornell Univ Ithaca NY USA

ISBN: (纸本)9781728114446

We present Versatile Inference Processor (VIP), a highly programmable architecture for machine learning inference. VIP consists of 128 lightweight processing engines employing a vector processing paradigm, with a simple ISA and carefully chosen microarchitecture features. It is coupled with a modern, lightly customized, 3D-stacked memory system. through detailed execution-driven simulations backed by RTL synthesis, we show that we can achieve online, real-time vision throughput (24 fps), at low power consumption, for both full-HD depth-from-stereo using belief propagation, and VGG-16 and VGG-19 deep neural networks (batch size of 1). Our RTL synthesis of a VIP processing engine in TSMC 28nm technology, using a commercial standard-cell library supplied by ARM, results in 18mm(2) of silicon area and 3.5W to 4.8W of power consumption for all 128 VIP processing engines combined.

关键词： Engines Optical imaging Field programmable gate arrays Convolution Task analysis computer architecture Microarchitecture

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Evaluation of memory system for integrated Prolog processor IPP. 89

Evaluation of memory system for integrated Prolog processor ...

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16th Annual International symposium on computer architecture

作者： Morioka, M. Yamaguchi, S. Bandoh, T. Hitachi Ltd Hitachi Jpn

ISBN: (纸本)9780897913195

An optimal memory system for realizing a high-performance integrated Prolog processor, the IPP, is discussed. First, the memory access characteristics of Prolog are analyzed by a simulator, which simulates the execution of a Prolog program at a microinstruction level. the main findings from this analysis are that the write-access ratio of Prolog is larger than that of procedural language and that performance improvement requires the memory system to process concentrated, large write accesses effectively. the Prolog acceleration strategies for conventional cache memories are discussed. Comparison is made of cache memories (store-swap, store-through) and a stack buffer, regarding not only performance but also reliability, complexity, and effects on procedural languages. It is concluded that the advanced store-through cache is best suited to the IPP.

关键词： computer systems, Digital

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Experience of Parallelizing cryo-EM 3D Reconstruction on a CPU-GPU Heterogeneous System 11

Experience of Parallelizing cryo-EM 3D Reconstruction on a C...

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20th International symposium on high performance Distributed computing

作者： Li, Linchuan Li, Xingjian Tan, Guangming Chen, Mingyu Zhang, Peiheng Chinese Acad Sci Inst Comp Technol Key Lab Comp Syst & Architecture Beijing Peoples R China

ISBN: (纸本)9781450305525

Heterogeneous architecture is becoming an important way to build a massive parallel computer system, i.e. the CPU-GPU heterogeneous systems ranked in Top500 list. However, it is a challenge to efficiently utilize massive parallelism of both applications and architectures on such heterogeneous systems. In this paper we present a practice on how to exploit and orchestrate parallelism at algorithm level to take advantage of underlying parallelism at architecture level. A potential Petaflops application cryo-EM 3D reconstruction is selected as an example. We exploit all possible parallelism in cryo-EM 3D reconstruction, and leverage a self-adaptive dynamic scheduling algorithm to create a proper parallelism mapping between the application and architecture. the parallelized programs are evaluated on a subsystem of Dawning Nebulae supercomputer, whose node is composed of two Intel six-core Xeon CPUs and one Nvidia Fermi CPU. the experiment confirms that hierarchical parallelism is an efficient pattern of parallel programming to utilize capabilities of both CPU and CPU in a heterogeneous system. the CUDA kernels run more than 3 times faster than the OpenMP parallelized ones using 12 cores (threads). Based on the CPU-only version, the hybrid CPU-CPU program further improves the whole application's performance by 30% on the average.

关键词： task parallelism data parallelism high performance computing CUDA cryo-EM

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Optical Interconnects between Microprocessor and Memories 16

Optical Interconnects between Microprocessor and Memories

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16th IEEE International Conference on high performance computing and Communications HPCC 2014\11th IEEE International Conference on Embedded Software and Systems ICESS 2014\6th International symposium on Cyberspace Safety and Security CSS 2014

作者： Luo, Daxin Liu, Yaoda Liu, Xiaoying Zhang, Bin Li, Gang Liao, Qi Hao, Qinfen Wei, Zhulin Huawei Technol Co Ltd Shannon Lab Shenzhen Guangdong Peoples R China

ISBN: (纸本)9781479961238

More memories will be required in a future server as the number of cores per microprocessor keeps growing, which means either the capacity of a memory chip or the number of memory chips connected to a microprocessor needs to catch up with the increasing core counts. With electrical interconnects between microprocessor and memories, layout and placement of memory chips around the microprocessor becomes a bottleneck. Optical interconnects will solve this problem by putting memory chips further away from a microprocessor. We investigate in this paper the performance of a computer with optically connected remote memory instead of electrically connected local memory, and verified that an operating system can successfully run with only optically connected memory. the experimental results demonstrated the feasibility of utilizing optically connected remote memory as memory instead of storage as discussed mostly in the literature.

关键词： computer architecture optical interconnects latency microprocessor memory

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ASADI: Accelerating Sparse Attention using Diagonal-based In-situ computing 30

ASADI: Accelerating Sparse Attention using Diagonal-based In...

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30th IEEE International symposium on high-performance computer architecture (HPCA)

作者： Li, Huize Li, Zhaoying Bai, Zhenyu Mitra, Tulika Natl Univ Singapore Sch Comp Singapore Singapore

ISBN: (纸本)9798350393132;9798350393149

the self-attention mechanism is the performance bottleneck of Transformer-based language models, particularly for long sequences. Researchers have proposed using sparse attention to speed up the Transformer. However, sparse attention introduces significant random access overhead, limiting computational efficiency. To mitigate this issue, researchers attempt to improve data reuse by utilizing row/column locality. Unfortunately, we find that sparse attention does not naturally exhibit strong row/column locality, but instead has excellent diagonal locality. thus, it is worthwhile to use diagonal compression (DIA) format. However, existing sparse matrix computation paradigms struggle to efficiently support DIA format in attention computation. To address this problem, we propose ASADI, a novel softwarehardware co-designed sparse attention accelerator. In the software side, we propose a new sparse matrix computation paradigm that directly supports the DIA format in self-attention computation. In the hardware side, we present a novel sparse attention accelerator that efficiently implements our computation paradigm using highly parallel in-situ computing. We thoroughly evaluate ASADI across various models and datasets. Our experimental results demonstrate an average performance improvement of 18.6x and energy savings of 2.9x compared to a PIM-based baseline.

关键词： diagonal compression format processing-in-memory sparse attention

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