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A bit level area aware cache-based architecture for memory repairs

A bit level area aware cache-based architecture for memory r...

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16th IEEE International On-Line Testing symposium, IOLTS 2010

作者： Axelos, Nicholas Pekmestzi, Kiamal School of Electrical and Computer Engineering National Technical University of Athens Greece

ISBN: (纸本)9781424477227

In this paper an architecture for memory Built-In Self-Repair (BISR) is presented. the proposed scheme utilises a multiple bank cache-like memory for repairing defective bits and is a heavily modified version of a previously studied architecture that repaired at the word level, while the proposed repairs at the bit level. this scheme achieves high repair ratios at high defect densities with small overheads. the two architectures are compared on their footprint by means of an area approximation analysis. the proposed modified scheme shows significant area savings (greater than 4 times) while retaining the same high repairability qualities as its predecessor. © 2010 IEEE.

关键词： Repair

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2K:: A distributed operating system for dynamic heterogeneous environments 9

2<i>K</i>:: A distributed operating system for dynamic heter...

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9th IEEE International symposium on high performance Distributed computing

作者： Kon, F Campbell, RH Mickunas, MD Nahrstedt, K Ballesteros, FJ Univ Illinois Dept Comp Sci Urbana IL 61801 USA

ISBN: (纸本)0769507832;0769507840

the first decades of the new millennium will witness an explosive growth in the number and diversity of networked devices and portals. We foresee high degrees of mobility, heterogeneity, and interactions among computing devices connected to global networks. While previous research in distributed operating systems solved many problems related to resource management, they seldom addressed the problems of heterogeneity and dynamic adaptability. On the other hand, middleware solutions, like CORBA and Java/Jini, solve part of the heterogeneity problem by permitting seamless communication among different platforms. But, they do not address dynamic resource management and adaptability for applications requiring high-performance distributed computing. this paper presents 2K, an integrated operating system architecture that addresses the problems of resource management in heterogeneous networks, dynamic adaptability, and configuration of component-based distributed applications.

关键词： computer architecture computer science Distributed computing Environmental management Explosives Middleware Operating systems Portals Power system management Resource management

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MDACCER: Modified Distributed Assessment of the Closeness CEntrality Ranking in Complex Networks for Massively Parallel Environments 27

MDACCER: Modified Distributed Assessment of the Closeness CE...

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IEEE 27th International symposium on computer architecture and high performance computing

作者： Cabral, Frederico Luis Osthoff, Carla Ramos, Daniel Nardes, Rafael LNCC Ctr Comp Alto Desempenho Petropolis RJ Brazil

ISBN: (纸本)9781467386210

We propose a new method derived from DACCER (Distributed Assessment of the Closeness CEntrality Ranking): the modified DACCER (MDACCER), for assessing traditional closeness centrality ranking. MDACCER presents a relaxation that allows it to take advantage of massively parallel environments like General Purpose Graphics Processing Units (GPGPUs). Traditional DACCER proposal assesses Closeness centrality ranking in a limited neighborhood using only information around each node at low computational cost and capability to be executed in a distributed environment. Despite all the advantages, DACCER presents some difficulties in GPGPUs programming model that increases its computational cost at this particular environment. In contrast to the poor performance of DACCER on GPGPUs, experimental results demonstrate MDACCER is as simple and efficient as DACCER to assess Closeness centrality ranking in complex networks and moreover it does not have the same bottlenecks in GPGPUs computing about memory usage and time complexity. We performed MDACCER for some synthetically generated networks, specifically Barabasi-Albert ones and results indicate MADCCER correlates Closeness centrality ranking almost as well as DACCER does with lower computational costs.

关键词： Parallel computing Network Centrality Ranking DACCER Closeness GPU CUDA

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ASADI: Accelerating Sparse Attention using Diagonal-based In-situ computing 30

ASADI: Accelerating Sparse Attention using Diagonal-based In...

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30th IEEE International symposium on high-performance computer architecture (HPCA)

作者： Li, Huize Li, Zhaoying Bai, Zhenyu Mitra, Tulika Natl Univ Singapore Sch Comp Singapore Singapore

ISBN: (纸本)9798350393132;9798350393149

the self-attention mechanism is the performance bottleneck of Transformer-based language models, particularly for long sequences. Researchers have proposed using sparse attention to speed up the Transformer. However, sparse attention introduces significant random access overhead, limiting computational efficiency. To mitigate this issue, researchers attempt to improve data reuse by utilizing row/column locality. Unfortunately, we find that sparse attention does not naturally exhibit strong row/column locality, but instead has excellent diagonal locality. thus, it is worthwhile to use diagonal compression (DIA) format. However, existing sparse matrix computation paradigms struggle to efficiently support DIA format in attention computation. To address this problem, we propose ASADI, a novel softwarehardware co-designed sparse attention accelerator. In the software side, we propose a new sparse matrix computation paradigm that directly supports the DIA format in self-attention computation. In the hardware side, we present a novel sparse attention accelerator that efficiently implements our computation paradigm using highly parallel in-situ computing. We thoroughly evaluate ASADI across various models and datasets. Our experimental results demonstrate an average performance improvement of 18.6x and energy savings of 2.9x compared to a PIM-based baseline.

关键词： diagonal compression format processing-in-memory sparse attention

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Service Deployment in Cloud 16

Service Deployment in Cloud

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16th IEEE International Conference on high performance computing and Communications HPCC 2014\11th IEEE International Conference on Embedded Software and Systems ICESS 2014\6th International symposium on Cyberspace Safety and Security CSS 2014

作者： Haji, Amel Ben Letaifa, Asma Tabbane, Sami SUPCOM Mediatron Lab Higher Sch Commun Tunis Tunis Tunisia

ISBN: (纸本)9781479961238

Among the many limitations that the clouds are facing today, the heterogeneity of IT resources and networks. the dynamic deployment and on-demand applications are also major challenges. To ensure this deployment, it is essential to rely on methods of managing applications and services in a cloud. this paper proposes to apply the concept of Virtual Appliance for cloud architectures to ensure the dynamic deployment, interoperability and reuse of services supported by these clouds. Proposed architecture aims to solve problems of users whose are blocked from sellers with very little flexibility to move their services to other providers. Using standards of DMTF could provide more flexibility and response to user's requirement under SLA constraints.

关键词： Cloud computing Cloud federation OVF Virtual Appliance Service Deployment

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performance Analysis with high-Level Languages for high-performance Reconfigurable computing

Performance Analysis with High-Level Languages for High-Perf...

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16th Annual IEEE symposium on Field-Programmable Custom computing Machines

作者： Curreri, John Koehler, Seth Holland, Brian George, Alan D. Univ Florida NSF Ctr High Performance Reconfigurable Comp ECE Dept Gainesville FL 32611 USA

ISBN: (纸本)9780769533070

high-Level Languages (HLLS) for FPGAs (Field-Programmable Gate Arrays) facilitate the use of reconfigurable computing resources for application developers by using familiar, higher-level syntax, semantics, and abstractions, typically enabling faster development times than with traditional Hardware Description Languages (HDLs). However, this abstraction is typically accompanied by some loss of performance as well as reduced transparency of application behavior, making it difficult to understand and improve application performance. While runtime tools for performance analysis are often featured in development with traditional HLLS for serial and parallel programming, HLL-based applications for FPGAs have an equal or greater need yet lack these tool. this presents a novel and portable framework for runtime performance analysis of HLL applications for FPGAs, including a prototype tool for performance analysis with Impulse C, a commerical HLL for FPGAs. As a case study, this tool is used to locate performance bottlenecks in a molecular dynamics applications.

关键词： performance analysis profile trace reconfigurable computing FPGA high-level language application mapper Impulse C Carte

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high-performance extendable instruction set computing 6

High-performance extendable instruction set computing

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6th Australasian computer Systems architecture Conference (ACSAC 2001)

作者： Lee, H Beckett, P Appelbe, B Asia Design Corporation Australia RMIT University Australia

ISBN: (纸本)0769509541

In this paper, a new architecture called the extendable instruction set computer (EISC) is introduced that addresses the issues of memory size and performance in embedded microprocessor systems. the architecture exhibits an efficient fixed length 16-bit instruction set with short length offset and immediate operands. the offset and immediate operands can be extended to 32 bits via the operation of an extension flag. the code density of the EISC instruction set and its memory transfer performance is shown to be significantly higher than current architectures making it a suitable candidate for the next generation of embedded computer systems. the compact EISC instruction set introduces data dependencies that seemingly limit deep pipeline and superscalar implementations. this paper suggests a mechanism by which these dependencies might be removed in hardware.

关键词： Bandwidth Central Processing Unit Circuits computer aided instruction computer architecture Embedded computing Microprocessors Personal digital assistants Pipelines Random access memory

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Supporting Secure Multi-GPU computing with Dynamic and Batched Metadata Management 30

Supporting Secure Multi-GPU Computing with Dynamic and Batch...

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30th IEEE International symposium on high-performance computer architecture (HPCA)

作者： Na, Seonjin Kim, Jungwoo Lee, Sunho Huh, Jaehyuk Georgia Inst Technol Atlanta GA 30332 USA Korea Adv Inst Sci & Technol Seoul South Korea

ISBN: (纸本)9798350393132;9798350393149

With growing problem sizes for GPU computing, multi-GPU systems with fine-grained memory sharing have emerged to improve the current coarse-grained unified memory support based on page migration. Such multi-GPU systems with shared memory pose a new challenge in securing CPUGPU and inter-GPU communications, as the cost of secure data transfers adds a significant performance overhead. there are two overheads of secure communication in multi-GPU systems: First, extra overhead is added to generate one-time pads (OTPs) for authenticated encryption. Second, the security metadata such as MACs and counters passed along with encrypted data consume precious network bandwidth. this study investigates the performance impact of secure communication in multi-GPU systems and evaluates the prior CPU-oriented OTP precomputation schemes adapted for multi-GPU systems. Our investigation identifies the challenge with the limited OTP buffers for interGPU communication and the opportunity to reduce traffic for security meta-data with bursty communications in GPUs. Based on the analysis, this paper proposes a new dynamic OTP buffer allocation technique, which adjusts the buffer assignment for each source-destination pair to reflect the communication patterns. To address the bandwidth problem by extra security metadata, the study employs a dynamic batching scheme to transfer only a single set of metadata for each batched group of data responses. the proposed design constantly tracks the communication pattern from each GPU, periodically adjusts the allocated buffer size, and dynamically forms batches of data transfers. Our evaluation shows that in a 16-GPU system, the proposed scheme can improve the performance by 13.2% and 17.5% on average from the prior cached and private schemes, respectively.

关键词： Graphics processing unit

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Application Defined On-chip Networks for Heterogeneous Chiplets: An Implementation Perspective 28

Application Defined On-chip Networks for Heterogeneous Chipl...

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28th Annual IEEE International symposium on high-performance computer architecture (HPCA)

作者： Wang, Tianqi Feng, Fan Xiang, Shaolin Li, Qi Xia, Jing Huawei Shenzhen Peoples R China

ISBN: (纸本)9781665420273

With the help of advanced packaging technologies to integrate multiple chips (e.g., CPU, AI, IO), a chiplet-based SoC design process can enable fast system construction. However, the design of network-on-chip used within the individual chiplets and across chiplets is an extremly challenge. We introduce the design process and methodology of a bufferless multi-ring NoC for heterogeneous chiplet-based SoC. Our design is portable and can be used in diverse scenarios, like Server-CPU, AI-Processor, and Baseband-Processor. the co-design of the application, architecture, and implementation is the key to make the system power efficient and high performance. We determined many architectural design choices by reflecting an analysis of a set of target applications by application teams and several physical implementation constraints provided by development teams. In this paper, we present the pragmatic practice of our co-design effort for the NoC. As a result, the system has been proven to achieve 16TB/s bandwidth in an AI processor and low latency, in a server CPU with nearly one hundred cores.

关键词： Design methodology computer architecture Bandwidth Network-on-chip Packaging Energy efficiency Servers

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Leveraging optimization methods for dynamically assisted control-flow integrity mechanisms 26

Leveraging optimization methods for dynamically assisted con...

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26th International symposium on computer architecture and high performance computing, SBAC-PAD 2014

作者： Moreira, João Teixeira, Lucas Borin, Edson Rigo, Sandro Institute of Computing University of Campinas São Paulo Brazil

ISBN: (纸本)9781479969043

Dynamic Binary Modification (DBM) tools are useful for cross-platform execution of binaries and are powerful run time environments that allow execution optimizations, instrumentation and profiling. these tools have also been used as enablers for control-flow integrity verification, a process that consists in the observation and analysis of a program's execution path focusing on the detection of anomalies, such as those arising from flow corruption based software attacks. Even though this class of tools helps us in identifying a myriad of attacks, it is typically expensive at run time and introduce significant overhead to the program execution. Considering their inherent high cost, further expanding the capabilities of such tools for detection of program flow anomalies can slow down the analysis to the point that it is unfeasible to run it in real world workflows. In this paper we present a mechanism for including program flow verification in DBMs that uses asynchronous analysis and applies different parallel-programming techniques that leverage current multi-core systems to control the overhead of our analysis. Our mechanism was tested against synthetic program flow corruption use cases and correctly detected all detours. With our new optimizations, we show that our system achieves an slowdown of only 1.46x, while a naively implemented verification system face 4.22x of overhead. © 2014 IEEE.

关键词： Parallel programming

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