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Optimizing a calibration software for radio astronomy 16

Optimizing a calibration software for radio astronomy

引用

16th IEEE Int Conf on high performance computing and Communications/11th IEEE Int Conf on Embedded Software and Systems\6th Int symposium on Cyberspace Safety and Security

作者： Madougou, Souley Varbanescu, Ana L. van Nieuwpoort, Rob Univ Amsterdam IvI Amsterdam Netherlands Netherlands eSci Ctr Amsterdam Netherlands

ISBN: (纸本)9781479961238

With the turn to multicore in chip design and manufacturing, both consumer and high performance applications can benefit from ubiquitous hardware parallelism. However, the performance improvement to be achieved is not always in the orders of magnitude range. In this paper, we present the challenging example of designing a parallel version of a model fitting algorithm used in calibrating telescope observation data in radio astronomy. the complexity of the application, together with the limited opportunities for code modification, bound the performance gain that any parallel system could achieve. However, we show how classical bound-and-bottleneck analysis and optimization using multicore architectures help achieving up to 2.3x "wallclock" speedup compared to the original sequential implementation. We further discuss the reasons for this limitation, and suggest possible solutions to address it.

关键词： code optimization model fitting multicore architecture parallel computing radio astronomy radio astronomy code optimization mode matching PARALLEL PROCESSING (computerS) Multi-core processors chip scale packaging parallel system

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FPGA-Based Computational Fluid Dynamics Simulation architecture via high-Level Synthesis Design Method 16th

FPGA-Based Computational Fluid Dynamics Simulation Architect...

引用

16th International symposium on Applied Reconfigurable computing

作者： Du, Changdao Firmansyah, Iman Yamaguchi, Yoshiki Univ Tsukuba Tsukuba Ibaraki 3058577 Japan

ISBN: (纸本)9783030445331;9783030445348

Today's high-performance computing (HPC) systems often use GPUs as dedicated hardware accelerators to meet the computation requirements of applications such as neural networks, genetic decoding, and hydrodynamic simulations. Meanwhile, FPGAs have also been considered as alternative suitable hardware accelerators due to their advancing computational capabilities and low power consumption. Moreover, the developments of high-Level Synthesis (HLS) allow users to generate FPGA designs directly from mainstream languages, e.g., C, C++, and OpenCL. However, writing efficient high-level programs with good performance is still a time-consuming task, and the lack of knowledge about FPGA architecture can lead to poor scalability and portability. In this paper, we propose an architecture design for Computational Fluid Dynamics (CFD) simulations based on the HLS method. Our design can adjust the performance by utilizing the parallelism inside both temporal and spatial domains of CFD simulations. We also discuss the data reuse buffer optimization choices while considering the potability of HLS codes. A performance model is introduced to guide the design space exploration under the constraints of available resources on FPGA. We evaluate our design via a Xilinx VCU1525 FPGA board and compare the results with other state-of-the-art studies. Experiment results show that VCU1525 can achieve 629.6 GFLOP/s in D2Q9 LBM-BGK model and the design and optimization methods can be used for developing various CFD applications.

关键词： HPC FPGA HLS CFD

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CAT: A high performance, distributed component architecture toolkit for the Grid

CAT: A high performance, distributed component architecture ...

引用

proceedings of the 1999 8th IEEE International symposium on high performance Distributed computing - HPDC-8

作者： Villacis, Juan Govindaraju, Madhusudhan Stern, David Whitaker, Andrew Breg, Fabian Deuskar, Prafulla Temko, Benjamin Gannon, Dennis Bramley, Randall Indiana Univ Bloomington United States

Taking advantage of the Grid for high-performance scientific computing requires a software framework layered above the Grid that supports a new style of programming, component-based programming. the component architecture toolkit (CAT) facilitates such programming by providing a conceptually simple `port-based' component model together with a suite of developer tools for incorporating existing scientific codes into the framework, as well as a set of end user tools for locating, composing, building and running distributed component application over the Grid.

关键词： Distributed computer systems

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A split&merge data management architecture for a grid environment

A split&merge data management architecture for a grid enviro...

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19th IEEE symposium on computer-Based Medical Systems

作者： Aloisio, Giovanni Cafaro, Massimo Fiore, Sandro Mirto, Maria Univ Lecce CACT ISUFI Via Arnesano I-73100 Lecce Italy Univ Lecce NNL INFM I-73100 Lecce Italy Univ Lecce CNR I-73100 Lecce Italy

ISBN: (纸本)0769525172

Currently several applications produce huge amount of data making them available for post-processing operations in order to infer new knowledge. Main issues of these applications are the need for efficient mechanisms to access data and high performance computing to obtain the results in an acceptable time. Wrapping the applications as Web Services allows interoperability with others tools and in particular with Grid computing environments exploiting a large set of resources through a standard interface, to support the requirements of so-called "data intensive" applications that handle large amounts of data. this paper presents the architecture of a complex data managements system leveraging the grid computing paradigm, exploiting existing middleware developed at the University of Lecce within the ProGenGrid, GRelC and GRB projects to support high throughput applications. this architecture has been specialized for a bioinformatics domain and a case study of the use of a biological application will be also described.

关键词： Data Management Grid computing Computational Grid Web Services BLAST

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Exploring the Serverless First Strategy in Cloud Application Development 35

Exploring the Serverless First Strategy in Cloud Application...

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35th IEEE International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Cavalheiro, Adriano Prado Schepke, Claudio Fed Univ Pampa Alegrete PPGES Grad Program Software Engn Alegrete Brazil

ISBN: (纸本)9798350381603

this paper explores the Serverless First strategy in cloud application development. Serverless computing has gained popularity due to its flexibility and scalability. In our work, we provide a systematic review of the literature about the Serverless paradigm in cloud computing and an evaluation of the advantages of this approach by performing a comparative analysis among three ways for the implementation of an application: AWS Lambda, AWS Lambda with Chalice framework, and the traditional form using the Flask framework. the literature review results show the gains in scaling, cost reduction, and ease of maintenance achieved with the Serverless First strategy. However, some limitations and challenges were also highlighted, such as the greater complexity of the environment, less control over resources, resource limitations imposed by the cloud provider, and difficulties in debugging and managing the infrastructure. the case study demonstrates in practice that the Chalice framework provided the most straightforward and rapid implementation, the AWS Lambda without Chalice offered greater flexibility and control, and the Flask version allowed local testing and total control but required more manual setup and lacked automatic scalability.

关键词： Serverless First Function as a Service Serverless computing Serverless architecture Serverless Applications Software Development Cloud computing Cloud Services

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SmarCo: An Efficient Many-Core Processor for high-throughput Applications in Datacenters 24

SmarCo: An Efficient Many-Core Processor for High-Throughput...

引用

24th IEEE International symposium on high performance computer architecture (HPCA)

作者： Fan, Dongrui Li, Wenming Ye, Xiaochun Wang, Da Zhang, Hao Tang, Zhimin Sun, Ninghui Chinese Acad Sci ICT SKL Comp Architecture Beijing Peoples R China Univ Chinese Acad Sci Sch Comp & Control Engn Beijing Peoples R China SmarCo Co Ltd Beijing Peoples R China

ISBN: (纸本)9781538636596

Fast-growing high-throughput applications, such as web services, are characterized by high-concurrency processing, hard real-time response, and high-bandwidth memory access. the newly-born applications bring severe challenges to processors in datacenters, both in concurrent processing performance and energy efficiency. To offer a satisfactory quality of services, it is of critical importance to meet these newly emerging demands of high-throughput applications in the future datacenters in a more efficient way. In this paper, we propose a novel architecture, called SmarCo, which allows high-throughput applications to be processed more efficiently in datacenters. Based on the dominant characteristics of high-throughput applications, we implement large-scale many-core architecture with in-pair threads to support high-concurrency processing;we also introduce a hierarchical ring topology and laxity-aware task scheduler to guarantee hard real-time response;furthermore, we propose high-throughput datapath to improve memory access efficiency. We verify the efficiency of SmarCo by using simulators, large-scale FPGA and prototype with TSMC 40-nm technology node. the experimental results show that, compared to Intel Xeon E7-8890V4, SmarCo achieves 10.11X performance improvement and 6.95X energy-efficiency improvement with higher throughput and a better guarantee of real-time response.

关键词： Instruction sets Task analysis Indexes Real-time systems Memory management throughput

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Unlimited Vector Extension with Data Streaming Support 21

Unlimited Vector Extension with Data Streaming Support

引用

ACM/IEEE 48th Annual International symposium on computer architecture (ISCA)

作者： Domingos, Joao Mario Neves, Nuno Roma, Nuno Tomas, Pedro Univ Lisbon Inst Super Tecn INESC ID Lisbon Portugal INESC ID Inst Telecomunicacoes Lisbon Portugal

ISBN: (纸本)9781665433334

Unlimited vector extension (UVE) is a novel instruction set architecture extension that takes streaming and SIMD processing together into the modern computing scenario. It aims to overcome the shortcomings of state-of-the-art scalable vector extensions by adding data streaming as a way to simultaneously reduce the overheads associated with loop control and memory access indexing, as well as with memory access latency. this is achieved through a new set of instructions that pre-configure the loop memory access patterns. these attain accurate and timely data prefetching on predictable access patterns, such as in multidimensional arrays or in indirect memory access patterns. Each of the configured data streams is associated to a general-purpose vector register, which is then used to interface with the streams. In particular, iterating over a given stream is simply achieved by reading/writing to the corresponding input/output stream, as the data is instantly consumed/produced. To evaluate the proposed UVE, a proof-of-concept gem5 implementation was integrated in an out-of-order processor model, based on the ARM Cortex-A76, thus taking into consideration the typical speculative and out-of-order execution paradigms found in high-performance computing processors. the evaluation was carried out with a set of representative kernels, by assessing the number of executed instructions, its impact on the memory bus and its overall performance. Compared to other state-of-the-art solutions, such as the upcoming ARM Scalable Vector Extension (SVE), the obtained results show that the proposed extension attains average performance speedups over 2.4x for the same processor configuration, including vector length.

关键词： Scalable SIMD/Vector Processing Data Streaming Instruction Set Extension Processor Microarchitecture high-performance computing

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Modeling a reconfigurable system for computing the FFT in place via rewriting-logic 16

Modeling a reconfigurable system for computing the FFT in pl...

引用

16th symposium on Integrated Circuits and Systems Design

作者： Ayala-Rincón, M Nogueira, RB Llanos, CH Jacobi, RP Hartenstein, RW Univ Brasilia Dept Matemat BR-70910900 Brasilia DF Brazil

ISBN: (纸本)076952009X

the growing adoption of reconfigurable architectures opens new implementation alternatives and creates new design challenges. In the case of dynamically reconfigurable architectures, the choice of an efficient architecture and reconfiguration scheme for a given application is a complex task. Tools for exploration of design alternatives at higher abstraction levels are needed. this paper describes the modeling and simulation of a dynamically reconfigurable hardware implementation of the Fast Fourier Transform - FFT using rewriting-logic. It is shown that rewriting-logic can be used as a framework for fast design space exploration, providing a quick evaluation of different reconfigurable solutions.

关键词： Application specific integrated circuits Brazil Council Circuit simulation Computational modeling computer architecture Costs Field programmable gate arrays Hardware Reconfigurable architectures Signal processing algorithms

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FLIPBIT: Approximate Flash Memory for IoT Devices 30

FLIPBIT: Approximate Flash Memory for IoT Devices

引用

30th IEEE International symposium on high-performance computer architecture (HPCA)

作者： Buck, Alexander Ganesan, Karthik Jerger, Natalie Enright Univ Toronto Toronto ON Canada

ISBN: (纸本)9798350393132;9798350393149

IoT devices commonly use flash memory for both data and code storage. Flash memory consumes a significant portion of the overall energy of such devices. this is problematic because IoT devices are energy constrained due to their reliance on batteries or energy harvesting. To save energy, we leverage a unique property of flash memory;write operations take unequal amounts of energy depending on if we are flipping a 1. 0 versus a 0. 1. We exploit this asymmetry to reduce energy consumption with FLIPBIT, a hardware-software approximation approach that limits costly 0. 1 transitions in flash. Instead of performing an exact write, we write an approximated value that avoids any costly 0. 1 bit flips. Using FLIPBIT, we reduce the mean energy used by flash by 68% on video streaming applications while maintaining 42 dB PSNR. On machine learning models, we reduce energy by an average of 39% and up to 71% with only a 1% accuracy loss. Additionally, by reducing the number of program-erase cycles, we increase the flash lifetime by 68%.

关键词： Approximate computing Internet-of-things Non-volatile memory

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Beyond the "device as portal": Meeting the requirements of wireless and mobile devices in the legion grid computing system 16

Beyond the "device as portal": Meeting the requirements of w...

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16th International Parallel and Distributed Processing symposium, IPDPS 2002

作者： Clarke, B. Humphrey, M. Department of Computer Science University of Virginia CharlottesvilleVA22903 United States

ISBN: (纸本)0769515738

Grid computing is an emerging paradigm in which resources in multiple organizations are combined into a single, seamless computing environment. As the storage, processing, and networking capabilities of wireless and mobile devices continue to expand, there will soon be the ability to use such devices as first-class compute- and data-servers (albeit for restricted problem sizes). However, without the proper software architecture for Grid computing, such devices will continue to be only usable as Web portals to high-power backend servers. this paper describes the unique capabilities of the Legion Grid computing infrastructure that will directly support these next-generation, poweful devices as first-class entities. © 2002 IEEE.

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