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MDACCER: Modified Distributed Assessment of the Closeness CEntrality Ranking in Complex Networks for Massively Parallel Environments 27

MDACCER: Modified Distributed Assessment of the Closeness CE...

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IEEE 27th International symposium on computer architecture and high performance computing

作者： Cabral, Frederico Luis Osthoff, Carla Ramos, Daniel Nardes, Rafael LNCC Ctr Comp Alto Desempenho Petropolis RJ Brazil

ISBN: (纸本)9781467386210

We propose a new method derived from DACCER (Distributed Assessment of the Closeness CEntrality Ranking): the modified DACCER (MDACCER), for assessing traditional closeness centrality ranking. MDACCER presents a relaxation that allows it to take advantage of massively parallel environments like General Purpose Graphics Processing Units (GPGPUs). Traditional DACCER proposal assesses Closeness centrality ranking in a limited neighborhood using only information around each node at low computational cost and capability to be executed in a distributed environment. Despite all the advantages, DACCER presents some difficulties in GPGPUs programming model that increases its computational cost at this particular environment. In contrast to the poor performance of DACCER on GPGPUs, experimental results demonstrate MDACCER is as simple and efficient as DACCER to assess Closeness centrality ranking in complex networks and moreover it does not have the same bottlenecks in GPGPUs computing about memory usage and time complexity. We performed MDACCER for some synthetically generated networks, specifically Barabasi-Albert ones and results indicate MADCCER correlates Closeness centrality ranking almost as well as DACCER does with lower computational costs.

关键词： Parallel computing Network Centrality Ranking DACCER Closeness GPU CUDA

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Energy-efficient online resource provisioning for cloud-edge platforms via multi-armed bandits 34

Energy-efficient online resource provisioning for cloud-edge...

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34th IEEE International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Rey-Jouanchicot, Jordan del Castillo, Juan Angel Lorenzo Zuckerman, Stephane Veronica Belmega, E. CY Cergy Paris Univ CY Tech Cergy France CY Cergy Paris Univ ETIS UMR 8051 ENSEA CNRS F-95000 Cergy France Univ Gustave Eiffel CNRS LIGM F-77454 Marne La Vallee France

ISBN: (数字)9781665451574

ISBN: (纸本)9781665451574

Edge computing is a new paradigm in which data are locally collected, aggregated and preprocessed before being sent to a Cloud platform. Edge devices, typically IoT objects, are characterized by limited computational capabilities, alongside high energy efficiency operations. In smart building or smart city applications, the overall amount of available IoT devices may account for an important computational capacity. Aggregating the idle CPU cycles of several devices would allow performing on-site parallel and distributed computing, while reusing the available resources in the network. Timely and important computational tasks such as video surveillance processing, HPC jobs, or deep neural network training, can be performed with local available resources. this includes local servers or a private, on-site cloud, as opposed to the use of public clouds, thus avoiding security issues and fostering energy efficiency. An ongoing research topic in such a distributed and volatile context is to design novel algorithms for resource provisioning that allow tasks to be distributed over a set of available IoT devices in an efficient manner. this work presents two online, adaptive and robust scheduling techniques, based on the UCB and EXP3 Multi-Armed Bandit algorithms (MABs), for resource management in Cloud-Edge computing based environments while improving performance and reducing energy consumption. the novelty of our adapted algorithms lies in the fact that we explicitly account for unavailable computing IoT devices resulting in a time-varying available set of arms at each stage. Our numerical results show the high relevance of our approach in reaching optimal provisioning policies in time-varying environments.

关键词： Cloud Edge computing resource provisioning online learning multi-armed bandits

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Bypass: A tool for building split execution systems 9

Bypass: A tool for building split execution systems

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9th IEEE International symposium on high performance Distributed computing

作者： thain, D Livny, M Univ Wisconsin Dept Comp Sci Madison WI 53703 USA

ISBN: (纸本)0769507832;0769507840

Split execution is a common model for providing a friendly environment on a foreign machine. In this model, a remotely executing process sends some or all of its system calls back to a home environment for execution. Unfortunately, hand-coding split execution system for experimentation and research is difficult and error-prone. We have built a tool, Bypass, for quickly producing portable and correct split execution systems for unmodified legacy applications. We demonstrate Bypass by using it to transparently connect a POSIX application to a simple data staging system based on the Globus toolkit.

关键词： Application software Buildings computer architecture Databases Kernel Libraries Machine vision Operating systems Programming profession Routing

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Reliability Evaluation of Mixed-Precision architectures 25

Reliability Evaluation of Mixed-Precision Architectures

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25th IEEE International symposium on high performance computer architecture (HPCA)

作者： dos Santos, Fernando Fernandes Lunardi, Caio Oliveira, Daniel Libano, Fabiano Rech, Paolo Univ Fed Rio Grande do Sul Inst Informat Porto Alegre RS Brazil

ISBN: (纸本)9781728114446

Novel computing architectures offer the possibility to execute float point operations with different precisions. the execution of reduced precision operationsis likely to reduce both the execution time and power consumption. However, the application's error rate and the device's reliability can also be impacted by these precision changes. In this paper, we study the impact of data and operation precision changes on the reliability of modern architectures. We consider Xilinx Field-Programmable Gate-Arrays (FPGA), Intel Xeon Phis, and NVIDIA Graphics Processing Units (GPUs) executing a set of codes implemented in double, single, and half-precision IEEE754-compliant float point data. On FPGAs, the reduced area and performance improvements brought by reduced precision operations increase reliability. On Xeon Phis the compiler biases significantly double- and single-precision instructions execution. this raises the drawback of increasing single-precision error rates when compared to double-precision. NVIDIA GPUs make use of dedicated mixed-precision cores, which draw nontrivial effects on the device reliability. In general, on GPUs half-precision allows a higher number of executions to be correctly completed before experimenting a failure. Finally, we also evaluate how transient faults impact the output correctness. Our study shows that for most applications faults in a single or half-precision data or operation are more likely to significantly modify the output value than errors in double-precision data.

关键词： computer architecture

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Leveraging optimization methods for dynamically assisted control-flow integrity mechanisms 26

Leveraging optimization methods for dynamically assisted con...

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26th International symposium on computer architecture and high performance computing, SBAC-PAD 2014

作者： Moreira, João Teixeira, Lucas Borin, Edson Rigo, Sandro Institute of Computing University of Campinas São Paulo Brazil

ISBN: (纸本)9781479969043

Dynamic Binary Modification (DBM) tools are useful for cross-platform execution of binaries and are powerful run time environments that allow execution optimizations, instrumentation and profiling. these tools have also been used as enablers for control-flow integrity verification, a process that consists in the observation and analysis of a program's execution path focusing on the detection of anomalies, such as those arising from flow corruption based software attacks. Even though this class of tools helps us in identifying a myriad of attacks, it is typically expensive at run time and introduce significant overhead to the program execution. Considering their inherent high cost, further expanding the capabilities of such tools for detection of program flow anomalies can slow down the analysis to the point that it is unfeasible to run it in real world workflows. In this paper we present a mechanism for including program flow verification in DBMs that uses asynchronous analysis and applies different parallel-programming techniques that leverage current multi-core systems to control the overhead of our analysis. Our mechanism was tested against synthetic program flow corruption use cases and correctly detected all detours. With our new optimizations, we show that our system achieves an slowdown of only 1.46x, while a naively implemented verification system face 4.22x of overhead. © 2014 IEEE.

关键词： Parallel programming

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SIMP (Single Instruction stream/Multiple instruction Pipelining): a novel high-speed single-processor architecture. 89

SIMP (Single Instruction stream/Multiple instruction Pipelin...

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16th Annual International symposium on computer architecture

作者： Murakami, Kazuaki Irie, Naohiko Kuga, Morihiro Tomita, Shinji Kyushu Univ Fukuoka Jpn

ISBN: (纸本)9780897913195

SIMP is a novel multiple-instruction-pipeline parallel architecture. It enhances the performance of SISD (single-instruction/single-data-stream) processors by using both temporal and spatial parallelisms, while keeping program compatibility. the degree of performance enhancement achieved by SIMP depends on determining how to supply multiple instructions continuously and how to resolve data and control dependencies effectively. Techniques for instruction fetch and dependency resolution have been devised for this purpose. the instruction-fetch mechanism utilizes unique schemes for prefetching multiple instructions with the help of branch prediction, squashing instructions selectively, and providing multiple conditional modes as a result. the dependency-resolution mechanism permits out-of-order execution of sequential instruction stream. the out-of-order execution model is based on R.M. Tomasulo's algorithm (1967), which has been used in single instruction-pipeline processors. However, it is greatly extended to accommodate multiple-instruction pipelining.

关键词： computer systems, Digital

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Power Consumption Analysis of Parallel Algorithms on GPUs 16

Power Consumption Analysis of Parallel Algorithms on GPUs

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16th IEEE Int Conf on high performance computing and Communications/11th IEEE Int Conf on Embedded Software and Systems\6th Int symposium on Cyberspace Safety and Security

作者： Magoules, Frederic Ahamed, Abal-Kassim Cheik Desmaison, Alban Lechenet, Jean-Christophe Mayer, Francois Ben Salem, Haifa Zhu, thomas Ecole Cent Paris CUDA Res Ctr Paris France

ISBN: (纸本)9781479961238

Due to their highly parallel multi-cores architecture, GPUs are being increasingly used in a wide range of computationally intensive applications. Compared to CPUs, GPUs can achieve higher performances at accelerating the programs' execution in an energy-efficient way. therefore GPGPU computing is useful for high performance computing applications and in many scientific research fields. In order to bring further performance improvements, GPU clusters are increasingly adopted. the energy consumed by GPUs cannot be neglected. therefore, an energy-efficient time scheduling of the programs that are going to be executed by the parallel GPUs based on their deadline as well as the assigned priorities could be deployed to face their energetic avidity. For this reason, we present in this paper a model enabling the measure of the power consumption and the time execution of some elementary operations running on a single GPU using a new developed energy measurement protocol. Consequently, using our methodology, energy needs of a program could be predicted, allowing a better task scheduling.

关键词： Energy Measuring Device Energy Consumption Green computing Linear Algebra Operation Prediction Algorithm Task Scheduling Algorithm GPU Parallel computing Gravity equation

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RECAP: A Region-Based Cure for the Common Cold (Cache)

RECAP: A Region-Based Cure for the Common Cold (Cache)

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19th IEEE International symposium on high performance computer architecture (HPCA)

作者： Zebchuk, Jason Cain, Harold W. Tong, Xin Srinivasan, Vijayalakshmi Moshovos, Andreas Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 1A1 Canada

ISBN: (纸本)9781467355872

Virtualization has become a magic bullet to increase utilization, improve security, lower costs, and reduce management overheads. In many scenarios, the number of virtual machines consolidated onto a single processor has grown even faster than the number of hardware threads. this results in multiprogrammed virtualization where many virtual machines time-share a single processor core. Such fine-grain sharing comes at a cost;each time a virtual machine gets scheduled by the hypervisor, it effectively begins with a "cold" cache, since any cache blocks it accessed in the past have likely been evicted by other virtual machines. Recently, cache restoration prefetchers have been shown to reduce the cold cache effects caused by multiprogrammed virtualization. However, these prefetchers waste large amounts of bandwidth prefetching many useless blocks and writing and reading metadata to and from memory. Using block reuse based filtering, we enhance two existing cache restoration prefetchers and reduce their bandwidth overheads by 16% and 32%, with slowdowns of only 0.5% and 0.6%. We also propose a Region-Based Cache Restoration Prefetcher (RECAP), which groups cache blocks into coarse-grain regions of memory, and predicts which regions contain useful blocks to prefetch the next time the current virtual machine executes. Based on these predictions, and using a simple compression technique that exploits spatial locality, RECAP provides a robust prefetcher that improves performance by up to 42% for some applications and only uses 14% more bandwidth and 3.5% more power than a stride prefetcher, on average. Compared to other prefetchers designed for multiprogrammed virtualization, RECAP provides comparable performance while using an average of 12% to 27% less bandwidth, and reducing the energy-delay product of the L2 cache and main memory by 12% to 13% on average.

关键词： cache storage data compression multiprogramming power aware computing processor scheduling supervisory programs virtual machines virtualisation

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Self-adaptive arallel rocessing architecture for high-speed networking 16

Self-adaptive arallel rocessing architecture for high-speed ...

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16th Annual International symposium on high performance computing Systems and Applications, HPCS 2002

作者： Foag, Jürgen Pazos, Nuria Wild, thomas Brunnbauer, Winthir Inst. for Integrated Circuits Techn. University of Munich Bavaria Munich80290 Germany Infineon Technologies San JoseCA United States

ISBN: (纸本)0769516262

this article describes a packet processing methodology, which executes the required protocol layer functions of a networking device in parallel. Based on the dynamic prediction of the inherent protocol-stack of receiving packets, the data dependency of the layers is speculatively resolved and the functions are processed. Consequently, packet processing latency can be minimized and end-to-end transmission delays can be optimized without sacrificing flexibility in the supported networking protocols and applications. Utilizing the self-adaptive processing methodology, presented in this paper, transmission systems may realize a mean system processing time reduction and consequently a transmission rate increase of up to 40 percent dependent on the quality of the prediction. © 2002 IEEE.

关键词： Internet protocols

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Supporting Secure Multi-GPU computing with Dynamic and Batched Metadata Management 30

Supporting Secure Multi-GPU Computing with Dynamic and Batch...

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30th IEEE International symposium on high-performance computer architecture (HPCA)

作者： Na, Seonjin Kim, Jungwoo Lee, Sunho Huh, Jaehyuk Georgia Inst Technol Atlanta GA 30332 USA Korea Adv Inst Sci & Technol Seoul South Korea

ISBN: (纸本)9798350393132;9798350393149

With growing problem sizes for GPU computing, multi-GPU systems with fine-grained memory sharing have emerged to improve the current coarse-grained unified memory support based on page migration. Such multi-GPU systems with shared memory pose a new challenge in securing CPUGPU and inter-GPU communications, as the cost of secure data transfers adds a significant performance overhead. there are two overheads of secure communication in multi-GPU systems: First, extra overhead is added to generate one-time pads (OTPs) for authenticated encryption. Second, the security metadata such as MACs and counters passed along with encrypted data consume precious network bandwidth. this study investigates the performance impact of secure communication in multi-GPU systems and evaluates the prior CPU-oriented OTP precomputation schemes adapted for multi-GPU systems. Our investigation identifies the challenge with the limited OTP buffers for interGPU communication and the opportunity to reduce traffic for security meta-data with bursty communications in GPUs. Based on the analysis, this paper proposes a new dynamic OTP buffer allocation technique, which adjusts the buffer assignment for each source-destination pair to reflect the communication patterns. To address the bandwidth problem by extra security metadata, the study employs a dynamic batching scheme to transfer only a single set of metadata for each batched group of data responses. the proposed design constantly tracks the communication pattern from each GPU, periodically adjusts the allocated buffer size, and dynamically forms batches of data transfers. Our evaluation shows that in a 16-GPU system, the proposed scheme can improve the performance by 13.2% and 17.5% on average from the prior cached and private schemes, respectively.

关键词： Graphics processing unit

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