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APPROX-NoC: A Data Approximation Framework for Network-On-Chip architectures 17

APPROX-NoC: A Data Approximation Framework for Network-On-Ch...

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44th Annual International symposium on computer architecture (ISCA)

作者： Boyapati, Rahul Huang, Jiayi Majumder, Pritam Yum, Ki Hwan Kim, Eun Jung Texas A&M Univ College Stn TX 77843 USA

ISBN: (纸本)9781450348928

the trend of unsustainable power consumption and large memory bandwidth demands in massively parallel multicore systems, with the advent of the big data era, has brought upon the onset of alternate computation paradigms utilizing heterogeneity, specialization, processor-in-memory and approximation. Approximate computing is being touted as a viable solution for high performance computation by relaxing the accuracy constraints of applications. this trend has been accentuated by emerging data intensive applications in domains like image/video processing, machine learning and big data analytics that allow inaccurate outputs within an acceptable variance. Leveraging relaxed accuracy for high throughput in Networks-on-Chip (NoCs), which have rapidly become the accepted method for connecting a large number of on-chip components, has not yet been explored. We propose APPROX-NoC, a hardware data approximation framework with an online data error control mechanism for high performance NoCs. APPROX-NoC facilitates approximate matching of data patterns, within a controllable value range, to compress them thereby reducing the volume of data movement across the chip. Our evaluation shows that APPROX-NoC achieves on average up to 9% latency reduction and 60% throughput improvement compared with state-of-the-art NoC data compression mechanisms, while maintaining low application error. Additionally, with a data intensive graph processing application we achieve a 36.7% latency reduction compared to state-of-the-art compression mechanisms.

关键词： Networks-On-Chip Approximate computing Data Compression

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DUO: Exposing On-chip Redundancy to Rank-Level ECC for high Reliability 24

DUO: Exposing On-chip Redundancy to Rank-Level ECC for High ...

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24th IEEE International symposium on high performance computer architecture (HPCA)

作者： Gong, Seong-Lyong Kim, Jungrae Lym, Sangkug Sullivan, Michael David, Howard Erez, Mattan UT Austin Austin TX 78712 USA Microsoft Albuquerque NM USA NVIDIA Santa Clara CA USA Huawei Shenzhen Peoples R China

ISBN: (纸本)9781538636596

DRAM row and column sparing cannot efficiently tolerate the increasing inherent fault rate caused by continued process scaling. In-DRAM ECC (IECC), an appealing alternative to sparing, can resolve inherent faults without significant changes to DRAM, but it is inefficient for highly-reliable systems where rank-level ECC (RECC) is already used against operational faults. In addition, DRAM design in the near future (possibly as early as DDR5) may transfer data in longer bursts, which complicates high-reliability RECC due to fewer devices being used per rank and increased fault granularity. We propose dual use of on-chip redundancy (DUO), a mechanism that bypasses the IECC module and transfers on-chip redundancy to be used directly for RECC. Due to its increased redundancy budget, DUO enables a strong and novel RECC for highly-reliable systems, called DUO SDDC. the long codewords of DUO SDDC provide fundamentally higher detection and correction capabilities, and several novel secondary-correction techniques integrate together to further expand its correction capability. According to our evaluation results, DUO shows performance degradation on par with or better than IECC (average 2-3%), while consuming less DRAM energy than IECC (average 4-14% overheads). DUO provides higher reliability than either IECC or the state-of-the-art ECC technique. We show the robust reliability of DUO SDDC by comparing it to other ECC schemes using two different inherent fault-error models.

关键词： DRAM reliability scaling errors ECC

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Power Provisioning for a Warehouse-sized computer 07

Power Provisioning for a Warehouse-sized Computer

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34th Annual International symposium on computer architecture

作者： Fan, Xiaobo Weber, Wolf-Dietrich Barroso, Luiz Andre Google Inc Mountain View CA 94043 USA

ISBN: (纸本)9781595937063

Large-scale Internet services require a computing infrastructure that can be appropriately described as a warehouse-sized computing system. the cost of building datacenter facilities capable of delivering a given power capacity to such a computer can rival the recurring energy consumption costs themselves. therefore, there are strong economic incentives to operate facilities as close as possible to maximum capacity, so that the non-recurring facility costs can be best amortized. that is difficult to achieve in practice because of uncertainties in equipment power ratings and because power consumption tends to vary significantly with the actual computing activity. Effective power provisioning strategies are needed to determine how much computing equipment can be safely and efficiently hosted within a given power budget. In this paper we present the aggregate power usage characteristics of large collections of servers (up to 15 thousand) for different classes of applications over a period of approximately six months. those observations allow us to evaluate opportunities for maximizing the use of the deployed power capacity of datacenters, and assess the risks of over-subscribing it. We find that even in well-tuned applications there is a noticeable gap (7 - 16%) between achieved and theoretical aggregate peak power usage at the cluster level (thousands of servers). the gap grows to almost 40% in whole datacenters. this headroom can be used to deploy additional compute equipment within the same power budget with minimal risk of exceeding it. We use our modeling framework to estimate the potential of power management schemes to reduce peak power and energy usage. We find that the opportunities for power and energy savings are significant, but greater at the cluster-level (thousands of servers) than at the rack-level (tens). Finally we argue that systems need to be power efficient across the activity range, and not only at peak performance levels.

关键词： Power modeling power provisioning energy efficiency

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high performance Simulations of Kernel P Systems 16

High Performance Simulations of Kernel P Systems

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16th IEEE Int Conf on high performance computing and Communications/11th IEEE Int Conf on Embedded Software and Systems\6th Int symposium on Cyberspace Safety and Security

作者： Bakir, Mehmet E. Konur, Savas Gheorghe, Marian Niculescu, Ionut Ipate, Florentin Univ Sheffield Dept Comp Sci Sheffield S Yorkshire England Univ Bucharest Dept Comp Sci Bucharest Romania

ISBN: (纸本)9781479961238

the paper presents the use of a membrane computing model for specifying a synthetic biology pulse generator example and discusses some simulation results produced by the tools associated with this model and compare their performances. the results show the potential of the simulation approach over the other analysis tools like model checkers.

关键词： FLAME Simulator KPWorkbench Simulator Kernel P System performance Comparision Simulation results high-performance simulating Computational Molecular Biology Seeds Draughts EQUIPMENT pulse generator use of treadmill synthetic biology Kernel

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Grid information services for distributed resource sharing

Grid information services for distributed resource sharing

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10th Annual IEEE International symposium on high performance Distributed computing

作者： Czajkowski, K Fitzgerald, S Foster, I Kesselman, C Univ So Calif Inst Informat Sci Marina Del Rey CA 90292 USA

ISBN: (纸本)0769512968

Grid technologies enable large-scale sharing of resources within formal or informal consortia of individuals and/or institutions: what are sometimes called virtual organizations. In these settings, the discovery, characterization, and monitoring of resources, services, and computations are challenging problems due to the considerable diversity, large numbers, dynamic behavior and geographical distribution of the entities in which a user might be interested. Consequently, information services are a vital part of any Grid software infrastructure, providing fundamental mechanisins for discovery, and monitoring, and hence for planning and adapting application behavior We present here an information services architecture that addresses performance, security, scalability, and robustness requirements. Our architecture defines simple low-level enquiry and registration protocols that make it easy to incorporate individual entities into various information structures, such as aggregate directories that support a variety of different query languages and discovery strategies. these protocols can also be combined with other Grid protocols to construct additional higher-level services and capabilities such as brokering, monitoring, fault detection, and troubleshooting. Our architecture has been implemented as MDS-2, which forms part of the Globus Grid toolkit and has been widely deployed and applied.

关键词： Distributed computer systems

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MIMDRAM: An End-to-End Processing-Using-DRAM System for high-throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data computing 30

MIMDRAM: An End-to-End Processing-Using-DRAM System for High...

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30th IEEE International symposium on high-performance computer architecture (HPCA)

作者： Oliveira, Geraldo F. Olgun, Ataberk Yaglikci, Abdullah Giray Bostanci, F. Nisa Gomez-Luna, Juan Ghose, Saugata Mutlu, Onur Swiss Fed Inst Technol Zurich Switzerland Univ Illinois Champaign IL USA

ISBN: (纸本)9798350393132;9798350393149

Processing-using-DRAM (PUD) is a processing-in-memory (PIM) approach that uses a DRAM array's massive internal parallelism to execute very-wide (e.g., 16,384-262,144-bit-wide) data-parallel operations, in a single-instruction multiple-data (SIMD) fashion. However, DRAM rows' large and rigid granularity limit the effectiveness and applicability of PUD in three ways. First, since applications have varying degrees of SIMD parallelism (which is often smaller than the DRAM row granularity), PUD execution often leads to underutilization, throughput loss, and energy waste. Second, due to the high area cost of implementing interconnects that connect columns in a wide DRAM row, most PUD architectures are limited to the execution of parallel map operations, where a single operation is performed over equally-sized input and output arrays. third, the need to feed the wide DRAM row with tens of thousands of data elements combined with the lack of adequate compiler support for PUD systems create a programmability barrier, since programmers need to manually extract SIMD parallelism from an application and map computation to the PUD hardware. Our goal is to design a flexible PUD system that overcomes the limitations caused by the large and rigid granularity of PUD. To this end, we propose MIMDRAM, a hardware/software co-designed PUD system that introduces new mechanisms to allocate and control only the necessary resources for a given PUD operation. the key idea of MIMDRAM is to leverage finegrained DRAM (i.e., the ability to independently access smaller segments of a large DRAM row) for PUD computation. MIMDRAM exploits this key idea to enable a multiple-instruction multiple-data (MIMD) execution model in each DRAM subarray (and SIMD execution within each DRAM row segment). We evaluate MIMDRAM using twelve real-world applications and 495 multi-programmed application mixes. Our evaluation shows that MIMDRAM provides 34x the performance, 14.3x the energy efficiency, 1.7x the throughp

关键词： DRAM energy-efficiency hardware/software co-design memory-centric computing processing-in-memory

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Runtime support for adaptive spatial partitioning and inter-kernel communication on GPUs 26

Runtime support for adaptive spatial partitioning and inter-...

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26th International symposium on computer architecture and high performance computing, SBAC-PAD 2014

作者： Ukidave, Yash Kalra, Charu Kaeli, David Mistry, Perhaad Schaa, Dana Department of Electrical and Computer Engineering Northeastern University BostonMA United States Advanced Micro Devices United States

ISBN: (纸本)9781479969043

GPUs have gained tremendous popularity in a broad range of application domains. these applications possess varying grains of parallelism and place high demands on compute resources - many times imposing real-time constraints, requiring flexible work schedules, and relying on concurrent execution of multiple kernels on the device. these requirements present a number of challenges when targeting current GPUs. To support this class of applications, and to take full advantage of the large number of compute cores present on the GPU, we need a new mechanism to support concurrent execution and provide flexible mapping of compute kernels to the GPU. In this paper, we describe a new scheduling mechanism for dynamic spatial partitioning of the GPU, which adapts to the current execution state of compute workloads on the device. To enable this functionality, we extend the OpenCL runtime environment to map multiple command queues to a single device, and effectively partitioning the device. the result is that kernels that can benefit from concurrent execution on a partitioned device can effectively utilize the full compute resources on the GPU. To accelerate next-generation workloads, we also support an inter-kernel communication mechanism that enables concurrent kernels to interact in a producer-consumer relationship. the proposed partitioning mechanism is evaluated using real world applications taken from signal and image processing, linear algebra, and data mining domains. For these performance-hungry applications we achieve a 3.1X performance speedup using a combination of the proposed scheduling scheme and inter-kernel communication, versus relying on the conventional GPU runtime. © 2014 IEEE.

关键词： Graphics processing unit

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MTF: A Scalable Exchange Format for Traces of high performance computing Systems

MTF: A Scalable Exchange Format for Traces of High Performan...

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IEEE 19th International Conference on Program Comprehension (ICPC)

作者： Alawneh, Luay Hamou-Lhadj, Abdelwahab Concordia Univ Software Behav Anal Grp Dept Elect & Comp Engn Montreal PQ H3G 1M8 Canada

ISBN: (纸本)9780769543987

Execution traces generated from running high performance computing applications (HPC) may reach tens or hundreds of gigabytes. the trace data can be used for visualization, analysis of profiling information about the target system. However, in order to make the utilization of this data efficient, the trace needs to be represented in a structure that facilitates the access to its data. One important factor that should be considered when representing trace data is scalability;the trace metamodel should be able to represent the trace in a compact form that enables scalability of the analysis tools. Additionally, a trace file needs to be available in a format that is well-known in the software engineering area by making it open. In this paper, we propose a metamodel for representing dynamic information generated from HPC that use the MPI standard as the inter-process communication model. MPI Trace Format (MTF) is meant to meet the aforementioned requirements and is intended to facilitate the interoperability among different trace analysis tools.

关键词： HPC-high performance computing systems Inter-process communication traces MPI-Message Passing Interface Standard exchange format Trace Metamodel

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Handoff in mobile ATM networks: Framework for performance optimization 16

Handoff in mobile ATM networks: Framework for performance op...

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16th Annual International symposium on high performance computing Systems and Applications, HPCS 2002

作者： Medidi, Sirisha R. Golshani, Forouzan School of Electrical Engineering and Computer Science Washington State University PullmanWA99164-2752 United States Department of Computer Science and Engineering Arizona State University TempeAZ85287-5406 United States

ISBN: (纸本)0769516262

Current handoff rerouting techniques in Mobile ATM networks fail to optimize some or all of the following parameters: handoff latency, route length, computational complexity, communication disruption period, network buffer requirements, and bandwidth *** s paper focuses on the optimization of the above parameters in the context of efficient handoff in Mobile ATM networks.W e propose a framework for efficient handoff, in which the route information of a call in progress can be released to the communicating mobile hosts and their corresponding *** switch covering the mobile host requesting handoff selects an appropriate rerouting process based on the route information and the location of the mobile hosts.A comparitive evaluation of our scheme with the existing schemes is presented. © 2002 IEEE.

关键词： Asynchronous transfer mode

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Conservative garbage collection on distributed shared memory systems

Conservative garbage collection on distributed shared memory...

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16th International Conference on Distributed computing Systems

作者： Yu, WM Cox, A RICE UNIV DEPT COMP SCIHOUSTONTX 77251

ISBN: (纸本)0818673982

In this paper we present the design and implementation of a conservative garbage collection algorithms for distributed shared memory (DSM) applications that use weakly-typed languages like C or C++, and evaluate its performance. In the absence of language support to identify references, our algorithm constructed a conservative approximation of the set of cross-node references based on local information only. It was also designed to tolerate memory inconsistency on DSM systems that use relaxed consistency protocols. these techniques enabled every node to perform garbage collections without communicating with others, effectively avoiding the high cost of cross-node communication in networks of workstations. We measured the performance of our garbage collector against explicit programmer management using three application programs. In two out of the three programs the performance of the GC version is within 15% of the explicit version. the results showed that the garbage collector has two effects on application programs. On one hand, it tends to reduce memory locality, increasing the communication cost;on the other hand, it may eliminate synchronization and memory accesses that would be incurred if memory were managed by the programmer, reducing the communication cost.

关键词： Distributed computer systems

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