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Constructing the ASCI computational grid 9

Constructing the ASCI computational grid

引用

9th IEEE International symposium on high performance Distributed computing

作者： Beiriger, JI Bivens, HP Humphreys, SL Johnson, WR Rhea, RE Sandia Natl Labs Albuquerque NM 87185 USA

ISBN: (纸本)0769507840

the Accelerated Strategic computing Initiative (ASCI) computational grid is being constructed to interconnect the high performance computing resources of the nuclear weapons complex. the grid will simplify access to the diverse computing, storage, network, and visualization resources, and will enable the coordinated use of shared resources regardless of location. To match existing hardware platforms, required security services, and current simulation practices, the Globus Metacomputing Toolkit[1] was selected to provide core grid services. the ASCI grid extends Globus functionality by operating as an independent grid, incorporating Kerberos-based security, interfacing to Sandia'S Cplant(TM), and extending job monitoring services. To fully meet ASCI's needs, the architecture layers distributed work management and criteria-driven resource selection services on top of Globus. these services simplify the grid interface by allowing users to simply request "run code X anywhere" this paper describes the initial design and prototype of the ASCI grid.

关键词： Acceleration Computational modeling computer networks Grid computing Hardware high performance computing Metacomputing Nuclear weapons Security Visualization

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Security and Privacy of Smart Cities: Issues and Challenge 20

Security and Privacy of Smart Cities: Issues and Challenge

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20th International Conference on high performance computing and Communications, 16th IEEE International Conference on Smart City and 4th IEEE International Conference on Data Science and Systems, HPCC/SmartCity/DSS 2018

作者： Sookhak, Mehdi Tang, Helen Yu, F. Richard Depart. of Systems and Computer Eng. Carleton University OttawaON Canada Defence Research and Development Canada OttawaON Canada

ISBN: (纸本)9781538666142

Smart city has been emerged as a new paradigm to dynamically optimize the resources in cities and provide better facilities and quality of life for the citizens. Despite the potential vision of smart cities, security and privacy issues remain to be carefully addressed. In this paper, we present a comprehensive survey of security and privacy issues of smart cities, and categorize the present and future developments within this area. We also describe a thematic taxonomy of security and privacy issues of smart cities to highlight the requirements for designing a secure smart city, identify the existing security and privacy solutions, and present open research issues and challenges of security and privacy in smart cities. © 2018 IEEE.

关键词： Big data

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Monitoring, accounting and automated decision support for the alice experiment based on the MonALISA framework

Monitoring, accounting and automated decision support for th...

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16th International symposium on high performance Distributed computing 2007, HPDC'07 and Co-Located Workshops

作者： Cirstoiu, Catalin C. Grigoras, Costin C. Betev, Latchezar L. Costan, Alexandru A. Legrand, Iosif Charles European Center for Nuclear Research CERN Geneva Switzerland Politehnica University of Bucharest Romania California Institute of Technology United States

ISBN: (纸本)1595937161

the successful administration of a global Data Grid system requires collecting and storing relevant monitoring information, using it to show the status and the trends of the entire system. the collected information is further used in developing the higher-level services and components of the distributed system to provide a degree of automated operational decisions, in order to maintain and optimize the work-flow through the entire system. In this paper we present the architecture of the monitoring system, developed within the MonALISA framework, for the ALICE Grid. the system uses flexible mechanisms for collecting, aggregating, storing and presenting monitoring information both in near real-time or history charts, in global or specific views, being able to generate alerts or take automated decisions based on it. Copyright 2007 ACM.

关键词： Grid computing

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On the efficiency of register file versus broadcast interconnect for collective communications in data-parallel hardware accelerators

On the efficiency of register file versus broadcast intercon...

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24th International symposium on computer architecture and high performance computing, SBAC-PAD 2012

作者： Pedram, Ardavan Gerstlauer, Andreas Van De Geijn, Robert A. Department of Electrical and Computer Engineering University of Texas Austin TX United States Department of Computer Science University of Texas Austin TX United States

ISBN: (纸本)9781467347907

Reducing power consumption and increasing efficiency is a key concern for many applications. How to design highly efficient computing elements while maintaining enough flexibility within a domain of applications is a fundamental question. In this paper, we present how broadcast buses can eliminate the use of power hungry multi-ported register files in the context of data-parallel hardware accelerators for linear algebra operations. We demonstrate an algorithm/architecture co-design for the mapping of different collective communication operations, which are crucial for achieving performance and efficiency in most linear algebra routines, such as GEMM, SYRK and matrix transposition. We compare a broadcast bus based architecture with conventional SIMD, 2D-SIMD and flat register file for these operations in terms of area and energy efficiency. Results show that fast broadcast data movement abilities in a prototypical linear algebra core can achieve up to 75x better power and up to 10x better area efficiency compared to traditional SIMD architectures. © 2012 IEEE.

关键词： Buses

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A Preliminary Review of Function as a Service platform running with AWS Spot Instances 35

A Preliminary Review of Function as a Service platform runni...

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35th IEEE International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Marques, Luciana da Costa Goldman, Alfredo Univ Sao Paulo Inst Math & Stat Sao Paulo Brazil

ISBN: (纸本)9798350381603

Cloud computing enabled users to easily implement what was previously a complex data center infrastructure, reducing its maintenance related costs. However, cloud costs can be challenging to predict with all its variety of resources and price schemes. Amazon Web Services offers the spot pricing mechanism for virtual machines (VM), in which an end user buys idle VM capacity for up to 90% cost reduction. But, these machines can be terminated by AWS at any given time, so not every application may be a good fit using them. We here explore the deployment of function as a service (FaaS) platforms in spots by using funcX, a distributed and high performance FaaS project. We chose MASA-OpenMP, a DNA sequence comparison project, to be executed in two different scenarios: one with in-memory execution in spot VMs, orchestrated with HADS, a Hibernation-Aware Dynamic Scheduler for spot instances, and the other using a funcX client deployed in spot instances as well. Our initial results showed that costs using the funcX approach are potentially smaller, and it also offers more implementation flexibility. We also present possible next steps for more experiments and investigation.

关键词： cloud computing spot instances preemptive virtual machines function as a service

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high-Bandwidth Low-Latency Approximate Interconnection Networks 23

High-Bandwidth Low-Latency Approximate Interconnection Netwo...

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23rd IEEE International symposium on high performance computer architecture (HPCA)

作者： Fujiki, Daichi Ishii, Kiyo Fujiwara, Ikki Matsutani, Hiroki Amano, Hideharu Casanova, Henri Koibuchi, Michihiro Natl Inst Informat Tokyo Japan Natl Inst Adv Ind Sci & Technol Tokyo Japan Keio Univ Tokyo Japan Univ Hawaii Manoa Honolulu HI 96822 USA

ISBN: (纸本)9781509049851

Computational applications are subject to various kinds of numerical errors, ranging from deterministic roundoff errors to soft errors caused by non-deterministic bit flips, which do not lead to application failure but corrupt application results. Non-deterministic bit flips are typically mitigated in hardware using various error correcting codes (ECC). But in practice, due to performance and cost concerns, these techniques do not guarantee error-free execution. On large-scale computing platforms, soft errors occur with non-negligible probability in RAM and on the CPU, and it has become clear that applications must tolerate them. For some applications, this tolerance is intrinsic as result quality can remain acceptable even in the presence of soft errors (e.g., data analysis applications, multimedia applications). Tolerance can also be built into the application, resolving data corruptions in software during application execution. By contrast, today's optical networks hold on to a rigid error-free standard, which imposes limits on network performance scalability. In this work we propose high-bandwidth, low-latency approximate networks with the following three features: (1) Optical links that exploit multi-level quadrature amplitude modulation (QAM) for achieving high bandwidth;(2) Avoidance of forward error correction (FEC), which makes optical link error-prone but affords lower latency;and (3) the use of symbol mapping coding between bit sequence and QAM to ensure data integrity that is sufficient for practical soft-error-tolerant applications. Discrete-event simulation results for application benchmarks show that approx networks achieve speedups up to 2.94 when compared to conventional networks.

关键词： Approximate computing Interconnect and network interface architectures

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ACEcardTM: A high-performance architecture for run-time reconfiguration 1

ACEcardTM: A high-performance architecture for run-time reco...

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proceedings of the 1998 12th International Parallel Processing symposium and 9th symposium on Parallel and Distributed Processing

作者： Davis, Don Harris, Jonathan TSI TelSys Inc Columbia United States

ISBN: (纸本)0818684038

Recent FPGA architectures have shown an increased emphasis on run-time reconfiguration, or the ability to rapidly change the functionality of the FPGA to sequentially accommodate large processing tasks. In addition, partial reconfiguration allows for the reconfiguration of a portion of the FPGA while the remainder is running. these two features enable the use of reconfigurable computing in high-performance multi-threaded multi-user environments. However, current board designs are not optimized to provide the processing support required to maintain this run-time environment which includes management of the reconfigurable resources, interface to the host processor and data movement. In this paper, we will describe the architecture, design and applicability of the ACEcard, a high performance reconfigurable co-processor. the ACEcard contains reconfigurable resources as well as an embedded processor to manage the runtime reconfiguration of those resources. We will provide details of the architecture of the card as well as a description of the current and future Java-based runtime environment.

关键词： computer architecture

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SIMP (Single Instruction stream/Multiple instruction Pipelining): a novel high-speed single-processor architecture. 89

SIMP (Single Instruction stream/Multiple instruction Pipelin...

引用

16th Annual International symposium on computer architecture

作者： Murakami, Kazuaki Irie, Naohiko Kuga, Morihiro Tomita, Shinji Kyushu Univ Fukuoka Jpn

ISBN: (纸本)9780897913195

SIMP is a novel multiple-instruction-pipeline parallel architecture. It enhances the performance of SISD (single-instruction/single-data-stream) processors by using both temporal and spatial parallelisms, while keeping program compatibility. the degree of performance enhancement achieved by SIMP depends on determining how to supply multiple instructions continuously and how to resolve data and control dependencies effectively. Techniques for instruction fetch and dependency resolution have been devised for this purpose. the instruction-fetch mechanism utilizes unique schemes for prefetching multiple instructions with the help of branch prediction, squashing instructions selectively, and providing multiple conditional modes as a result. the dependency-resolution mechanism permits out-of-order execution of sequential instruction stream. the out-of-order execution model is based on R.M. Tomasulo's algorithm (1967), which has been used in single instruction-pipeline processors. However, it is greatly extended to accommodate multiple-instruction pipelining.

关键词： computer systems, Digital

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Dynamically Specialized Datapaths for Energy Efficient computing

Dynamically Specialized Datapaths for Energy Efficient Compu...

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17th IEEE International symposium on high-performance computer architecture (HPCA)

作者： Govindaraju, Venkatraman Ho, Chen-Han Sankaralingam, Karthikeyan Univ Wisconsin Vert Res Grp Madison WI 53706 USA

ISBN: (纸本)9781424494354

Due to limits in technology scaling, energy efficiency of logic devices is decreasing in successive generations. To provide continued performance improvements without increasing power, regardless of the sequential or parallel nature of the application, microarchitectural energy efficiency must improve. We propose Dynamically Specialized Datapaths to improve the energy efficiency of general purpose programmable processors. the key insights of this work are the following. First, applications execute in phases and these phases can be determined by creating a path-tree of basic-blocks rooted at the inner-most loop. Second, specialized datapaths corresponding to these path-trees, which we refer to as DySER blocks, can be constructed by interconnecting a set of heterogeneous computation units with a circuit-switched network. these blocks can be easily integrated with a processor pipeline. A synthesized RTL implementation using an industry 55nm technology library shows a 64-functional-unit DySER block occupies approximately the same area as a 64 KB single-ported SRAM and can execute at 2 GHz. We extend the GCC compiler to identify path-trees and code-mapping to DySER and evaluate the PARSEC, SPEC and Parboil benchmarks suites. Our results show that in most cases two DySER blocks can achieve the same performance (within 5%) as having a specialized hardware module for each path-tree. A 64-FU DySER block can cover 12% to 100% of the dynamically executed instruction stream. When integrated with a dual-issue out-of-order processor, two DySER blocks provide geometric mean speedup of 2.1X (1.15X to 10X), and geometric mean energy reduction of 40% (up to 70%), and 60% energy reduction if no performance improvement is required.

关键词： Energy efficiency performance boost Energy conservation PROCESSOR instruction flow hardware module Logic devices Phase Geometric mean Circuit switched networks

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Bypass: A tool for building split execution systems 9

Bypass: A tool for building split execution systems

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9th IEEE International symposium on high performance Distributed computing

作者： thain, D Livny, M Univ Wisconsin Dept Comp Sci Madison WI 53703 USA

ISBN: (纸本)0769507832;0769507840

Split execution is a common model for providing a friendly environment on a foreign machine. In this model, a remotely executing process sends some or all of its system calls back to a home environment for execution. Unfortunately, hand-coding split execution system for experimentation and research is difficult and error-prone. We have built a tool, Bypass, for quickly producing portable and correct split execution systems for unmodified legacy applications. We demonstrate Bypass by using it to transparently connect a POSIX application to a simple data staging system based on the Globus toolkit.

关键词： Application software Buildings computer architecture Databases Kernel Libraries Machine vision Operating systems Programming profession Routing

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