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Bringing Fault-Tolerant GigaHertz-computing to Space A Multi-Stage Software-Side Fault-Tolerance Approach for Miniaturized Spacecraft 26

Bringing Fault-Tolerant GigaHertz-Computing to Space A Multi...

引用

26th IEEE Asian Test symposium (ATS)

作者： Fuchs, Christian M. Stefanov, Todor P. Murillo, Nadia M. Plaat, Aske Leiden Univ Leiden Inst Adv Comp Sci NL-2333 CA Leiden Netherlands Leiden Univ Leiden Observ NL-2333 CA Leiden Netherlands

ISBN: (纸本)9781538624371

Modern embedded technology is a driving factor in satellite miniaturization, contributing to a massive boom in satellite launches and a rapidly evolving new space industry. Miniaturized satellites, however, suffer from low reliability, as traditional hardware-based fault-tolerance (FT) concepts are ineffective for on-board computers (OBCs) utilizing modern systems-on-a-chip (SoC). therefore, larger satellites continue to rely on proven processors with large feature sizes. Software-based concepts have largely been ignored by the space industry as they were researched only in theory, and have not yet reached the level of maturity necessary for implementation. We present the first integral, real-world solution to enable fault-tolerant general-purpose computing with modern multiprocessor-SoCs (MPSoCs) for spaceflight, thereby enabling their use in future high-priority space missions. the presented multi-stage approach consists of three FT stages, combining coarse-grained thread-level distributed self-validation, FPGA reconfiguration, and mixed criticality to assure long-term FT and excellent scalability for both resource constrained and critical high-priority space missions. Early benchmark results indicate a drastic performance increase over state-of-the-art radiation-hard OBC designs and considerably lower software- and hardware development costs. this approach was developed for a 4-year European Space Agency (ESA) project, and we are implementing a tiled MPSoC prototype jointly with two industrial partners.

关键词： Satellites Space vehicles Circuit faults computer architecture Hardware Instruction sets

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Bit-Pragmatic Deep Neural Network computing 17

Bit-Pragmatic Deep Neural Network Computing

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50th Annual IEEE/ACM International symposium on Microarchitecture (MICRO)

作者： Albericio, Jorge Delmas, Alberto Judd, Patrick Sharify, Sayeh O'Leary, Gerard Genov, Roman Moshovos, Andreas NVIDIA Santa Clara CA 95051 USA Univ Toronto Toronto ON Canada

ISBN: (纸本)9781450349529

Deep Neural Networks expose a high degree of parallelism, making them amenable to highly data parallel architectures. However, data-parallel architectures often accept inefficiency in individual computations for the sake of overall efficiency. We show that on average, activation values of convolutional layers during inference in modern Deep Convolutional Neural Networks (CNNs) contain 92% zero bits. Processing these zero bits entails ineffectual computations that could be skipped. We propose Pragmatic (PRA), a massively data-parallel architecture that eliminates most of the ineffectual computations on-the-fly, improving performance and energy efficiency compared to state-of-the-art high-performance accelerators [5]. the idea behind PRA is deceptively simple: use serial-parallel shift-and-add multiplication while skipping the zero bits of the serial input. However, a straightforward implementation based on shift-and-add multiplication yields unacceptable area, power and memory access overheads compared to a conventional bit-parallel design. PRA incorporates a set of design decisions to yield a practical, area and energy efficient design. Measurements demonstrate that for convolutional layers, PRA is 4.31x faster than DaDianNao [5] (DaDN) using a 16-bit fixed-point representation. While PRA requires 1.68x more area than DaDN, the performance gains yield a 1.70x increase in energy efficiency in a 65nm technology. With 8-bit quantized activations, PRA is 2.25x faster and 1.31x more energy efficient than an 8-bit version of DaDN.

关键词： Hardware Accelerators Machine Learning Neural Networks

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NVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications symposium

NVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applic...

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6th IEEE Non-Volatile Memory Systems and Applications symposium, NVMSA 2017

ISBN: (纸本)9781538617687

the proceedings contain 20 papers. the topics discussed include: energy-efficient SQL query exploiting RRAM-based process-in-memory structure;a novel RERAM-based processing-in-memory architecture for graph computing;a quantization-aware regularized learning method in multi-level MEMristor-based neuromorphic computing system;an FPGA-based platform for non volatile memory emulation;designing persistent heap for byte addressable NVRAM;FSL: fast system launch through persistent computing with nonvolatile memory;a fast profiler for compilation of multi-threaded applications on a hybrid memory system;on-line memory defragmentation for NVM-based persistent heaps;advanced performance improvement algorithms for emerging resistive memory: CBRAM case study;framework for efficient and flexible scheduling of flash memory operations;enhancing SSD performance with LDPC -aware garbage collection;improving read performance via selective Vpass Reduction on high density 3D NAND flash memory;downsampling of time-series data for approximated dynamic time warping on nonvolatile memories;AEPE: an area and power efficient RRAM crossbar-based accelerator for deep CNNs;and runtime and reconfiguration dual-aware placement for SRAM-NVM hybrid FPGAs.

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Extended Dot Cluster Marker for high-speed 3D Tracking in Dynamic Projection Mapping 16

Extended Dot Cluster Marker for High-speed 3D Tracking in Dy...

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16th IEEE International symposium on Mixed and Augmented Reality (ISMAR)

作者： Watanabe, Yoshihiro Kato, Toshiyuki Ishikawa, Masatoshi Univ Tokyo Grad Sch Informat Sci & Technol Bunkyo Ku 7-3-1 Hongo Tokyo 1138656 Japan

ISBN: (纸本)9781538629437

the technique of Projection Mapping, which is useful for merging real-world geometry with an augmented appearance, is a promising core technology for augmented reality (AR). In recent years, dynamically changing environments, mainly a consequence of the growing demand for interactive user experiences, have contributed to a new style of AR applications. However, performance levels of current systems for realizing 3D effects, in terms of the tracking speed and projection ability, are insufficient to meet these demands. In this paper, we present a high-speed, occlusion-robust marker-based 3D tracking method achieved by only using a monocular monochrome image. the objective of our research is to develop an automatic marker design method for any 3D shape and an effective framework for stabilizing tracking at high throughput by extending the latest promising work based on a deformable dot cluster marker [46]. Furthermore, this tracking method was used in combination with a high-speed projector, both of which can achieve high throughput and low latency, on the order of milliseconds. this enabled us to realize a high-quality computational display capable of representing the material appearance of a dynamically moving target. the demonstration showed that the effect of a dynamically changing appearance with nearly imperceptible latency drastically enriches the sense of immersion in the recognition of augmented materials with the naked eye.

关键词： H.5.1 [Information Interfaces and Presentation]: Multimedia Information Systems-Artificial, augmented and virtual realities I. 4.8 [Image Processing and computer Vision]: Scene Analysis-Tracking I.4.0 [Image Processing and computer Vision]: General-Image displays

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high performance network-on-chip simulation by interval-based timing predictions 15

High performance network-on-chip simulation by interval-base...

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15th IEEE/ACM symposium on Embedded Systems for Real-Time Multimedia, ESTIMedia 2017

作者： Rolo, Sascha Hannig, Frank Teich, Jürgen Germany

ISBN: (纸本)9781450351171

Current multi- and many-core computer architectures heavily use Network-on-Chip (NoC) communication in order to meet the increased bandwidth demands between the processors and for reasons of scalability. For the proper analysis of concurrency, utilization, and workload distribution of parallel multi-media applications running on such NoC-based architectures, high-speed simulation techniques are required. Apart from accurate timing simulation of compute resources, it is of utmost importance also to accurately model the delays caused by the packet-based network communication in order to reliably verify performance numbers, or to identify any bolenecks of the underlying architecture, or to study workload distribution techniques or routing algorithms. In this paper, we present a novel simulation approach for NoCs that allows to simulate such communication delays equally accurate but much faster in average than on a it-by-it basis. We propose novel algorithmic and analytical techniques that predict the transmission intervals dynamically based on the arrival of communication requests, actual congestion in the NoC, routing information, packet lengths, and other parameters. According to such predictions, the simulation time may in many cases be automatically advanced, thus reducing the number of events to process in the simulator to a large extent. e presented NoC simulation technique has been integrated into a system-level multi-core architecture simulator. Experiments in running parallel real-world and multi-media applications on a simulated scalable NoC architecture show that we are able to achieve speedups of three orders of magnitude compared to cycle-accurate NoC simulators, while preserving a timing accuracy of above 95%. © 2017 ACM.

关键词： Network-on-chip

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13th International symposium on Applied Reconfigurable computing, ARC 2017

13th International Symposium on Applied Reconfigurable Compu...

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13th International symposium on Applied Reconfigurable computing, ARC 2017

ISBN: (纸本)9783319562575

the proceedings contain 28 papers. the special focus in this conference is on Applied Reconfigurable computing. the topics include: Improving the performance of adaptive cache in reconfigurable VLIW processor;VLIW-based FPGA computation fabric with streaming memory hierarchy for medical imaging applications;an FPGA-based implementation of a pipelined FFT processor for high-speed signal processing applications;soft timing closure for soft programmable logic cores: the ARGen approach;FPGA debugging with MATLAB using a rule-based inference system;hardness analysis and instrumentation of verilog gate level code for FPGA-based designs;a framework for high level simulation and optimization of coarse-grained reconfigurable architectures;parameter sensitivity in virtual FPGA architectures;custom framework for run-time trading strategies;exploring HLS optimizations for efficient stereo matching hardware implementation;architecture reconfiguration as a mechanism for sustainable performance of embedded systems in case of variations in available power;applying TMR in hardware accelerators generated by high-level synthesis design flow for mitigating multiple bit upsets in SRAM-based FPGAs;genomic data clustering on FPGAs for compression;optimizing CNN-based object detection algorithms on embedded FPGA platforms;an FPGA realization of a deep convolutional neural network using a threshold neuron pruning;accuracy evaluation of long short term memory network based language model with fixed-point arithmetic;FPGA implementation of a short read mapping accelerator and a machine learning methodology for cache recommendation.

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GCN: GPU-based Cube CNN Framework for Hyperspectral Image Classification 46

GCN: GPU-based Cube CNN Framework for Hyperspectral Image Cl...

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46th International Conference on Parallel Processing Workshops (ICPPW)

作者： Dong, Han Li, Tao Leng, Jiabing Kong, Lingyan Bai, Gang Nankai Univ Coll Comp & Control Engn Tianjin 300350 Peoples R China Chinese Acad Sci Inst Comp Technol State Key Lab Comp Architecture Beijing 100190 Peoples R China

ISBN: (纸本)9781538610428

Hyperspectral image classification has been proved significant in remote sensing field. Traditional classification methods have meet bottlenecks due to the lack of remote sensing background knowledge or high dimensionality. Deep learning based methods, such as deep convolutional neural network (CNN), can effectively extract high level features from raw data. But the training of deep CNN is rather time-consuming. the general purpose graphic processing units (GPUs) have been considered as one of the most common co-processors that can help accelerate deep learning applications. In this paper we propose a GPU-based Cube CNN (GCN) framework for hyperspectral image classification. First, a Parallel Neighbor Pixels Extraction (PNPE) algorithm is designed to enable the framework directly loading raw hyperspectral image into GPU's global memory, and extracting samples into data cube. then, based on the peculiarity of hyperspectral image and cube convolution, we propose a novel Cube CNN-to-GPU mapping mechanism that transfers the training of Cube CNN to GPU effectively. Finally, the mini-batch gradient descent(MBGD) algorithm is improved with computing United Device architecture(CUDA) multi-streaming technique, which further speeds up network training in GCN framework. Experiments on KSC dataset, PU dataset and SA dataset show that, compared with state-of-art framework Caffe, we achieve up to 83% and 67% reduction in network training time without losing accuracy, when using SGD (Stochastic Gradient Descent) and MBGD algorithm respectively. Experiments across different GPUs show the same performance trend, which demonstrates the good extendibility of GCN framework.

关键词： hyperspectral image classification deep CNN GPU parallel computing

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Strider: A Hybrid Adaptive Distributed RDF Stream Processing Engine 16th

Strider: A Hybrid Adaptive Distributed RDF Stream Processing...

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16th International Semantic Web Conference (ISWC)

作者： Ren, Xiangnan Cure, Olivier ATOS 80 Quai Voltaire F-95870 Bezons France UPEM CNRS LIGM UMR 8049 F-77454 Marne La Vallee France

ISBN: (纸本)9783319682884;9783319682877

Real-time processing of data streams emanating from sensors is becoming a common task in Internet of things scenarios. the key implementation goal consists in efficiently handling massive incoming data streams and supporting advanced data analytics services like anomaly detection. In an on-going, industrial project, a 24/7 available stream processing engine usually faces dynamically changing data and workload characteristics. these changes impact the engine's performance and reliability. We propose Strider, a hybrid adaptive distributed RDF Stream Processing engine that optimizes logical query plan according to the state of data streams. Strider has been designed to guarantee important industrial properties such as scalability, high availability, fault tolerance, high throughput and acceptable latency. these guarantees are obtained by designing the engine's architecture with state-of-the-art Apache components such as Spark and Kafka. We highlight the efficiency (e.g., on a single machine machine, up to 60x gain on throughput compared to state-of-the-art systems, a throughput of 3.1 million triples/second on a 9 machines cluster, a major breakthrough in this system's category) of Strider on real-world and synthetic data sets.

关键词： RDF stream processing SPARQL Adaptive query processing Distributed computing Apache spark

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Surrogate-Based Multidisciplinary Design Optimization of an Autonomous Underwater Vehicle Hull

Surrogate-Based Multidisciplinary Design Optimization of an ...

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International symposium on Distributed computing and Applications to Business, Engineering and Science (DCABES)

作者： Xu Chen Peng Wang Daiyu Zhang School of Marine Science and Technology Northwestern Polytechnical University Xi'an P.R. China School of Naval Architecture and Engineering Jiangsu University of Science and Technology Zhenjiang P.R. China

ISBN: (纸本)9781538621639

this paper performed multidisciplinary design optimization (MDO) of an AUV hull to minimize the energy consumption for sailing. the hull is decomposed into two disciplines and a multidisciplinary optimization problem is built. Multidisciplinary design feasible (MDF) architecture is adopted for optimization. A CFD-based analysis framework is proposed for resistance calculation of sample points in the hydrodynamics discipline and then a Kriging surrogate model is constructed. the optimal design of AUV hull is obtained and the computational cost is quite low with few high-fidelity CFD simulations.

关键词： Optimization Solid modeling Computational modeling computer architecture Hydrodynamics Nose Resistance

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Enhancing and evaluating an architecture for privacy in the integration of Internet of things and cloud computing

Enhancing and evaluating an architecture for privacy in the ...

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IEEE International symposium on Network computing and Applications

作者： Luis Alberto B. Pacheco Eduardo Alchieri Priscila A. Solis Barreto University of Brasília Brasília Brazil Universidade de Brasilia Brasilia DF Brazil

through the Internet of things (IoT) a large number of devices are connected to the Internet, resulting in a huge amount of produced data. Since these devices have limited resources, it is proposed the use of cloud computing to store, process and control the access to these data. A fundamental challenge related to this integration is the privacy, since confidential information about users may be collected by IoT devices and sent to the cloud. Consequently, it is imperative to provide mechanisms that allow users to control the use of their data. the proposed architectures either do not provide security inside the IoT network or do not evaluate the overhead imposed in the IoT devices. In order to fill this gap, this work evaluates and enhances an architecture for privacy in the integration of IoT and cloud computing by providing a method to protect the data generated by IoT devices without the use of a secure transport layer protocol, decreasing the amount of resources consumed by these devices. the proposed method is analyzed, in terms of delay and energy consumption, by an analytical and an experimental evaluation, comparing its performance with other approaches found in the literature.

关键词： Cloud computing computer architecture Cryptography Data privacy Privacy Logic gates

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