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16th IEEE ISPA / 17th IEEE IUCC / 8th IEEE BDCloud / 11th IEEE SocialCom / 8th IEEE SustainCom

作者： Zhang, Yang Feng, Dan Tan, Zhipeng Liu, Jingning Tong, Wei Wang, Chengning Huazhong Univ Sci & Technol Minist Educ China Key Lab Informat Storage Syst Wuhan Natl Lab OptoelectSch Comp Sci & Technol Wuhan Hubei Peoples R China

ISBN: (纸本)9781728111414

Resistive Memory (ReRAM) is promising to be used as the storage-class memory due to its good scalability, high density, low standby power and non-volatility. By employing the unique crossbar structure, ReRAM can be constructed with extremely high density. However, ReRAM's crossbar structure suffers from an IR drop issue, which causes the asymmetric access latency in crossbar arrays. Moreover, without access transistors in the crossbar structure, read and write disturbances lead to serious data reliability problem. In this paper, we propose Asymmetric-ReRAM (A-ReRAM) to overcome the challenges of crossbar ReRAM. By reducing the IR drops along both wordlines and bitlines, leveraging the asymmetric access latency in crossbar arrays and exposing the most appropriate write latency to the memory controller, A-ReRAM effectively reduces the access latency. By applying the circuit-architecture level solutions, A-ReRAM addresses the read and write disturbances, and significantly improves the reliability. the experimental results show that, A-ReRAM improves system performance by 29.7% and 19.2%, and reduces the energy consumption by 21.1% and 11.3% on average, compared to the baseline and the state-of-the-art crossbar ReRAM design. Meanwhile, A-ReRAM significantly improves the reliability of ReRAM-based memory systems.

关键词： ReRAM crossbar IR drop asymmetric access latency read and write disturbances

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Middleware support for global access to integrated computational collaboratories

Middleware support for global access to integrated computati...

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10th Annual IEEE International symposium on high performance Distributed computing

作者： Mann, V Parashar, M Rutgers State Univ Dept Elect & Comp Engn Appl Software Syst Lab Piscataway NJ 08854 USA

ISBN: (纸本)0769512968

the growth of the Internet and the advent of the computational "Grid" have made it possible to develop and deploy advanced computational collaboratories. these systems build on high-end computational resources and communication technologies underlying the Grid, and provide seamless and collaborative access to particular resources, services or applications. Integrating these 'focused" collaboratories presents significant challenges. Key among these is the design and development of robust middleware support that addresses scalability, service discovery, security and access control, and interaction and collaboration management for consistent access. In this paper we first investigate the architecture of such a middleware that enables global (web-based) access to collaboratories. We then present the design and implementation of a middle-ware substrate that enables a peer-to-peer integration of and global (collaborative) access to geographically, distributed instances of the DISCOVER computational collaboratory for interaction and steering.

关键词： computer supported cooperative work

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An Optimized Stochastic Techniques related to Option Pricing 16

An Optimized Stochastic Techniques related to Option Pricing

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16th Conference on computer Science and Intelligence Systems (FedCSIS)

作者： Todorov, Venelin Dimov, Ivan Fidanova, Stefka Apostolov, Stoyan Bulgarian Acad Sci Inst Math & Informat 8 Acad G Bonchev Str Sofia 1113 Bulgaria Bulgarian Acad Sci Inst Informat & Commun Technol 25A Acad G Bonchev Str Sofia 1113 Bulgaria Sofia Univ Fac Math & Informat Sofia 1126 Bulgaria

ISBN: (纸本)9788395918384

Recently stochastic methods have become very important tool for high performance computing of very high dimensional problems in computational finance. the advantages and disadvantages of the different highly efficient stochastic methods for multidimensional integrals related to evaluation of European style options will be analyzed. Multidimensional integrals up to 100 dimensions related to European options will be computed with highly efficient optimized lattice rules.

关键词： computer science Portable computers high performance computing Lattices Europe Finance Pricing

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Fourier spectrum-based signature test: A genetic CAD toolbox for reliable RF testing using low-performance test resources

Fourier spectrum-based signature test: A genetic CAD toolbox...

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16th Asian Test symposium

作者： Srinivasan, G. Chatterjee, A. Natarajan, V. Georgia Inst Technol Atlanta GA 30332 USA

ISBN: (纸本)9780769528908

At the present time, coordinated EDA tools for RF/mixed-signal pin test do not exist. In this paper, a CAD tool for efficient production testing of high-performance RF systems using low-cost baseband ATE is presented the CAD tool consists of a custom developed genetic ATPG for spectral (Fourier spectrum) signature-based alternate (to full specification-based tests) test of RF systems and involves co-simulation of scalable behavioral-level models of the RF System-Under-Test, baseband ATE test instrumentation, loadboard resources, and DfT resources for fast test vector optimization/generation. the CAD tool also enables the evaluation of various low-cost ATE architectures on the impact of the generated tests to provide a cost-effective solution.

关键词： computer aided design

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Catching accurate profiles in hardware 9

Catching accurate profiles in hardware

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9th International symposium on high-performance computer architecture

作者： Narayanasamy, S Sherwood, T Sair, S Calder, B Varghese, G Univ Calif San Diego Dept Comp Sci & Engn San Diego CA 92103 USA

ISBN: (纸本)0769518710

Run-time optimization is one of the most important ways of getting performance out of modern processors. Techniques such as prefetching, trace caching, memory disambiguation etc., are all based upon the principle of observation followed by adaptation, and all make use of some sort of profile information gathered at run-time. Programs are very complex, and the real trick in generating useful run-time profiles is sifting through all the unimportant and infrequently occurring events to find those that are important enough to warrant optimization. In this paper, we present the Multi-Hash architecture to catch important events even in the presence of extensive noise. Multi-hash uses a small amount of area, between 7 to 16 Kilobytes, to accurately capture these important events in hardware, without requiring any software support. this is achieved using multiple hash tables for the filtering, and interval-based profiling to help identify how important an event is in relationship to all the other events. We evaluate our design for value and edge profiling, and show that over a set of benchmarks, we get an average error less than 1%.

关键词： computer architecture computer errors computer science Filtering Hardware Prefetching Runtime Software systems Software tools System software

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Accelerate GPU Concurrent Kernel Execution by Mitigating Memory Pipeline Stalls 24

Accelerate GPU Concurrent Kernel Execution by Mitigating Mem...

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24th IEEE International symposium on high performance computer architecture (HPCA)

作者： Dai, Hongwen Lin, Zhen Li, Chao Zhao, Chen Wang, Fei Zheng, Nanning Zhou, Huiyang North Carolina State Univ Dept Elect & Comp Engn Raleigh NC 27695 USA Xi An Jiao Tong Univ Sch Elect & Informat Engn Xian Shaanxi Peoples R China

ISBN: (纸本)9781538636596

Following the advances in technology scaling, graphics processing units (GPUs) incorporate an increasing amount of computing resources and it becomes difficult for a single GPU kernel to fully utilize the vast GPU resources. One solution to improve resource utilization is concurrent kernel execution (CKE). Early CKE mainly targets the leftover resources. However, it fails to optimize the resource utilization and does not provide fairness among concurrent kernels. Spatial multitasking assigns a subset of streaming multiprocessors (SMs) to each kernel. Although achieving better fairness, the resource underutilization within an SM is not addressed. thus, intra-SM sharing has been proposed to issue thread blocks from different kernels to each SM. However, as shown in this study, the overall performance may be undermined in the intra-SM sharing schemes due to the severe interference among kernels. Specifically, as concurrent kernels share the memory subsystem, one kernel, even as computing-intensive, may starve from not being able to issue memory instructions in time. Besides, severe L1 D-cache thrashing and memory pipeline stalls caused by one kernel, especially a memory-intensive one, will impact other kernels, further hurting the overall performance. In this study, we investigate various approaches to overcome the aforementioned problems exposed in intra-SM sharing. We first highlight that cache partitioning techniques proposed for CPUs are not effective for GPUs. then we propose two approaches to reduce memory pipeline stalls. the first is to balance memory accesses of concurrent kernels. the second is to limit the number of inflight memory instructions issued from individual kernels. Our evaluation shows that the proposed schemes significantly improve the weighted speedup of two state-of-the-art intra-SM sharing schemes, Warped-Slicer and SMK, by 24.6% and 27.2% on average, respectively, with lightweight hardware overhead.

关键词： Kernel Graphics processing units Pipelines Instruction sets Resource management Benchmark testing computer architecture

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BIPROCESSOR CONFIGURATION WIth ALTERNATING HIERARCHY FOR high SPEED PROCESS CONTROL.

Conference Proceedings - Annual Symposium on Computer Archit...

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Conference proceedings - Annual symposium on computer architecture 1980年 443-449页

作者： Borangiu, th. Dobrescu, R.

A biprocessor control configuration dedicated to high speed technological processes, such as electrical drives, is presented. In the proposed structure, a specialized asynchronous interface connects two INTEL 8085 microprocessors, the first of which performs the frequency control for two electric stepper motors, according to numerical two-axes interpolating algorithms, while the second works out the optimal controls (feedrate, speed) for a class of nonlinear performance indexes, subject to nonlinear constraints of inequality type. Any one of the two microprocessors, logically placed on priority based hierarchical levels, can take hold of the master position in the control system and communicate over an eight bit data bus with the subordinate processing unit (slave). Real time processing diagrams are worked out, making therefore possible parallel high speed processing of both complex computing functions and of advanced optimization algorithms. Final remarks are made concerning some practical results for machine tools.

关键词： PROCESS CONTROL

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LightTrader: A Standalone high-Frequency Trading System with Deep Learning Inference Accelerators and Proactive Scheduler 29

LightTrader: A Standalone High-Frequency Trading System with...

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29th IEEE International symposium on high-performance computer architecture (HPCA)

作者： Yoo, Sungyeob Kim, Hyunsung Kim, Jinseok Park, Sunghyun Kim, Joo-Young Oh, Jinwook Korea Adv Inst Sci & Technol Daejeon South Korea Rebellions Inc Seoul South Korea

ISBN: (纸本)9781665476522

Recent research shows that artificial intelligence (AI) algorithms can dramatically improve the profitability of high-frequency trading (HFT) with accurate market prediction, overcoming the limitation of conventional latency-oriented approaches. However, it is challenging to integrate the computationally intensive AI algorithm into the existing trading pipeline due to its excessively long latency and insufficient throughput, necessitating a breakthrough in hardware. Furthermore, harsh HFT environments such as bursty data traffic and stringent power constraint make it even more difficult to achieve systemlevel performance without missing crucial market signals. In this paper, we present LightTrader, the world's first AIenabled HFT system that incorporates an FPGA and custom AI accelerators for short-latency-high-throughput trading systems. Leveraging the computing power of brand-new AI accelerators fabricated in TSMC's 7nm FinFET technology, LightTrader optimizes the tick-to-trade latency and response rate for stock market data. the AI accelerators, adopting Coarse-Grained Reconfigurable Array (CGRA) architecture, which maximizes the hardware utilization from the flexible dataflow architecture, achieve a throughput of 16 TFLOPS and 64 TOPS. In addition, we propose both workload scheduling and dynamic voltage and frequency scaling (DVFS) scheduling algorithms to find an optimal offloading strategy under bursty market data traffic and limited power condition. Finally, we build a reliable and rerunnable simulation framework that can back-test the historical market data, such as Chicago Mercantile Exchange (CME), to evaluate the LightTrader system. We thoroughly explore the performance of LightTrader when the number of AI accelerators, power conditions, and complexity of deep neural network models change. As a result, LightTrader achieves 13.92x and 7.28x speed-up of AI algorithm processing compared to existing GPU-based, FPGA-based systems, respectively. LightTrader wit

关键词： Commerce

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A low cost method for determining the entire network path bandwidths of indirect high-performance computer networks 16

A low cost method for determining the entire network path ba...

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16th IEEE International symposium on Parallel and Distributed Processing with Applications, 17th IEEE International Conference on Ubiquitous computing and Communications, 8th IEEE International Conference on Big Data and Cloud computing, 11th IEEE International Conference on Social computing and Networking and 8th IEEE International Conference on Sustainable computing and Communications, ISPA/IUCC/BDCloud/SocialCom/SustainCom 2018

作者： Yan, Baicheng Zhou, Yi Xiao, Limin Yang, Zhang Wu, Hongyu Wei, Bing School of Computer Science and Engineering Beihang University Beijing100191 China Institute of Applied Physics and Computational Mathematics Beijing100094 China

ISBN: (纸本)9781728111414

Bandwidth is an important performance metric for high-performance computer network (HINET). How to determine large-scale HINET path bandwidths quickly and precisely is a highly pivotal challenge for parallel application performance analysis and prediction, optimizing end-to-end data transport performance, network management, etc. However, it is hard to determine the entire network point-to-point bandwidths of HINET since it often costs amounts of measurement time. Existing path bandwidth measurement methods focus on improving the accuracy of single path bandwidth measurement, however, lack considerations for reducing the entire network path bandwidths measurement times. To address this issue, we present an efficient method to generate the full-scale point-to-point bandwidth measurement plan for rapidly obtaining each path bandwidth in HINET. For evaluating, a source routing Fat-tree simulator and comprehensive experiments were conducted for different application scenarios. Both experimental and analysis showed that our method can reduce the measurement times significantly. In particular, compared to the exhaustive method, the measurement times of our method are one in 185 for the entire path bandwidth fault and can save 95% measurement times in 1024 nodes network with synthetic traffic. © 2018 IEEE.

关键词： Bandwidth

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Designing Next Generation Clusters: Evaluation of InfiniBand DDR/QDR on Intel computing Platforms

Designing Next Generation Clusters: Evaluation of InfiniBand...

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17th symposium on high-performance Interconnects

作者： Subramoni, Hari Koop, Matthew Panda, Dhabaleswar K. Ohio State Univ Dept Comp Sci & Engn Columbus OH 43210 USA

ISBN: (纸本)9781424452026

Clusters based on commodity components continue to be very popular for high-performance computing (HPC). these clusters must be careful to balance both computational as well as I/O requirements of applications. this I/O requirement is generally fulfilled by a high-speed interconnect such as InfiniBand. the balance of computational and I/O performance is often changing, with the latest change being made by the Intel "Nehalem" architecture that can dramatically increase computing power In this paper we explore how this balance has changed and how different speeds of InfiniBand interconnects including Double Data Rate (DDR) and Quad Data Rate (QDR) InfiniBand HCAs. We explore microbenchmarks, the "communication balance" ratio of intra-node to inter-node performance as well as end application performance. We show up to 10% improvement when using a QDR interconnect for Nehalem systems versus a DDR interconnect on the NAS Parallel Benchmarks. We also see up to 25% performance gain with the HPCC randomly ordered ring bandwidth benchmark.

关键词： Benchmarking

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