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Memory-Aware Circuit Overlay NoCs for Latency Optimized GPGPU architectures

Memory-Aware Circuit Overlay NoCs for Latency Optimized GPGP...

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International symposium on Quality Electronic Design

作者： Venkata Yaswanth Raparti Sudeep Pasricha Department of Electrical and Computer Engineering Colorado State University

ISBN: (纸本)9781509012145

the growing parallelism in most of today's applications has led to an increased demand for parallel computing in processors. General Purpose Graphics Processing Units (GPGPUs) have been used extensively to provide the necessary computation for highly parallel applications. GPGPUs generate huge volumes of network traffic between memory controllers (MCs) and cores. As a result, the network-on-chip (NoC) fabric can become a performance bottleneck, especially for memory intensive applications on GPGPUs. Traditional mesh-based NoC topologies are not suitable for GPGPUs as they possess high network latency that leads to congestion at MCs and an increase in application execution time. In this paper, we propose a novel memory-aware circuit overlay NoC that exploits characteristics of traffic in GPGPUs to eliminate router arbitration at each hop. Our experimental results show that our approach yields an improvement of 40-75% in NoC latency, 20-70% in execution time, and 10-65% in overall energy consumption compared to the state-of-the-art.

关键词： Latency execution time Overlay network delay traffic network PARALLEL PROCESSING (computerS) energy consumption Memory Memory architecture MCS gene core Traffic

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Architectural Reliability Estimation using Design Diversity 16

Architectural Reliability Estimation using Design Diversity

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16th International symposium on Quality Electronic Design (ISQED)

作者： Wang, Zheng Yang, Liu Chattopadhyay, Anupam Rhein Westfal TH Aachen Inst Commun Technol & Embedded Syst ICE Aachen Germany Nanyang Technol Univ Sch Comp Engn Singapore Singapore

ISBN: (纸本)9781479975815

Reliability has emerged as an important design criterion due to shrinking device dimensions. Several reliability estimation techniques have been proposed which apply either fault injection or analytical methods. Among all such techniques, design diversity, which is initially proposed to protect system from common-mode failures using redundant copies of different implementation, has been applied to quantify the availability of a duplex system in circuit-level design. In this paper, we utilize the design diversity metric for architecture-level reliability analysis and validate the concept with diverse processing architectures. A novel graph based analysis is introduced which jointly quantifies circuit-level design diversity and architecture-level operator exclusiveness. the proposed approach is demonstrated on several embedded computing architectures through the analysis on architecture and application-level design diversity, as well as estimation of system Mean-Time-to-Failure.

关键词： Design Diversity Reliability Estimation high-level architecture Design

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performance and Power Analysis of high-Density Multi-GPGPU architectures: A Preliminary Case Study 17

Performance and Power Analysis of High-Density Multi-GPGPU A...

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2015 IEEE 17th International Conference on high performance computing and Communications (HPCC)

作者： Gao, Yuxiang Iqbal, Saeed Zhang, Peng Qiu, Meikang Dell Inc Global Solut Engn Grp Round Rock TX 78682 USA SUNY Stony Brook Dept Biomed Engn Stony Brook NY 11794 USA Pace Univ Dept Comp Sci New York NY 10038 USA

ISBN: (纸本)9781479989379

A system architecture with high-density general purpose graphic processing unit (GPGPU) is emerging as a promising solution that can offer high compute performance and performance-per-watt for building cluster supercomputers. the raw compute power of these heterogeneous systems greatly exceeds the current prevailing homogenous systems, motivating their rapid adoption. these heterogeneous systems do however increase the complexity of developing parallel applications and there is a need to investigate the compute performances and associated power consumption of common benchmarks and scientific computing applications. In this paper, we present the performance and power studies through using the Dell C4130 server that integrates up to 4 GPGPU cards and NVIDIA GPGPU K80 is used. the high performance Linpack (HPL) and molecular dynamics (MD) simulators including NAMD, LAMMPS and GROMACS are tested. through comparing 4-K80 and 2-Xeon E5-2690 v3 systems, we show that: (1) for HPL tests, the 4-GPU server delivers up to 7 TFLOPS that is 9 times faster than the 2-CPU system and its power efficiency is 4 GFLOPS per Watt;(2) for MD tests, NAMD on 4-GPU server achieves 7.8 times speedup and it uses 2.3 times power consumption compared to 2-CPU system;and LAMMPS achieves 16 times speedup and it uses 2.6 times power consumption;and GROMACS achieves 3.3 times speed up and it uses 2.6 times power consumption. these preliminary results demonstrated that the novel high-density multi-GPGPU architecture offers high performances for computing intensive applications and molecular simulators with superior power efficiencies in a space efficient design. In future, such heterogeneous architecture could be a powerful alternative solution for next generation supercomputer systems.

关键词： dense GPGPU architecture parallel computer architecture performance evaluations GPGPU power consumption

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Fast Support for Unstructured Data Processing: the Unified Automata Processor 48

Fast Support for Unstructured Data Processing: the Unified A...

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48th Annual IEEE/ACM International symposium on Microarchitecture (MICRO)

作者： Fang, Yuanwei Hoang, Tung T. Becchi, Michela Chien, Andrew A. Univ Chicago Dept Comp Sci Chicago IL 60637 USA Univ Missouri Dept Elect & Comp Engn Columbia MO 65211 USA Univ Chicago Comp Sci MCS Argonne Natl Lab Chicago IL 60637 USA

ISBN: (纸本)9781450340342

We propose the Unified Automata Processor (UAP), a new architecture that provides general and efficient support for finite automata (FA). the UAP supports a wide range of existing finite automata models (DFAs, NFAs, A-DFAs, JFAs, counting-DFAs, and counting-NFAs), and future novel FA models. Evaluation on realistic workloads shows that UAP implements all models efficiently, achieving line rates 94.5% of ideal. A single UAP lane delivers line rates 50x greater than software approaches on CPUs and GPUs. Scaling UAP to 64 lanes achieves FA transition throughputs as high as 295 Gbps, more than 100x higher than CPUs and GPUs, and even exceeding ASIC approaches such as IBM's RegX by 6x. With efficient support for multiple input streams, UAP achieves throughputs that saturate even high speed stacked DRAM memory systems. the UAP design and implementation is efficient in instructions executed, memory references, and energy. UAP achieves a 1.2 Ghz clock rate (32nm TSMC CMOS), and a 64-lane UAP requires only 2.2 mm(2) and 563 mW. At these levels of performance and energy-efficiency, UAP is a promising candidate for integration into general-purpose computing architectures.

关键词： computer architecture Processor Finite Automata Data Processing Pattern-matching Energy-efficient Custom architecture

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Model-driven optimisation of memory hierarchy and multithreading on GPUs 13th

Model-driven optimisation of memory hierarchy and multithrea...

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proceedings of the 13th Australasian symposium on Parallel and Distributed computing, AusPDC 2015

作者： Haigh, Andrew A. McCreath, Eric C. Research School of Computer Science The Australian National University Canberra Australia

ISBN: (纸本)9781921770456

Due to their potentially high peak performance and energy effciency, GPUs are increasingly popular for scientific computations. However, the complexity of the architecture makes it difficult to write code that achieves high performance. Two of the most important factors in achieving high performance are the usage of the GPU memory hierarchy and the way in which work is mapped to threads and blocks. the dominant frameworks for GPU computing, CUDA and OpenCL, leave these decisions largely to the programmer. In this work, we address this in part by proposing a technique that simultaneously manages use of the GPU lowlatency shared memory and chooses the granularity with which to divide the work (block size). We show that a relatively simple heuristic based on an abstraction of the GPU architecture is able to make these decisions and achieve average performance within 17% of an optimal configuration on an NVIDIA Tesla K20. © 2015, Australian computer Society, Inc.

关键词： Graphics processing unit

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BFC: high-performance distributed big-file cloud storage based on key-value store 16

BFC: High-performance distributed big-file cloud storage bas...

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16th IEEE/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed computing, SNPD 2015

作者： Nguyen, thanh Trung Vu, Tin Khac Nguyen, Minh Hieu Information Technology Faculty Le Quy Don Technical University Ha Noi Viet Nam VNG Research Viet Nam

ISBN: (纸本)9781479986767

Nowadays, cloud-based storage services are rapidly growing and becoming an emerging trend in data storage field. there are many problems when designing an efficient storage engine for cloud-based systems with some requirements such as big-file processing, lightweight meta-data, low latency, parallel I/O, deduplication, distributed, high scalability. Key-value stores played an important role and showed many advantages when solving those problems. this paper presents about Big File Cloud (BFC) with its algorithms and architecture to handle most of problems in a big-file cloud storage system based on key-value store. It is done by proposing low-complicated, fixed-size meta-data design, which supports fast and highly-concurrent, distributed file I/O, several algorithms for resumable upload, download and simple data deduplication method for static data. this research applied the advantages of ZDB - an in-house key-value store which was optimized with auto-increment integer keys for solving big-file storage problems efficiently. the results can be used for building scalable distributed data cloud storage that support big-file with size up to several terabytes. © 2015 IEEE.

关键词： Integer programming

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Cache line aware optimizations for ccnuma systems 15

Cache line aware optimizations for ccnuma systems

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24th ACM symposium on high-performance Parallel and Distributed computing, HPDC 2015

作者： Ramos, Sabela Hoefler, Torsten Computer Architecture Group University of A Coruña Spain Scalable Parallel Computing Lab ETH Zurich Switzerland

ISBN: (纸本)9781450335508

Current shared memory systems utilize complex memory hi-erarchies to maintain scalability when increasing the num-ber of processing units. Although hardware designers aim to hide this complexity from the programmer, ignoring the detailed architectural characteristics can harm performance significantly. We propose to expose the block-based design of caches in parallel computers to middleware designers to allow semi-automatic performance tuning with the system-atic translation from algorithms to an analytic performance model. For this, we design a simple interface for cache line aware (CLa) optimization, a translation methodology, and a full performance model for cache line transfers in ccNUMA systems. Algorithms developed using CLa design perform up to 14x better than vendor and open-source libraries, and 2x better than existing ccNUMA optimizations. © 2015 ACM.

关键词： Middleware

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Asian Option Pricing on Intel® MIC architecture 13th

Asian Option Pricing on Intel® MIC Architecture

引用

proceedings of the 13th Australasian symposium on Parallel and Distributed computing, AusPDC 2015

作者： Li, Shuo Lin, James Developer Relations Division Software and Services Group Intel Corporation 2111 NE 25th Ave PortlandOR97124 United States Center for High Performance Computing Shanghai Jiaotong University 800 Dongchuan Rd Shanghai200240 China

ISBN: (纸本)9781921770456

In this paper, we discuss the problem of pricing one exotic option, the strong path dependent Asian option using the Black-Scholes model and compare how the pricing algorithm can be implemented on Intel® Many Integrated Core or MIC architecture and achieve impressive performance gains. We can demonstrate that a 2-year contract with 252 times steps and 1,000,000 samples can be priced in approximately one fifth of a second on Intel® Xeon Phi™ 7120p. © 2015, Australian computer Society, Inc.

关键词： Costs

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Achieving performance isolation with lightweight co-kernels 15

Achieving performance isolation with lightweight co-kernels

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24th ACM symposium on high-performance Parallel and Distributed computing, HPDC 2015

作者： Ouyang, Jiannan Kocoloski, Brian Lange, John Pedretti, Kevin Department of Computer Science University of Pittsburgh United States Center for Computing Research Sandia National Laboratories United States

ISBN: (纸本)9781450335508

performance isolation is emerging as a requirement for high performance computing (HPC) applications, particularly as HPC architectures turn to in situ data processing and application composition techniques to increase system throughput. these approaches require the co-location of disparate workloads on the same compute node, each with different resource and runtime requirements. In this paper we claim that these workloads cannot be effectively managed by a single Operating System/Runtime (OS/R). therefore, we present Pisces, a system software architecture that enables the co-existence of multiple independent and fully isolated OS/Rs, or enclaves, that can be customized to address the disparate requirements of next generation HPC workloads. Each enclave consists of a specialized lightweight OS cokernel and runtime, which is capable of independently managing partitions of dynamically assigned hardware resources. Contrary to other co-kernel approaches, in this work we consider performance isolation to be a primary requirement and present a novel co-kernel architecture to achieve this goal. We further present a set of design requirements necessary to ensure performance isolation, including: (1) elimination of cross OS dependencies, (2) internalized management of I/O, (3) limiting cross enclave communication to explicit shared memory channels, and (4) using virtualization techniques to provide missing OS features. the implementation of the Pisces co-kernel architecture is based on the Kitten Lightweight Kernel and Palacios Virtual Machine Monitor, two system software architectures designed specifically for HPC systems. Finally we will show that lightweight isolated co-kernels can provide better performance for HPC applications, and that isolated virtual machines are even capable of outperforming native environments in the presence of competing workloads. © 2015 ACM.

关键词： Virtual machine

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Centiman: Elastic, high performance Optimistic Concurrency Control by Watermarking 6

Centiman: Elastic, High Performance Optimistic Concurrency C...

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Conference on 6th ACM symposium on Cloud computing (SoCC 2015)

作者： Ding, Bailu Kot, Lucja Demers, Alan Gehrke, Johannes Cornell Univ Ithaca NY 14853 USA Cornell Univ Microsoft Corp Ithaca NY 14853 USA

ISBN: (纸本)9781450336512

We present Centiman, a system for high performance, elastic transaction processing in the cloud. Centiman provides serializability on top of a key-value store with a lightweight protocol based on optimistic concurrency control (OCC). Centiman is designed for the cloud setting, with an architecture that is loosely coupled and avoids synchronization wherever possible. Centiman supports sharded transaction validation;validators can be added or removed on-the-fly in an elastic manner. Processors and validators scale independently of each other and recover from failure transparently to each other. Centiman's loosely coupled design creates some challenges: it can cause spurious aborts and it makes it difficult to implement common performance optimizations for read-only transactions. To deal with these issues, Centiman uses a watermark abstraction to asynchronously propagate information about transaction commits through the system. In an extensive evaluation we show that Centiman provides fast elastic scaling, low-overhead serializability for read-heavy workloads, and scales to millions of operations per second.

关键词： optimistic concurrency control elastic transaction processing sharded validation

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