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检索条件"任意字段=Proceedings - 16th Symposium on Computer Architecture and High Performance Computing"

共 2312 条记录，以下是51-60 订阅

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Evaluation of Coarse-to-Fine Spatio-Temporal Information Fusion (CF-STIF) Network

Evaluation of Coarse-to-Fine Spatio-Temporal Information Fus...

引用

IEEE Latin American symposium on Circuits and Systems (LASCAS)

作者： Luis Carlos Linares Gilberto Kreisler Daniel Palomino Guilherme Corrêa Bruno Zatt Video Technology Research Group (ViTech) Graduate Program in Computing (PPGC) Federal University of Pelotas (UFPel) Pelotas Brazil

ISBN: (数字)9798331522124

ISBN: (纸本)9798331522131

this paper presents an evaluation of the Coarse-to-Fine Spatio-Temporal Information Fusion (CF-STIF) network for enhancing the quality of compressed videos across multiple codecs, including HEVC, VVC, VP9, and AV1. the CF-STIF network leverages spatiotemporal fusion and deep learning techniques to reduce compression artifacts and improve video quality. the evaluation extends existing methods by employing multiple quality metrics such as PSNR, SSIM, LPIPS. the CF-STIF network has been integrated with the Spatio-Temporal Deformable Fusion (STDF) training scheme in order to execute the model. Results demonstrate that CF-STIF achieves the highest quality improvements for HEVC-encoded videos, with an average PSNR increase of 0.813 dB and superior visual quality as measured by SSIM. However, the performance significantly drops for other codecs, particularly AV1, highlighting the need for future adaptations to optimize CF-STIF for diverse compression standards.

关键词： Training Deep learning Adaptation models Visualization Codecs Computational modeling computer architecture Quality assessment Standards Videos

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proceedings 16th Annual International symposium on high performance computing Systems and Applications

Proceedings 16th Annual International Symposium on High Perf...

引用

IEEE International symposium on high performance computing Systems and Applications (HPCS)

the following topics were dealt with: multiple processor architectures; networks and grids; non-numerical algorithms including sorting and graph algorithms; computation models; numerical parallel algorithms; scheduling and performance evaluation including compiling, thread migration and meta computing; and high performance computing applications including computational chemistry, command and control, and finance.

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Energy-Efficient PRNG Based on a Discrete-Space Chaotic Map Using an AxRMU Multiplier

Energy-Efficient PRNG Based on a Discrete-Space Chaotic Map ...

引用

IEEE Latin American symposium on Circuits and Systems (LASCAS)

作者： João Inácio Moreira Bezerra Morgana Macedo da Rosa Leonardo Antonietti Vinícius V. Camargo Alexandre Molter Rafael Iankowski Soares Technology Development Center Federal University of Pelotas (UFPel) Pelotas Brazil Porto Alegre Brazil Institute of Physics and Mathematics Federal University of Pelotas (UFPel) Pelotas Brazil

ISBN: (数字)9798331522124

ISBN: (纸本)9798331522131

the development of pseudo-random number genera-tors (PRNG) has attracted significant attention from researchers, due to, among others, its application to cryptographic systems. An effective method for developing a PRNG involves utilizing chaotic systems, however, the use of continuous-space chaotic systems makes the PRNG inefficient in terms of energy consumption. In this context, we propose an energy-efficient PRNG based on a discrete-space chaotic map employing approximate computation. Using an Approximate Radix-4 Multiplier Unit in the map's implementation reduces the complexity of its single complex calculation, which is an integer multiplication, aiding both its energy efficiency and its performance. the fast version of the PRNG has a 4.39 times increase in throughput compared to the state-of-the-art, along with a 74% reduction in energy consumption. the lightweight version achieves a 85.6% area reduction and 90.57% lower energy consumption, with only a 37% throughput reduction. the use of approximate computing does not affect the PRNG's deterministic behavior, which is essential to applications in cryptography. the randomness of the generated sequences was verified through NIST tests.

关键词： Energy consumption Circuits and systems Approximate computing computer architecture NIST throughput Energy efficiency Generators Complexity theory Cryptography

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A LUT-Based Calibration Approach of the ESP32 ADC for a Power Quality Analyzer

A LUT-Based Calibration Approach of the ESP32 ADC for a Powe...

引用

IEEE Latin American symposium on Circuits and Systems (LASCAS)

作者： Kélton da Rosa Severo José Wagner M. Kaehler Crístian Müller Alessandro G. Girardi Natalia Braun Chagas Paulo César C. de Aguirre Integrated Exploration of Energetic Resources - EIRE Computer Architecture and Microelectronics Group - GAMA Federal University of Pampa - UNIPAMPA Alegrete Rio Grande do Sul Brazil

ISBN: (数字)9798331522124

ISBN: (纸本)9798331522131

Low-cost electronic circuits for Internet-of-things (IoT) applications are based on system-on-chips (SoCs) with wireless connectivity. Among them, the ESP32 is a well-known microcontroller family adopted by a wide developer community. this SoC is selected in this work to implement a wireless remote power meter for energy quality analysis. the ESP32 provides a 12-bit analog-to-digital converter (ADC), but its performance is not suitable for precision applications. In this work, an offline ADC calibration is performed and the correction codes are stored in the ESP32 internal memory to optimize the analog-to-digital conversion to meet high-precision energy quality measurement standards. the results before and after calibration are shown to verify the effects of ADC linearity especially when measuring total harmonic distortion. We demonstrate that the ADC nonlinearity distorts the signal and introduce odd harmonic components that affect the reliability of the measured values, especially at the end of the scale. the look-up table based correction method can mitigate these effects and allows the use of a low-cost ADC with poor linearity in high-precision applications.

关键词： Wireless communication Meters Total harmonic distortion Linearity Calibration Table lookup System-on-chip Power system reliability Reliability Analog-digital conversion

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Combining a shared-memory high performance computer and a heterogeneous cluster for the simulation of light interaction with human skin

Combining a shared-memory high performance computer and a he...

引用

16th symposium on computer architecture and high performance computing

作者： Krishnaswamy, A Baranoski, GVG Univ Waterloo Sch Comp Sci Nat Phenomena Simulat Grp Waterloo ON N2L 3G1 Canada

ISBN: (纸本)0769522408

When light interacts with human skin, a complex and involved process begins as the light is absorbed and propagated by cells, fibers and other microscopic materials. this interaction happens countless times each day and its accurate simulation is essential to biomedical and computer graphics applications. Simulating this interaction is computationally intensive, yet highly suitable to parallelization. this paper describes the use of both a shared-memory high performance computer and a heterogeneous cluster to accelerate these simulations. With a description of the parallel software used, we present results to show the performance gains from using such a hybrid approach.

关键词： computer systems

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A cluster-based strategy for scheduling task on heterogeneous processors

A cluster-based strategy for scheduling task on heterogeneou...

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16th symposium on computer architecture and high performance computing

作者： Boeres, C Viterbo, J Rebello, VEF Univ Fed Fluminense Inst Comp Niteroi RJ Brazil

ISBN: (纸本)0769522408

Efficient task scheduling is fundamental for parallel applications to achieve good performance on distributed systems. While extensive work exists for scheduling tasks on homogeneous processors, fewer algorithms exist for the more common problem of scheduling in heterogeneous processor environments. In this paper we propose coupling a replication-based clustering heuristic for homogeneous processors, with a mechanism to map the generated clusters to the heterogeneous environment. Experimental results show that this strategy compares favourably in terms of the makespan with traditional list scheduling approaches to this problem, particularly when communication costs are high.

关键词： Distributed computer systems

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A performance evaluation of a quorum-based state-machine replication algorithm for computing grids

A performance evaluation of a quorum-based state-machine rep...

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16th symposium on computer architecture and high performance computing

作者： Busca, JM Bertier, M Belkouch, F Sens, P Arantes, L Univ Paris 06 CNRS LIP6 Paris France

ISBN: (纸本)0769522408

Quorum systems are well-known tools that improve the performance and the availability of distributed systems. In this paper we explore their use as a means to achieve low response time for network services that are replicated and accessed over computing grids. To that end, we propose both a quorum construction and a quorum-based state-machine replication algorithm that tolerates crash failures in a partially synchronous model. We show through the evaluation of a real implementation that although simple, this quorum construction and replication algorithm exhibit a response time 20% lower than that of a regular active replication algorithm in appropriate conditions.

关键词： Distributed computer systems

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Optimizations for compiled simulation using instruction type information

Optimizations for compiled simulation using instruction type...

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16th symposium on computer architecture and high performance computing

作者： Bartholomeu, M Azevedo, R Rigo, S Araujo, G Univ Campinas Inst Comp Campinas SP Brazil

ISBN: (纸本)0769522408

the design of new architectures can be simplified with the use of retargetable instruction set simulation tools, which can validate the design decisions in the design exploration cycle with high flexibility and reduced cost. the growing system complexity makes the traditional approach inefficient for todays architectures. Compiled simulation techniques make use of a priori knowledge to accelerate the simulation, with the highest efficiency achieved by employing static scheduling techniques. this paper presents our approach to the static scheduling compiled simulation technique that is 90% faster than the best published performance results. It also introduces two novel optimization techniques based on instruction type information that further increase the simulation speed by more than 100%. the so called Fast Static Compiled Simulation (FSCS) technique applicability will be demonstrated by the use of the SPARC and MIPS architectures.

关键词： computer architecture

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ArchC:: A systemC-based architecture description language

ArchC:: A systemC-based architecture description language

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16th symposium on computer architecture and high performance computing

作者： Rigo, S Araújo, G Bartholomeu, M Azevedo, R Univ Estadual Campinas Inst Comp Comp Syst Lab Campinas SP Brazil

ISBN: (纸本)0769522408

this paper presents an architecture description language (ADL) called ArchC, which is an open-source SystemC-based language that is specialized for processor architecture description. Its main goal is to provide enough information, at the right level of abstraction, in order to allow users to explore and verify new architectures, by automatically generating software tools like simulators and coverification interfaces. ArchC's key features are a storage based co-verification mechanism that automatically checks the consistency of a refined ArchC model against a reference (functional) description, memory hierarchy modeling capability, the possibility of integration with other SystemC IPs and the automatic generation of high-level SystemC simulators. We have used ArchC to synthesize both functional and cycle-based simulators for the MIPS, Intel 8051 and SPARC V8 processors, as well as functional models of modem architectures like TMS320C62x, XScale and PowerPC.

关键词： computer architecture

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Design space exploration using T&D-Bench

Design space exploration using T&D-Bench

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16th symposium on computer architecture and high performance computing

作者： Soares, SN Wagner, FR UFRGS UCS PGCC CARVI Porto Alegre RS Brazil

ISBN: (纸本)0769522408

this paper presents T&D-Bench - Teaching and Design Workbench, a software infrastructure for modeling and simulation of state-of-the-art processors. It combines features that simplify and accelerate the processor design process without restricting the designer possibilities, thus representing a good trade off for educational and research purposes that is not found in other environments. In T&D-Bench, a new model is constructed by the designer using a script language to define micro-architecture, instruction set, and timing aspects of the processor. these scripts can be produced by a graphical front-end, and a Java simulator targeted at the modeled processor is automatically built from the scripts. this approach can fit well the requirements imposed by the educational environment. Fine-tuning adjustments or the description of more complex processor mechanisms can be achieved by means of modifications in selected parts of the software infrastructure.

关键词： computer software

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