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Lock-free GaussSieve for linear speedups in parallel high performance SVP calculation 26

Lock-free GaussSieve for linear speedups in parallel high pe...

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26th International symposium on computer architecture and high performance computing, SBAC-PAD 2014

作者： Mariano, Artur Timnat, Shahar Bischof, Christian Institute for Scientific Computing Technische Universität Darmstadt Darmstadt Germany Department of Computer Science Technion - Israel Institute of Technology Haifa Israel

ISBN: (纸本)9781479969043

Lattice-based cryptography became a hot-topic in the past years because it seems to be quantum immune, i.e., resistant to attacks operated with quantum computers. the security of lattice-based cryptosystems is determined by the hardness of certain lattice problems, such as the Shortest Vector Problem (SVP). thus, it is of prime importance to study how efficiently SVP-solvers can be implemented. this paper presents a parallel shared-memory implementation of the GaussSieve algorithm, a well known SVP-solver. Our implementation achieves almost linear and linear speedups with up to 64 cores, depending on the tested scenario, and delivers better sequential performance than any other disclosed GaussSieve implementation. In this paper, we show that it is possible to implement a highly scalable version of GaussSieve on multi-core CPU-chips. the key features of our implementation are a lock-free singly linked list, and hand-tuned, vectorized code. Additionally, we propose an algorithmic optimization that leads to faster convergence. © 2014 IEEE.

关键词： Quantum computers

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Efficient virtual channel organization and congestion avoidance in multicore NoC systems 26

Efficient virtual channel organization and congestion avoida...

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26th IEEE International symposium on computer architecture and high performance computing Workshops, SBAC-PADW 2014

作者： Oveis-Gharan, Masoud Khan, Gul N. Electrical and Computer Engineering Ryerson University 350 Victoria St TorontoONM5B 2K3 Canada

ISBN: (纸本)9781479970148

Dynamically Allocated Multi Queues (DAMQ) is an effective mechanism to achieve Virtual Channel (VC) based flow control with maximum buffer utilization in multi-core Network-on-Chip (NoC) systems. We present a new methodology to remedy some of the drawbacks of DAMQ technique. the architectural design of a DAMQ router inputport that uses minimal hardware is introduced. Our input-port design saves 70% of combinational-logic and 14.7% register hardware as compared to conventional Link-List input-port. We also present an efficient mechanism to remove traffic congestion in on-chip communication for NoC systems. It improves latency and throughput by 30% and 23% respectively as compared to conventional dynamic Virtual Channel design. © 2014 IEEE.

关键词： Traffic congestion

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RACB: Resource aware cache bypass on GPUs 26

RACB: Resource aware cache bypass on GPUs

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26th IEEE International symposium on computer architecture and high performance computing Workshops, SBAC-PADW 2014

作者： Dai, Hongwen Kartsaklis, Christos Li, Chao Janjusic, Tomislav Zhou, Huiyang Department of Electrical and Computer Engineering North Carolina State University Raleigh United States Computer Science and Mathematics Division Oak Ridge National Laboratory Oak Ridge United States

ISBN: (纸本)9781479970148

Caches are universally used in computing systems to hide long off-chip memory access latencies. Unlike CPUs, massive threads running simultaneously on GPUs bring a tremendous pressure on memory hierarchy. As a result, the limitation of cache resources becomes a bottleneck for a GPU to exploit thread-level parallelism (TLP) and memory-level parallelism (MLP) and achieve high performance. In this paper, we propose a mechanism to bypass L1D and L2 cache based on the availability of cache resources. Our proposed mechanism is based on the observation that a huge number of stalls coming from limited cache resources prohibit GPUs from providing a higher throughput. So we propose Resource Aware Cache Bypass (RACB) with minor hardware changes to eliminate such stalls to improve performance. We examine the effectiveness of this approach when applied to L1D and L2 cache separately as well as together. Evaluation results with NVIDIA computing SDK show that RACB generally improves performance the most when applied to both L1D and L2 cache, which is up to 88.05% and on an average of 16.73%;additionally, energy is saved up to 22.35% and on an average of 5.88% with minor hardware overheads. © 2014 IEEE.

关键词： Graphics processing unit

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Service Deployment in Cloud 16

Service Deployment in Cloud

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16th IEEE International Conference on high performance computing and Communications HPCC 2014\11th IEEE International Conference on Embedded Software and Systems ICESS 2014\6th International symposium on Cyberspace Safety and Security CSS 2014

作者： Haji, Amel Ben Letaifa, Asma Tabbane, Sami SUPCOM Mediatron Lab Higher Sch Commun Tunis Tunis Tunisia

ISBN: (纸本)9781479961238

Among the many limitations that the clouds are facing today, the heterogeneity of IT resources and networks. the dynamic deployment and on-demand applications are also major challenges. To ensure this deployment, it is essential to rely on methods of managing applications and services in a cloud. this paper proposes to apply the concept of Virtual Appliance for cloud architectures to ensure the dynamic deployment, interoperability and reuse of services supported by these clouds. Proposed architecture aims to solve problems of users whose are blocked from sellers with very little flexibility to move their services to other providers. Using standards of DMTF could provide more flexibility and response to user's requirement under SLA constraints.

关键词： Cloud computing Cloud federation OVF Virtual Appliance Service Deployment

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A novel flexible 16-core MP-SoC architecture based on parallel skeletons for image processing applications 57

A novel flexible 16-core MP-SoC architecture based on parall...

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57th IEEE International Midwest symposium on Circuits and Systems (MWSCAS)

作者： Boussadi, Mohamed Amine Tixier, thierry Landrault, Alexis Derutin, Jean-Pierre UBP IFMA Inst Pascal UMR CNRS 6602 F-63171 Aubiere France

ISBN: (纸本)9781479941322

For many image processing systems, the computing power required can not be provided by a single sequential processor, this is why many designers appeal to multiprocessor systems (parallelism). this article proposes an original flexible MP-SoC (Multi-Processors System on Chip) architecture for image processing applications. Developing processors network systems tailored to a particular application domain is critical and design-time consuming in order to achieve high-performance customized solutions. this paper introduces a 16-core MP-SoC ASIC with a software configuration. In particular, each tile of the network can configure its communication links depending on the most relevant overall parallelism scheme for a targeted application. Results are shown in term of power, area and timing performance for a 65 nm CMOS technology ASIC design. A case study (grey scale histogram analyzes) is presented to illustrate the proposed flexible MP-SoC design methodology and enables to focus on architecture exploration, instantiated scheme of parallelization and timing performance.

关键词： Application specific integrated circuits Clocks computer architecture Field programmable gate arrays Hardware Skeleton Topology

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Energy efficient seismic wave propagation simulation on a low-power manycore processor 26

Energy efficient seismic wave propagation simulation on a lo...

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26th International symposium on computer architecture and high performance computing, SBAC-PAD 2014

作者： Castro, Marcio Dupros, Fabrice Francesquini, Emilio Mehautk, Jean-Francois Navaux, Philippe O.A. Informatics Institute Federal University of Rio Grande Do sul Brazil Department of Informatics and Statistics Federal University of Santa Catarina Brazil BRGM Orléans France Institute of Computing University of Campinas Brazil Institute of Mathematics and Statistics University of São Paulo Brazil CEA/DRT University of Grenoble France

ISBN: (纸本)9781479969043

Large-scale simulation of seismic wave propagation is an active research topic. Its high demand for processing power makes it a good match for high performance computing (HPC). Although we have observed a steady increase on the processing capabilities of HPC platforms, their energy efficiency is still lacking behind. In this paper, we analyze the use of a low-power manycore processor, the MPPA-256, for seismic wave propagation simulations. First we look at its peculiar characteristics such as limited amount of on-chip memory and describe the intricate solution we brought forth to deal with this processor's idiosyncrasies. Next, we compare the performance and energy efficiency of seismic wave propagation on MPPA-256 to other commonplace platforms such as general-purpose processors and a GPU. Finally, we wrap up with the conclusion that, even if MPPA-256 presents an increased software development complexity, it can indeed be used as an energy efficient alternative to current HPC platforms, resulting in up to 71% and 81% less energy than a GPU and a general-purpose processor, respectively. © 2014 IEEE.

关键词： Graphics processing unit

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Cross-layer self-adaptive/self-aware system software for exascale systems 26

Cross-layer self-adaptive/self-aware system software for exa...

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26th International symposium on computer architecture and high performance computing, SBAC-PAD 2014

作者： Gioiosa, Roberto Kestor, Gokcen Kerbyson, Darren J. Hoisie, Adolfy High Performance Computing Pacific Northwest National Laboratory RichlandWA United States

ISBN: (纸本)9781479969043

the extreme level of parallelism coupled with the limited available power budget expected in the exascale era brings unprecedented challenges that demand optimization of performance, power and resiliency in unison. Scalability on such systems is of paramount importance, while power and reliability issues may change the execution environment in which a parallel application runs. To solve these challenges exascale systems will require an introspective system software that combines system and application observations across all system stack layers with online feedback and adaptation mechanisms. In this paper we propose the design of a novel self-aware, selfadaptive system software in which a kernel-level Monitor, which continuously inspects the evolution of the target system through observation of Sensors, is combined with a user-level Controller, which reacts to changes in the execution environment, explores opportunities to increase performance, save power and adapts applications to new execution scenarios. We show that the monitoring system accurately monitors the evolution of parallel applications with a runtime overhead below 1-2%. As a test case, we design and implement a runtime system that aims at optimizing application's performance and system power consumption on complex hierarchical architectures. Our results show that our adaptive system reaches 98% of performance efficiency of manually-tuned applications. © 2014 IEEE.

关键词： Budget control

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Reducing compiler-inserted instrumentation in unified-parallel-C code generation 26

Reducing compiler-inserted instrumentation in unified-parall...

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26th International symposium on computer architecture and high performance computing, SBAC-PAD 2014

作者： Alvanosl, Michail Amaral, José Nelson Tiotto, Ettore Farreras, Montse Martorell, Xavier Computer Science Barcelona Supercomputing Center Spain Department of Computing Science University of Alberta Edmonton Canada Static Compilation Technology IBM Toronto Laboratory Markham Canada Department of Computer Architecture Universitat Politècnica de Catalunya Spain

ISBN: (纸本)9781479969043

Programs written in Partitioned Global Address Space (PGAS) languages can access any location of the entire address space via standard read/write operations. However, the compiler have to create the communication mechanisms and the runtime system to use synchronization primitives to ensure the correct execution of the programs. However, PGAS programs may have fine-grained shared accesses that lead to performance degradation. One solution is to use the inspector-executor technique to determine which accesses are indeed remote and which accesses may be coalesced in larger remote access operations. A straightforward implementation of the inspector-executor in a PGAS system may result in excessive instrumentation that hinders performance. this paper introduces a shared-data localization transformation based on linear memory descriptors (LMADs) that reduces the amount of instrumentation introduced by the compiler into programs written in the UPC language and describes a prototype implementation of the proposed transformation. A performance evaluation, using up to 2048 cores of a POWER 775 supercomputer, allows for a prediction that applications with regular accesses can achieve up to 180% of the performance of handoptimized versions while applications with irregular accesses yield performance gain from 1.12X up to 6.3X speedup. © 2014 IEEE.

关键词： Linear transformations

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Optical Interconnects between Microprocessor and Memories 16

Optical Interconnects between Microprocessor and Memories

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作者： Luo, Daxin Liu, Yaoda Liu, Xiaoying Zhang, Bin Li, Gang Liao, Qi Hao, Qinfen Wei, Zhulin Huawei Technol Co Ltd Shannon Lab Shenzhen Guangdong Peoples R China

ISBN: (纸本)9781479961238

More memories will be required in a future server as the number of cores per microprocessor keeps growing, which means either the capacity of a memory chip or the number of memory chips connected to a microprocessor needs to catch up with the increasing core counts. With electrical interconnects between microprocessor and memories, layout and placement of memory chips around the microprocessor becomes a bottleneck. Optical interconnects will solve this problem by putting memory chips further away from a microprocessor. We investigate in this paper the performance of a computer with optically connected remote memory instead of electrically connected local memory, and verified that an operating system can successfully run with only optically connected memory. the experimental results demonstrated the feasibility of utilizing optically connected remote memory as memory instead of storage as discussed mostly in the literature.

关键词： computer architecture optical interconnects latency microprocessor memory

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high-level dataflow programming for reconfigurable computing 26

High-level dataflow programming for reconfigurable computing

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26th IEEE International symposium on computer architecture and high performance computing Workshops, SBAC-PADW 2014

作者： Sérot, J. Berry, F. Institut Pascal Université Blaise Pascal / CNRS Clermont-Ferrand France

ISBN: (纸本)9781479970148

In many application domains, FPGAS are now promoted as a way of getting round the restrictions of specific CPU designs on system scalability. However, in the current state-of-the art, programming FPGAS remains essentially a hardware-oriented activity, relying on dedicated hardware description languages such as VHDL or Verilog. Using these languages requires expertise in digital design and in practice this limits the applicability of FPGA-based solutions. this is particulary true for stream-processing applications, in which some processing must be carried out "on the fly" on digital data streams. In this context, the dataflow programming model offers a very effective way to reduce the gap between high-level formulations and low-level implementations. To support this claim, the authors have recently introduced CAPH, a domain specific language, offering a fully-automated compilation path from high-level dataflow descriptions to FPGA configuration for stream-processing applications. this paper is a introduction to the CAPH language, giving its motivations and main design principles and exposing the basic features of its syntax, semantics and compilation. It also points to experimental results showing that, at least for stream-processing applications, the dataflow model of computation, used jointly as a programming model and an execution model, can offer a very effective way to conciliate abstraction and efficiency when programming FPGAS. © 2014 IEEE.

关键词： computer hardware description languages

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