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检索条件"任意字段=Proceedings - 16th Symposium on Computer Architecture and High Performance Computing"

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performance Characterization and Evaluation of HPC Algorithms on Dissimilar Multicore architectures 16

Performance Characterization and Evaluation of HPC Algorithm...

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16th IEEE International Conference on high performance computing and Communications HPCC 2014\11th IEEE International Conference on Embedded Software and Systems ICESS 2014\6th International symposium on Cyberspace Safety and Security CSS 2014

作者： Krishnan, S. P. T. Veeravalli, Bharadwaj Agcy Sci Technol & Res Inst Infocomm Res Singapore 138632 Singapore Natl Univ Singapore Dept Elect & Comp Engn Singapore 117583 Singapore

ISBN: (纸本)9781479961238

In this paper, we share our experiences in using two important yet different high performance computing (HPC) architectures for evaluating two HPC algorithms. the first architecture is an Intel x64 ISA based homogenous multicore with Uniform Memory Access (UMA) type shared-memory based Symmetric Multi-Processing system. the second architecture is an IBM Power ISA based heterogenous multicore with Non-Uniform Memory Access (NUMA) based distributed-memory Asymmetric Multi-Processing system. the two HPC algorithms are for predicting biological molecular structures, specifically the RNA secondary structures. the first algorithm that we created is a parallelized version of a popular serial RNA secondary structure prediction algorithm called PKNOTS. the second algorithm is a new parallel-by-design algorithm that we have developed called MARSs. Using real Ribo-Nucleic Acid (RNA) sequences, we conducted large-scale experiments involving hundreds of sequences using the above two algorithms. Based on thousands of data points that we collected as an outcome of our experiments, we report on the observed performance metrics for both the algorithms on the two architectures. through our experiments, we infer that architectures with specialized co-processors for number-crunching along with high-speed memory bus and dedicated bus controllers generally perform better than general-purpose multi-processor architectures. In addition, we observed that algorithms that are intrinsically parallelized by design are able to scale & perform better by taking advantage of the underlying parallel architecture. We further share best practices on handling scalability aspects with regards to workload size. We believe our results are applicable to other HPC applications on similar HPC architectures.

关键词： architecture high performance computing algorithms Multi-core processors Prediction algorithms Parallel architectures Multi-Processing performance metrics Building construction Best Practices

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On the performance of the WRF Numerical Model over Complex Terrain on a high performance computing Cluster 16

On the Performance of the WRF Numerical Model over Complex T...

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16th IEEE Int Conf on high performance computing and Communications/11th IEEE Int Conf on Embedded Software and Systems\6th Int symposium on Cyberspace Safety and Security

作者： Christakis, Nicholas Katsaounis, theodoros Kossioris, George Plexousakis, Michael Univ Crete CCQCN Dept Phys Iraklion Greece Univ Crete FORTH GR IACM Iraklion Greece Univ Crete Dept Math & Appl Math Iraklion Greece

ISBN: (纸本)9781479961238

In this paper the performance of the Weather Research and Forecasting (WRF) numerical model over complex terrain on a high performance computing (HPC) cluster is discussed. Simulations were performed with two different nested domain configurations and the patterns and variability of near-surface winds over two selected areas of the Greek territory were compared with data from surface meteorological stations. Various verification statistics were utilized to gauge the ability of the model for accurate predictions and its performance for the different configurations was assessed. Finally, suggestions were made concerning performance optimization for high resolution simulations.

关键词： HPC cluster WRF nested domains high resolution simulations model performance surface wind patterns

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Utilizing many-core accelerators for halo and center finding within a cosmology simulation

Utilizing many-core accelerators for halo and center finding...

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IEEE symposium on Large Data Analysis and Visualization (LDAV)

作者： Christopher Sewell Li-ta Lo Katrin Heitmann Salman Habib James Ahrens Los Alamos National Laboratory Argonne National Laboratory

Efficiently finding and computing statistics about “halos” (regions of high density) are essential analysis steps for N-body cosmology simulations. However, in state-of-the-art simulation codes, these analysis operators do not currently take advantage of the shared-memory data-parallelism available on multi-core and many-core architectures. the Hybrid / Hardware Accelerated Cosmology Code (HACC) is designed as an MPI+X code, but the analysis operators are parallelized only among MPI ranks, because of the difficulty in porting different X implementations (e.g., OpenMP, CUDA) across all architectures on which it is run. In this paper, we present portable data-parallel algorithms for several variations of halo finding and halo center finding algorithms. these are implemented with the PISTON component of the VTK-m framework, which uses Nvidia's thrust library to construct data-parallel algorithms that allow a single implementation to be compiled to multiple backends to target a variety of multi-core and many-core architectures. Finally, we compare the performance of our halo and center finding algorithms against the original HACC implementations on the Moonlight, Stampede, and Titan supercomputers. the portability of thrust allowed the same code to run efficiently on each of these architectures. On Titan, the performance improvements using our code have enabled halo analysis to be performed on a very large data set (81923 particles across 16,384 nodes of Titan) for which analysis using only the existing CPU algorithms was not feasible.

关键词： Algorithm design and analysis computer architecture Computational modeling Graphics processing units Analytical models Acceleration Pistons

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Online performance Analysis: An Event-based Workflow Design Towards Exascale 16

Online Performance Analysis: An Event-based Workflow Design ...

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16th IEEE Int Conf on high performance computing and Communications/11th IEEE Int Conf on Embedded Software and Systems\6th Int symposium on Cyberspace Safety and Security

作者： Wagner, Michael Hilbrich, Tobias Brunst, Holger Tech Univ Dresden Ctr Informat Serv & High Performance Comp ZIH D-01062 Dresden Germany

ISBN: (纸本)9781479961238

Today, it is commonly accepted that speedup and efficiency are not granted automatically when developing or porting software for high performance computing (HPC) platforms. the reasons are manifold and actively investigated in the community. Software monitors are essential for these studies as they provide the raw performance data to be analyzed. We propose an online monitoring workflow for event-based performance analysis that takes into account the significant changes in system architecture towards the development of exascale supercomputers. Critical properties are: communication across large numbers of processing elements, limited I/O capabilities, and a decreasing memory-per- core ratio. We present a hierarchical data management and steering workflow that directly couples the application, measurement, and analysis processes, thus eliminating the need for extensive communication and buffering. the workflow is closely integrated with the native system communication API to enable best communication across processing elements. the memory issue is addressed with a new lossy hierarchical data compression technique for in-memory storage, intended for small, fixed-size buffers. Further, we abandon secondary storage to avoid potential I/O challenges. We demonstrate the feasibility of our design with a prototype implementation that features services for data collection, analysis, and runtime compression. Our evaluation extrapolates results obtained with the NAS Parallel Benchmarks at up to 2,048 processes to an exascale workflow.

关键词： GTI OTFX Online performance analysis event tracing online tracing Workflow Event-based data compression technology AUXILIARY STORAGE Communication Research IO high performance computing Data management Speeding

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Research on Mahalanobis Distance Algorithm Optimization Based on OpenCL 16

Research on Mahalanobis Distance Algorithm Optimization Base...

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16th IEEE Int Conf on high performance computing and Communications/11th IEEE Int Conf on Embedded Software and Systems\6th Int symposium on Cyberspace Safety and Security

作者： Xie, Qingchun Zhang, Yunquan Jia, Haipeng Lu, Yongquan Commun Univ China High Performance Comp Ctr Beijing 100024 Peoples R China Chinese Acad Sci Inst Software Lab Parallel Comp Beijing 100190 Peoples R China Chinese Acad Sci Inst Comp Technol State Key Lab Comp Architecture Beijing 100190 Peoples R China

ISBN: (纸本)9781479961238

Mahalanobis distance algorithms has been widely used in machine learning and classification algorithms, and it has an important practical significance in improving the performance of some applications through GPU, especially in some applications with high real-time demand. However, due to the complexity of the GPU hardware architectures, how to complete the algorithm optimization and achieve high performance portability on different GPU platforms is still a hard work. the redundant calculation of traditional Mahalanobis distance algorithm is very large and is hard to implement parallel. In this paper, we not only throw light on the universal ways to properly map mature algorithms to GPU devices to implement the Mahalanobis distance, such as fixed number of workgroups and vectorization, but also put forward five valuable methods of performance optimization on heterogeneous computing platforms, such as two-dimension NDRange workgroup arrangement, Uberkernel, binary reduction with the help of LDS register in one workgroup. Furthermore, We also demonstrate the high performance of our implementation by comparing it with a well-optimized CPU version from OpenCV library. Experimental results show that speedup reaches up 10.59 times on NVIDIA GPU C2050, 8.55 times on AMD HD5850 and 16.08 times on HD7970. the last experimental results verified the effectiveness of optimization methods which we proposed.

关键词： OpenCL Heterogeneous computing GPU Mahalanobis Parallel Optimization

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Real-time Environmental Monitoring for Cloud-based Hydrogeological Modeling with HydroGeoSphere 16

Real-time Environmental Monitoring for Cloud-based Hydrogeol...

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16th IEEE Int Conf on high performance computing and Communications/11th IEEE Int Conf on Embedded Software and Systems\6th Int symposium on Cyberspace Safety and Security

作者： Lapin, Andrei Schiller, Eryk Kropf, Peter Schilling, Oliver Brunner, Philip Jamakovic-Kapic, Almerima Braun, Torsten Maffioletti, Sergio Univ Neuchatel Comp Sci Dept IIUN CH-2000 Neuchatel Switzerland Univ Neuchatel Ctr Hydrogeol & Geotherm CHYN CH-2000 Neuchatel Switzerland Univ Bern Commun & Distributed Syst Grp CDS CH-3012 Bern Switzerland Univ Zurich Grid Comp Competence Ctr CH-8057 Zurich Switzerland

ISBN: (纸本)9781479961238

this paper describes an architecture for real-time environmental modeling. It consists of a wireless mesh network equipped with sensors and a cloud-based infrastructure to perform real-time environmental simulations using a physics-based model combined with an Ensemble Kalman Filter. the purpose of the system is to optimize groundwater abstraction close to a river. these initial studies demonstrate that the cloud infrastructure can simultaneously compute a large number of simulations, thus allowing for the implementation of Ensemble Kalman Filters in real-time.

关键词： cloud computing distributed systems environmental simulations hydrogeosphere mesh networking

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Compact hash tables for high-performance traffic classification on multi-core processors 26

Compact hash tables for high-performance traffic classificat...

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26th International symposium on computer architecture and high performance computing, SBAC-PAD 2014

作者： Qu, Yun R. Prasanna, Viktor K. Ming Hsieh Department of Electrical Engineering University of Southern California Los AngelesCA90007 United States

ISBN: (纸本)9781479969043

Traffic classification is one of the kernel applications in network management. Many Machine Learning (ML) traffic classification algorithms are based on decision-trees. While most of the existing implementations of decision-trees are hardwarebased, a new trend in network applications is to use softwarebased solutions. the decision-tree used for traffic classification is highly unbalanced, it is challenging to achieve high performance on multi-core platforms. In this paper, we present a high-throughput and low-latency traffic classification engine on multi-core platforms. We convert the decision-tree used in the C4.5 algorithm into multiple compact tables. All the compact tables are searched in parallel, efficient hashing techniques are employed to reduce the processing latency. the outcomes from all the tables are merged into the final classification result. high throughput can be sustained even if we scale up (1) the number of concurrent traffic classifiers, (2) the number of decision-tree leaves and (3) the number of features examined during the classification process. We prototype our design on state-of-the-art AMD and Intel multi-core platforms. For a typical C4.5 decisiontree consisting of 92 leaf nodes and 7 flow-level features, we achieve 134:15 Million Lookups Per Second (MLPS) throughput and 238:53 ns processing latency per lookup. Even for highly unbalanced decision-trees or large decision-trees consisting of up to 2K leaf nodes, our traffic classification engine sustains high throughput and low latency without sacrificing classification accuracy (≥ 98.15%). We achieve 2.7× throughput compared with the classic C4.5 decision-tree-based implementations, and at least 12× speed-up compared with the existing traffic classifiers on multi-core platforms. © 2014 IEEE.

关键词： Decision trees

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A minimalistic dataflow programming library for python 26

A minimalistic dataflow programming library for python

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26th IEEE International symposium on computer architecture and high performance computing Workshops, SBAC-PADW 2014

作者： Alves, Tiago A.O. Goldstein, Brunno F. França, Felipe M. G. Marzulo, Leandro A.J. Programa de Engenharia de Sistemas e Computação COPPE Universidade Federal Do Rio de Janeiro Rio de Janeiro Brazil Dep. de Informática e Ciência da Computação Instituto de Matemática e Estatística - IMe Universidade Do Estado Do Rio de Janeiro - UERJ Rio de Janeiro Brazil

ISBN: (纸本)9781479970148

Current work on parallel programming models are trending towards the dataflow paradigm. Previous works on that topic have shown that dataflow programming is indeed a natural way to exploit parallelism in programs. However, there is still a gap in terms of ease of programming between high level languages adopted by the scientific community and the languages and tools available for dataflow programming. In this paper we present Sucuri: a minimalistic Python library that provides dataflow programming with reasonably simple syntax. To parallelize applications using our library, the programmer needs only to identify functions of his code that are good candidates for parallelization and instantiate a dataflow graph where each node is associated with one of such functions, and the edges between nodes describe data dependencies between functions. We then proceed to implement two benchmarks that represent important parallel programming patterns using our library and execute them on a cluster of multicores. Experimental results are promising, proving that our library can be an interesting first option for parallelization. © 2014 IEEE.

关键词： high level languages

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Stack-tagged dataflow 26

Stack-tagged dataflow

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26th IEEE International symposium on computer architecture and high performance computing Workshops, SBAC-PADW 2014

作者： Santiago, Leandro Marzulo, Leandro A.J. Goldstein, Brunno F. Alves, Tiago A.O. França, Felipe M.G. Dep. de Informática e Ciência da Computação Instituto de Matemática e Estatística - IMe Universidade Do Estado Do Rio de Janeiro - UERJ Rio de Janeiro Brazil Programa de Engenharia de Sistemas e Computação COPPE Universidade Federal Do Rio de Janeiro Rio de Janeiro Brazil

ISBN: (纸本)9781479970148

Dynamic Dataflow allows simultaneous execution of instructions in different iterations of a loop, boosting parallelism exploitation. In this model, operands are tagged with their associated instance number, incremented as they go through the loop. Instruction execution is triggered when all input operand with the same tag become available. However, this traditional tagging mechanism often requires the generation of several control instructions to manipulate tags and guarantee the correct matching. To address this problem, this work presents Stack- Tagged Dataflow, a tagging mechanism that uses stacks of tags to reduce control overheads in dataflow, while isolating context from different nested loops. Push instructions at the beginning of loops will create a new context, while Pop instructions, at the end of the loop, will restore the original context tags. Experimental results show that Stack-Tagged Dataflow is a viable solution, suggesting that a hybrid compiling approach can be used to enable Stack- Tags only when needed. © 2014 IEEE.

关键词： data flow computing program control structures context isolation dataflow control overhead reduction nested loops pop instructions push instructions stack-tagged dataflow tagging mechanism Assembly computer architecture Context Libraries Parallel processing Tagging Virtual machining Dataflow Parallel Programming Stack Tag data flow TAGGING program control structures virtual machines Parallel programming computer architecture Furnace conveyors PARALLEL PROCESSING (computerS) Loops Libraries assemblies NESTED LOOPS virtual machining instruction

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HiTS: A high throughput memory scheduling scheme to mitigate denial-of-service attacks in multi-core systems 26

HiTS: A high throughput memory scheduling scheme to mitigate...

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26th International symposium on computer architecture and high performance computing, SBAC-PAD 2014

作者： Shafaei, Mansour Fei, Yunsi Electrical and Computer Engineering Department Northeastern University BostonMA02115 United States

ISBN: (纸本)9781479969043

Sharing DRAM memory by multiple cores in a computer system potentially exposes the running threads on cores to denial-of-service (DoS) attacks. this issue is usually addressed by memory scheduling schemes that rotate the memory service among threads according to a certain ranking mechanism. these ranking-based schemes, however, often incur many memory banks' row-buffer conflicts which reduce the throughput of DRAM and the entire system. this paper proposes a new ranking-based memory scheduling scheme, called HiTS, to mitigate DoS attacks in multicore systems with the lowest performance degradation. HiTS achieves these by ranking threads according to each thread's memory usage/requirement. HiTS then enforces the ranking in a way that minimum performance overhead would occur and fairness is also balanced. the effectiveness of HiTS is evaluated by simulations with 18 different workloads running on 8- and 16-core machines. the simulation results show up to 15.8% improvements in terms of unfairness reduction and 24.1% in system throughput compared with the best existing scheduling scheme. © 2014 IEEE.

关键词： Dynamic random access storage

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