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A parallel maximum subarray algorithm on GPUs 26

A parallel maximum subarray algorithm on GPUs

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26th IEEE International symposium on computer architecture and high performance computing Workshops, SBAC-PADW 2014

作者： Ferreira, Cleber S. Camargo, Raphael Y. Song, Siang Wun E. Politécnica USP and Universidade Federal Do ABC São Paulo Brazil Universidade Federal Do ABC São Paulo Brazil Dept Computer Science Universidade de São Paulo São Paulo Brazil

ISBN: (纸本)9781479970148

this paper presents a parallel algorithm for the maximum subarray problem implemented on a machine with GPUs. Given a sequence of numbers, the maximum subsequence is a contiguous subsequence with maximum sum. the maximum subarray problem is a 2-D version of the maximum subsequence problem. Given a 2-D array of numbers, the maximum subarray is the subarray with maximum sum of its elements. the main difficulty lies in the complex memory organization of the GPU architecture, as well as its more restricted SIMD computing paradigm. Efficient ways to distribute the tasks among threads should be *** ran the experiments on a machine with two NVIDIA Geforce GTX 680 graphics units and an Intel i7 CPU. For large input arrays, the parallel algorithm using CPU and two GPUs was able to run about 590 times faster than the sequential counterpart when only one CPU core is used. © 2014 IEEE.

关键词： Parallel algorithms

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Watershed reengineering: Making streams programmable 26

Watershed reengineering: Making streams programmable

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26th IEEE International symposium on computer architecture and high performance computing Workshops, SBAC-PADW 2014

作者： Rocha, Rodrigo Caetano Ferreira, Renato Meira, Wagner Guedes, Dorgival Department of Computer Science Universidade Federal de Minas Gerais Belo Horizonte Brazil

ISBN: (纸本)9781479970148

Most high-performance data processing (aka bigdata) systems allow users to express their computation using abstractions (like map-reduce) that simplify the extraction of parallelism from applications. Most frameworks, however, do not allow users to specify how communication must take place: that element is deeply embedded into the run-time system (RTS), making changes hard to implement. In this work we describe our reengineering of the Watershed system, a framework based on the filter-stream paradigm and focused on continuous stream processing. Like other big-data environments, watershed provided object-oriented abstractions to express computation (filters), but the implementation of streams was an RTS element. By isolating stream functionality into appropriate classes, combination of communication patterns and reuse of common message handling functions (like compression and blocking) become possible. the new architecture even allow the design of new communication patterns, for example, allowing users to choose MPI, TCP or shared memory implementations of communication channels as their problem demand. Applications designed for the new interface showed reductions in code size on the order of 50% and above in some cases, with no significant performance penalty. © 2014 IEEE.

关键词： Parallel programming

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Evaluating GPU Passthrough in Xen for high performance Cloud computing 28

Evaluating GPU Passthrough in Xen for High Performance Cloud...

引用

28th IEEE International Parallel & Distributed Processing symposium Workshops (IPDPSW)

作者： Younge, Andrew J. Walters, John Paul Crago, Stephen Fox, Geoffrey C. Indiana Univ Pervas Technol Inst 2719 E 10th St Bloomington IN 47408 USA Univ Southern Calif Informat Sci Inst Arlington VA 22203 USA

ISBN: (纸本)9781479941162

With the advent of virtualization and Infrastructure-as-a-Service (IaaS), the broader scientific computing community is considering the use of clouds for their technical computing needs. this is due to the relative scalability, ease of use, advanced user environment customization abilities clouds provide, as well as many novel computing paradigms available for data-intensive applications. However, there is concern about a performance gap that exists between the performance of IaaS when compared to typical high performance computing (HPC) resources, which could limit the applicability of IaaS for many potential scientific users. Most recently, general-purpose graphics processing units (GPGPUs or GPUs) have become commonplace within high performance computing. We look to bridge the gap between supercomputing and clouds by providing GPU-enabled virtual machines (VMs) and investigating their feasibility for advanced scientific computation. Specifically, the Xen hypervisor is utilized to leverage specialized hardware-assisted I/O virtualization and PCI passthrough in order to provide advanced HPC-centric Nvidia GPUs directly in guest VMs. this methodology is evaluated by measuring the performance of two Nvidia Tesla GPUs within Xen VMs and comparing to bare-metal hardware. Results show PCI passthrough of GPUs within virtual machines is a viable use case for many scientific computing workflows, and could help support high performance cloud infrastructure in the near future.

关键词： Cloud computing GPUs HPC IaaS Scientific computing

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A Provisioning Service for Automatic Command Line Applications Deployment in computing Clouds 16

A Provisioning Service for Automatic Command Line Applicatio...

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16th IEEE Int Conf on high performance computing and Communications/11th IEEE Int Conf on Embedded Software and Systems\6th Int symposium on Cyberspace Safety and Security

作者： Pyshkin, Evgeny Kuznetsov, Andrey St Petersburg State Polytech Univ Inst Comp & Control St Petersburg 195251 Russia Motorola Solut Inc St Petersburg Software Ctr St Petersburg 192019 Russia

ISBN: (纸本)9781479961238

this paper discusses an approach for deploying command-line applications on cloud computing platforms. the main focus of the paper is on execution of scientific algorithms (such as algorithms from the music information retrieval domain) by enabling the sharing of algorithm implementations, the reproducibility of results, and an easy access to non-experts of distributed environments. We propose a method of automatic deployment of client command line applications in PaaS and IaaS clouds which, unlike to existing approaches, requires neither preliminary platform configuration, nor platform configuration description. We designed a deployment manager using an expert system in order to automatically setup a virtual execution platform, by resolving dependencies and solving configuration issues on the basis of a pre-existing knowledge base.

关键词： Command line Expert System AUTOMATIC deployment Cloud computing Legal Executions Clouds Reproducibility of Results Platform Knowledge Bases algorithms

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Virtual Machine Scheduling Considering Both computing and Cooling Energy 16

Virtual Machine Scheduling Considering Both Computing and Co...

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16th IEEE Int Conf on high performance computing and Communications/11th IEEE Int Conf on Embedded Software and Systems\6th Int symposium on Cyberspace Safety and Security

作者： Li, Xiang Jiang, Xiaohong He, Yanzhang Zhejiang Univ Coll Comp Sci Hangzhou Zhejiang Peoples R China

ISBN: (纸本)9781479961238

the problem of high energy consumption of data centers has become increasingly serious. computing and cooling energy are the most significant parts. On one hand, as the energy consumption of under-utilized resources accounts for a substantial amount of the actual energy draw, load consolidation is widely used for reducing computing energy by increasing resource utilization. On the other hand, to avoid the hot spots, which increase the requirement of cooling capacity and reduce cooling efficiency, load balance is often adopted for better thermal management. these two approaches are contradict with each other. this paper explores the tradeoff between load consolidation and balance. Our proposed policy DartScheduler selects genetic algorithm to generate a near optimum scheduling solution. the results show that, in most cases, our approach can significantly reduce the total energy consumption comparing with the other baseline algorithms. Further, the time cost for DartScheduler is tolerable for online deployment and scheduling.

关键词： Workload Scheduling Energy Efficiency Energy Modeling Data Center Cloud computing

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Coupling and Simulation of Fluid-Structure Interaction Problems for Automotive Sun-roof on Graphics Processing Unit 16

Coupling and Simulation of Fluid-Structure Interaction Probl...

引用

16th IEEE Int Conf on high performance computing and Communications/11th IEEE Int Conf on Embedded Software and Systems\6th Int symposium on Cyberspace Safety and Security

作者： Lai, Liang S. Lai, Choi-Hong Ahamed, Abal-Kassim Cheik Magoules, Frederic Univ Greenwich Sch Comp & Math Sci London SE18 6PF England Ecole Cent Paris Paris France

ISBN: (纸本)9781479961238

In this paper, the authors propose an analysis of the frequency response function in a car compartment, subject to some fluctuating pressure distribution along the open cavity of the sun-roof at the top of a car. Coupling of a computational fluid dynamics and of a computational acoustics code is considered to simulate the acoustic fluid-structure interaction problem. Iterative Krylov methods and domain decomposition methods, tuned on Graphic Processing Unit (GPU), are considered to solve the acoustic problem with complex number arithmetics with double precision. Numerical simulations illustrate the efficiency, robustness and accuracy of the proposed approaches.

关键词： Parallel and distributed computing GPU Krylov method domain decomposition method computational fluid dynamics acoustics

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DASCA: Dead write prediction assisted STT-RAM cache architecture

DASCA: Dead write prediction assisted STT-RAM cache architec...

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20th IEEE International symposium on high performance computer architecture, HPCA 2014

作者： Ahn, Junwhan Yoo, Sungjoo Choi, Kiyoung Department of Electrical and Computer Engineering Seoul National University Seoul Korea Republic of Department of Electrical Engineering POSTECH Pohang Korea Republic of

ISBN: (纸本)9781479930975

Spin-Transfer Torque RAM (STT-RAM) has been considered as a promising candidate for on-chip last-level caches, replacing SRAM for better energy efficiency, smaller die footprint, and scalability. However, it also introduces several new challenges into last-level cache design that need to be overcome for feasible deployment of STT-RAM caches. Among other things, mitigating the impact of slow and energy-hungry write operations is of the utmost importance. In this paper, we propose a new mechanism to reduce write activities of STT-RAM last-level caches. the key observation is that a significant amount of data written to last-level caches is not actually re-referenced again during the lifetime of the corresponding cache blocks. Such write operations, which we call dead writes, can bypass the cache without incurring extra misses by definition. Based on this, we propose Dead Write Prediction Assisted STT-RAM Cache architecture (DASCA), which predicts and bypasses dead writes for write energy reduction. For this purpose, we first propose a novel classification of dead writes, which is composed of dead-on-arrival fills, dead-value fills, and closing writes, as a theoretical model for redundant write elimination. On top of that, we present a dead write predictor based on a state-of-the-art dead block predictor. Evaluations show that our architecture achieves an energy reduction of 68% (62%) in last-level caches and an additional energy reduction of 10% (16%) in main memory and even improves system performance by 6% (14%) on average compared to the STT-RAM baseline in a single-core (quad-core) system. © 2014 IEEE.

关键词： Energy efficiency

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Parallel Sub-Structuring Methods for solving Sparse Linear Systems on a cluster of GPU 16

Parallel Sub-Structuring Methods for solving Sparse Linear S...

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16th IEEE Int Conf on high performance computing and Communications/11th IEEE Int Conf on Embedded Software and Systems\6th Int symposium on Cyberspace Safety and Security

作者： Ahamed, Abal-Kassim Cheik Magoules, Frederic Ecole Cent Paris CUDA Res Ctr Paris France

ISBN: (纸本)9781479961238

the main objective of this work consists in analyzing sub-structuring method for the parallel solution of sparse linear systems with matrices arising from the discretization of partial differential equations such as finite element, finite volume and finite difference. With the success encountered by the general-purpose processing on graphics processing units (GPGPU), we develop an hybrid multiGPUs and CPUs sub-structuring algorithm. GPU computing, with CUDA, is used to accelerate the operations performed on each processor. Numerical experiments have been performed on a set of matrices arising from engineering problems. We compare C+MPI implementation on classical CPU cluster with C+MPI+CUDA on a cluster of GPU. the performance comparison shows a speed-up for the sub-structuring method up to 19 times in double precision by using CUDA.

关键词： Sub-structuring method Linear algebra Conjugate Gradient Parallel and distributed computing Graphics Processing Unit GPU computing CUDA Finite element

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Dual-page mode: exploring parallelism in MLC flash SSDs 16

Dual-page mode: exploring parallelism in MLC flash SSDs

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16th IEEE Int Conf on high performance computing and Communications/11th IEEE Int Conf on Embedded Software and Systems\6th Int symposium on Cyberspace Safety and Security

作者： Du, Yimo Zhang, Youtao Xiao, Nong Natl Univ Def Technol State Key Lab High Performance Comp Changsha Hunan Peoples R China Univ Pittsburgh Dept Comp Sci Pittsburgh PA 15260 USA

ISBN: (纸本)9781479961238

MLC flash memory SSDs have gained much popularity in storage subsystems from mobile devices to data centers because of their high performance and low power consumption. the naturally rich internal parallelism of SSDs is one of the most important factors that contribute to the high performance. Many studies make use of the parallelism from various perspectives such as scheduler, SSD organization and data layout etc. to promote the performance. However, internal parallelism of SSDs has been limited to plane level so far. this paper extends the parallelism beyond plain level, exploring the parallelism among pages within a block. We propose dual-page mode that can access two pages simultaneously. Experimental results demonstrate that SSDs with dual-page mode can reduce the average response time by up to 38% compared with contemporary SSDs.(1)

关键词： Flash Memory Parallelism SSD

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Warp-level divergence in GPUs: Characterization, impact, and mitigation

Warp-level divergence in GPUs: Characterization, impact, and...

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20th IEEE International symposium on high performance computer architecture, HPCA 2014

作者： Xiang, Ping Yang, Yi Zhou, Huiyang Dept. of Electrical and Computer Engineering North Carolina State University Raleigh NC United States Dept. of Computing Systems Architecture NEC Laboratories America Princeton NJ United States

ISBN: (纸本)9781479930975

high throughput architectures rely on high thread-level parallelism (TLP) to hide execution latencies. In state-of-art graphics processing units (GPUs), threads are organized in a grid of thread blocks (TBs) and each TB contains tens to hundreds of threads. With a TB-level resource management scheme, all the resource required by a TB is allocated/released when it is dispatched to / finished in a streaming multiprocessor (SM). In this paper, we highlight that such TB-level resource management can severely affect the TLP that may be achieved in the hardware. First, different warps in a TB may finish at different times, which we refer to as 'warp-level divergence'. Due to TB-level resource management, the resources allocated to early finished warps are essentially wasted as they need to wait for the longest running warp in the same TB to finish. Second, TB-level management can lead to resource fragmentation. For example, the maximum number of threads to run on an SM in an NVIDIA GTX 480 GPU is 1536. For an application with a TB containing 1024 threads, only 1 TB can run on the SM even though it has sufficient resource for a few hundreds more threads. To overcome these inefficiencies, we propose to allocate and release resources at the warp level. Warps are dispatched to an SM as long as it has sufficient resource for a warp rather than a TB. Furthermore, whenever a warp is completed, its resource is released and can accommodate a new warp. this way, we effectively increase the number of active warps without actually increasing the size of critical resources. We present our lightweight architectural support for our proposed warp-level resource management. the experimental results show that our approach achieves up to 76.0% and an average of 16.0% performance gains and up to 21.7% and an average of 6.7% energy savings at minor hardware overhead. © 2014 IEEE.

关键词： Graphics processing unit

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