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检索条件"任意字段=Proceedings - 16th Symposium on Computer Architecture and High Performance Computing"

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Direct Spatial Implementation of Sparse Matrix Multipliers for Reservoir computing 28

Direct Spatial Implementation of Sparse Matrix Multipliers f...

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28th Annual IEEE International symposium on high-performance computer architecture (HPCA)

作者： Denton, Matthew Schmit, Herman Google Res Mountain View CA 94043 USA

ISBN: (纸本)9781665420273

Reservoir computing is a nascent sub-field of machine learning which relies on the recurrent multiplication of a very large, sparse, fixed matrix. We argue that direct spatial implementation of these fixed matrices minimizes the work performed in the computation, and allows for significant reduction in latency and power through constant propagation and logic minimization. Bit-serial arithmetic enables massive static matrices to be implemented. We present the structure of our bit-serial matrix multiplier, and evaluate using canonical signed digit representation to further reduce logic utilization. We have implemented these matrices on a large FPGA and provide a cost model that is simple and extensible. these FPGA implementations, on average, reduce latency by 50x up to 86x versus GPU libraries. Comparing against a recent sparse DNN accelerator, we measure a 4.1x to 47x reduction in latency depending on matrix dimension and sparsity.

关键词： Costs Graphics processing units computer architecture Machine learning Reservoirs throughput Minimization

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A Research Retrospective on the AMD Exascale computing Journey 50

A Research Retrospective on the AMD Exascale Computing Journ...

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50th Annual International symposium on computer architecture (ISCA)

作者： Loh, Gabriel H. Aga, Shaizeen Alsop, Johnathan Blagodurov, Sergey Chalmers, Noel Cownie, David Dutu, Alexandru Greathouse, Joseph L. Hossamani, Sachin Kalamatianos, John Lowell, Daniel Manne, Srilatha Mishkin, Michael Potter, Brandon Rao, Karthik Slice, John Vishnu, Abhinav Wyse, Mark Schulte, Michael J. Aguren, Derrick Bauman, Paul T. Boraten, Travis Chen, Shaoming Curtis, Nicholas Eckert, Yasuko Gurumurthi, Sudhanva Huang, Wei Kayiran, Onur Madan, Niti Mashimo, Susumu Nutter, Mark Punniyamurthy, Kishore Rodgers, Gregory Sridharan, Vilas Wasmundt, Samuel Yalavarti, Adithya Ignatowski, Mike Agrawal, Varun Beckmann, Bradford M. Boyer, Michael Cheng, Kevin Del Pino, Joris Erb, Christopher Gutierrez, Anthony Islam, Mahzabeen Kotra, Jagadish Majumdar, Abhinandan McDougall, Damon Paul, Indrani Puthoor, Sooraj Scrbak, Marko van Oostrum, Rene Wilkening, Mark Yudanov, Dmitri Adhinarayanan, Vignesh Aji, Ashwin M. Beigi, Majed Valad Brantley, William C. Chu, Michael L. Duong, Nam Freitag, Chip Hamidouche, Khaled Jayasena, Nuwan Lee, Alan Malaya, Nicholas Mednick, Elliot Poremba, Matthew Raasch, Steven E. Seyedzadeh, Mohammad van Tassell, Eric Wolfe, Noah Adv Micro Devices Inc Santa Clara CA 95054 USA

ISBN: (纸本)9798400700958

the pace of advancement of the top-end supercomputers historically followed an exponential curve similar to (and driven in part by) Moore's Law. Shortly after hitting the petaflop mark, the community started looking ahead to the next milestone: Exascale. However, many obstacles were already looming on the horizon, such as the slowing of Moore's Law, and others like the end of Dennard Scaling had already arrived. Anticipating significant challenges for the overall high-performance computing (HPC) community to achieve the next 1000x improvement, the U.S. Department of Energy (DOE) launched the Exascale computing Program to enable and accelerate fundamental research across the many technologies needed to achieve exascale computing. AMD had the opportunity to contribute to the so-called "*Forward" programs from the DOE, which were a series of public-private partnerships focused on research and co-design activities covering compute architectures, interconnects, memory systems, chiplets and packaging, software stacks, applications, and more. Some of the research from these programs can now be found in the world's first exascale supercomputer, some were a little ahead of their time and may have an impact in the coming years, and others simply did not pan out. In this paper, we provide a retrospective of AMD's nearly decade-long research journey covering how we tried to predict the architecture of a supercomputer a decade into the future, what we got right, what we got wrong, and some of the insights and learnings that we discovered along the way.

关键词： Exascale HPC high-performance computing supercomputing Frontier memory chiplets heterogeneous compute accelerated processing unit research

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VAQUERO: A Scratchpad-based Vector Accelerator for Query Processing 29

VAQUERO: A Scratchpad-based Vector Accelerator for Query Pro...

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29th IEEE International symposium on high-performance computer architecture (HPCA)

作者： Pavon, Julian Vargas Valdivieso, Ivan Marimon, Joan Figueras, Roger Moll, Francesc Unsal, Osman Valero, Mateo Cristal, Adrian Barcelona Supercomp Ctr Barcelona Spain Univ Politecn Cataluna Barcelona Spain

ISBN: (纸本)9781665476522

Database Management Systems (DBMS) have become an essential tool for industry and research and are often a significant component of data centers. there have been many efforts to accelerate DBMS application performance. One of the most explored techniques is the use of vector processing. Unfortunately, conventional vector architectures have not been able to exploit the full potential of DBMS acceleration. In this paper, we present VAQUERO, our Scratchpad-based Vector Accelerator for QUEry pROcessing. VAQUERO improves the efficiency of vector architectures for DBMS operations such as data aggregation and hash joins featuring lookup tables. Lookup tables are significant contributors to the performance bottlenecks in DBMS processing suffering from insufficient ISA support in the form of scatter-gather instructions. VAQUERO introduces a novel Advanced Scratchpad Memory specifically designed with two mapping modes - direct- and associative-mode. these mapping modes enable VAQUERO to accelerate real-world databases with workload sizes that significantly exceed the scratchpad memory capacity. Additionally, the associative-mode allows to use VAQUERO with DBMS operators that use hashed keys, e.g. hash-join and hash-aggregate. VAQUERO has been designed considering general DBMS algorithm requirements instead of being based on a particular database organization. For this reason, VAQUERO is capable to accelerate DBMS operators for both row- and column-oriented databases. In this paper, we evaluate the efficiency of VAQUERO using two highly optimized popular open-source DBMS, namely the row-based PostgreSQL and column-based MonetDB. We implemented VAQUERO at the RTL level and prototype it, by performing Place&Route, at the 7nm technology node. VAQUERO incurs a modest 0.15% area overhead compared with an Intel Ice Lake processor. Our evaluation shows that VAQUERO significantly outperforms PostgreSQL and MonetDB by 2.09x and 3.32x respectively, when processing operators and queries

关键词： Vector computing Scratchpad Memory Database Accelerator PostgreSQL MonetDB

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Multi-GPU accelerating strategies of Ant Colony Optimization algorithms using Rank Based and Strong Elitist versions 35

Multi-GPU accelerating strategies of Ant Colony Optimization...

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35th IEEE International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Avila, Andres I. Manuel Aedo, Juan Gonzalez-Flores, Mariela Univ La Frontera Dept Ingn Matemat Temuco Chile Univ Aysen Dept Cs Nat & Tecnol Coyhaique Chile

ISBN: (纸本)9798350381603

the most used problem to compare these metaheuristics is the classical Travelling Salesman Problem (TSP) on a network with sizes from tens to millions of nodes. Nature-based metaheuristics are the main source of optimization techniques to solve this problem. Although there is a zoo of possibilities, Ant Colony Optimization (ACO) is still one of the most efficient, parallel, and simple techniques to implement. the pheromone evaporation rate, alpha,beta, and ant number M are the four parameters fitted for finding the best solutions. Candidate list and the use of a source solution are efficient strategies to optimize large problems, but there are other strategies to improve quality solutions such as local search strategies. Among the local search techniques, k-opt search has proved to be very efficient to deal with path-crossing. the initial route is split into k sub-routes connected in (k- 1)!2(k-1) ways. thus, 3-opt is an efficient strategy balancing complexity and precision. Moreover, the best alpha and beta are the result of the used strategy. Finally, the solution is improved by accelerating through parallel versions with multiGPUs. In this article, four ACO algorithms were developed using two variations (Rank Based 3-opt and Strong Elitist 3-opt), each one with two strategies (candidate list and restricted). To test the algorithms, TSPLIB95 was used with test problems between N = 51 and 4, 461 nodes in a server with 4 RTX A4000 GPUs. After improving the algorithms and parallelization, the parameters are tuned to get the highest performance improving the local minimum search. Statistical analysis of repetitions shows good stability of the chosen metaheuristics.

关键词： Multi-GPU Ant Colony Optimization algorithms metaheuristics local search high performance

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I/O performance of multiscale finite element simulations on HPC environments 34

I/O performance of multiscale finite element simulations on ...

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34th IEEE International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Boito, Francieli Gomes, Antonio Tadeu A. Peyrondet, Louis Teylo, Luan Univ Bordeaux LaBRI INRIA Bordeaux INPCNRSUMR 5800 F-33400 Talence France Lab Nacl Comp Cient LNCC Av Getulio Vargas 333 BR-25651075 Petropolis RJ Brazil

ISBN: (数字)9781665451574

ISBN: (纸本)9781665451574

In this paper, we present MSLIO, a code to mimic the I/O behavior of multiscale simulations. Such an I/O kernel is useful for HPC research, as it can be executed more easily and more efficiently than the full simulations when researchers are interested in the I/O load only. We validate MSLIO by comparing it to the I/O performance of an actual simulation, and we then use it to test some possible improvements to the output routine of the MHM (Multiscale Hybrid Mixed) library.

关键词： high-performance computing parallel I/O numeric library I/O kernel mini-app multiscale simulation

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uSystolic: Byte-Crawling Unary Systolic Array 28

uSystolic: Byte-Crawling Unary Systolic Array

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28th Annual IEEE International symposium on high-performance computer architecture (HPCA)

作者： Di Wu San Miguel, Joshua Univ Wisconsin Dept ECE Madison WI 53706 USA

ISBN: (纸本)9781665420273

General matrix multiply (GEMM) is an important operation in broad applications, especially the thriving deep neural networks. To achieve low power consumption for GEMM, researchers have already leveraged unary computing, which manipulates bitstreams with extremely simple logic. However, existing unary architectures are not well generalizable to varying GEMM configurations in versatile applications and incompatible to the binary computing stack, imposing challenges to execute unary GEMM effortlessly. In this work, we address the problem by architecting a hybrid unary-binary systolic array, uSystolic, to inherit the legacy-binary data scheduling with slow (thus power-efficient) data movement, i.e., data bytes are crawling out from memory to drive uSystolic. uSystolic exhibits tremendous area and power improvements as a joint effect of 1) low-power computing kernel, 2) spatial-temporal bitstream reuse, and 3) on-chip SRAM elimination. For the evaluated edge computing scenario, compared with the binary parallel design, the rated-coded uSystolic reduces the systolic array area and total on-chip area by 59.0% and 91.3%, with the on-chip energy and power efficiency improved by up to 112.2x and 44.8x for AlexNet.

关键词： Power demand Processor scheduling Neural networks Random access memory computer architecture Systolic arrays Hybrid power systems

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Message from Program Chairs

Proceedings - Symposium on Computer Architecture and High Pe...

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proceedings - symposium on computer architecture and high performance computing 2024年 X页

作者： Osthoff, Carla Nelson Amaral, J. National Laboratory for Scientific Computing Brazil University of Alberta Canada

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proceedings - 2024 International Conference on Cyber-Enabled Distributed computing and Knowledge Discover, CyberC 2024

Proceedings - 2024 International Conference on Cyber-Enabled...

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16th International Conference on Cyber-Enabled Distributed computing and Knowledge Discover, CyberC 2024

ISBN: (纸本)9798331506896

the proceedings contain 37 papers. the topics discussed include: few-shot image classification method with label consistent and inconsistent self-supervised learning;a high performance ai-powered cache mechanism for IoT devices;Q-MMT: Qinqiang Opera generation based on multi-track music transformer;research on human combination continuous motion recognition method;multispectral registration algorithm based on fusion of infrared and color images;improved detection of forged and generated facial images based on ResNet-50;intelligent spectrum management for UAV swarm with multiple combat missions: a DQN-based solution;multispectral registration algorithm based on fusion of infrared and color images;and OCDE: adaptive differential evolution algorithm in distributed intelligent systems.

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high-Quality I/O Bandwidth Prediction with Minimal Data via Transfer Learning Workflow 36

High-Quality I/O Bandwidth Prediction with Minimal Data via ...

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36th IEEE International symposium on computer architecture and high-performance computing, SBAC-PAD 2024

作者： Povaliaiev, Dmytro Liem, Radita Kunkel, Julian Lofstead, Jay Carns, Philip RWTH Aachen University Chair of High Performance Computing IT Center Aachen Germany Georg-August Universität Göttingen/GWDG Göttingen Germany Sandia National Laboratory Albuquerque United States Argonne National Laboratory Lemont United States

ISBN: (纸本)9798350356168

Providing a high-quality performance prediction has the potential to enhance various aspects of a cluster, such as devising scheduling and provisioning policies, guiding procurement decisions, suggesting candidate applications for tuning, and identifying probable scaling and porting challenges. Creating such a prediction for the I/O metrics is still challenging, however, due to the intricate interplay of multiple cluster components, making this an ideal case for machine learning. Nevertheless, achieving the required accuracy level with machine learning calls for a substantial amount of high-quality data, which is often a difficult challenge for most HPC clusters. In this work we explore the use of transfer learning to predict the applications' I/O bandwidth based on a public dataset. As a result, our experiment can provide an I/O bandwidth prediction for a different cluster comparable to the current state-of-the-art result while employing 100 times less data than needed to construct the base model. Furthermore, we evaluate potential future improvements of the proposed workflow. © 2024 IEEE.

关键词： Adversarial machine learning

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Development of More Robust and Stable Logic Gates Using Novel Parameter Values for SiDB 16

Development of More Robust and Stable Logic Gates Using Nove...

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16th IEEE Latin American symposium on Circuits and Systems, LASCAS 2025

作者： Ruella, Emanuel V.C. Ferreira, Ricardo S. Vilela Neto, Omar P Nacif, Jose Augusto M. Science and Technology Institute Universidade Federal de Viçosa Brazil Brazil Universidade Federal de Minas Gerais Computer Science Department Brazil Brazil

ISBN: (纸本)9798331522124

As CMOS technology approaches its physical limits, there is a growing need to explore alternatives beyond CMOS, such as Silicon Dangling Bonds (SiDBs). SiDBs, utilizing Coulombic interactions, offer the potential for ultra-low energy consumption and high integration density. Recent research has introduced new parameter values for SiDB technology, specifically the thomas-Fermi Screening Length (Tp=1.80nm) and relative permittivity (r=4.10). this study presents a comprehensive library of logic gates based on these novel values, demonstrating significant stability and interference reduction improvements. Our contributions include: (1) A library of standard Boolean function gates, (2) Additional gates adapted from existing designs, and (3) A detailed comparison of gate performance using new versus old parameter values. the findings indicate that these new parameters enable more robust and compact circuit designs, advancing the potential of SiDB technology. © 2025 IEEE.

关键词： CMOS integrated circuits

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