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检索条件"任意字段=Proceedings - 24th International Conference on Distributed Computing Systems Workshops"

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Evaluation of the Memory Communication Traffic in a Hierarchical Cache Model for Massively-Manycore Processors

Evaluation of the Memory Communication Traffic in a Hierarch...

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Euromicro conference on Parallel, distributed and Network-Based Processing

作者： Sharifa Al Khanjari Wim Vanderbauwhede School of Computing Science University of Glasgow Glasgow UK

the scaling of semiconductor technologies is leading to processors with increasing numbers of cores. A key enabler in manycore systems is the use of Networks-on-Chip (NoC) as a global communication mechanism. the adoption of NoCs in manycore systems requires a shift in focus from computation to communication, as communication is fast becoming the dominant factor in processor performance. Many researchers have focused on direct communication between cores in the NoC, however in a manycore processor the communication is actually between the cores and the memory hierarchy. In this work, we investigate the memory communication traffic of shared threads in a hierarchical cache architecture. We argue that the performance scalability for shared-memory applications in a hierarchical cache architecture for systems with thousands of processor cores depends on the distance between threads sharing memory in terms of the cache hierarchy (the "memory distance"). We present latency and throughput results comparing fat quadtree, concentrated mesh and mesh topologies as a function of the "memory distance" between the threads. Our results using the ITRS physical data for 2023 show that the model of thread placement and the distance of placing them significantly affects the NoC performance, and that scale-invariant topologies perform better than flat topologies.

关键词： Instruction sets Topology Computer architecture three-dimensional displays Coherence Network topology

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10th international conference on Critical Information Infrastructures Security, CRITIS 2015

10th International Conference on Critical Information Infras...

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10th international conference on Critical Information Infrastructures Security, CRITIS 2015

ISBN: (纸本)9783319333304

the proceedings contain 24 papers. the special focus in this conference is on Critical Information Infrastructure Protection. the topics include: Security architecture and specification framework for safe and secure industrial automation;access control issues in utilizing fog computing for transport infrastructure;a cyber forensic taxonomy for SCADA systems in critical infrastructure;resilience assessment of interdependent critical infrastructure;a methodology for resilience optimisation of interdependent critical infrastructures;limitation of individual BCP/BCM ensuring interoperability among banks cooperation with local governments for socioeconomic resilience in Japan;critical infrastructure assessment by emergency management;knowledge-driven scenario development for critical infrastructure protection;recovering structural controllability on erdos-renyi graphs in the presence of compromised nodes;vulnerability against internet disruptions - a graph-based perspective;a statechart-based anomaly detection model for multi-threaded SCADA systems;controllability assessment for cascade effects in ICT-enabled power grids;information flow resilience of a retail company with regard to the electricity scenarios of the sicherheitsverbundsubung schweiz;a robust and efficient secure aggregation scheme in smart grids;a distributed continuous double auction framework for resource constrained microgrids;ARIMA-based modeling and validation of consumption readings in power grids;identifying critical infrastructure clusters via spectral analysis;nuances for a water industry critical infrastructure specification exemplar;on robustness in multilayer interdependent networks;a review of relevant standards and guidelines on the topic;the challenge of critical infrastructure dependency modelling and simulation for emergency management and decision making by the civil security authorities and a mean field model of coupled cascades in flow networks.

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Optimal Time and Energy Efficient Work Distributions in Heterogeneous systems

Optimal Time and Energy Efficient Work Distributions in Hete...

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Euromicro conference on Parallel, distributed and Network-Based Processing

作者： Valon Raca Eduard Mehofer Marcus Hudec Faculty of Computer Science University of Vienna Austria

Heterogeneous cluster architectures with different types of compute devices are wide-spread in the field of high performance computing introducing new kind of challenges. Time-efficient distribution of work onto heterogeneous devices is much more intricate than in the homogeneous case. Moreover, the use of heterogeneous devices makes it necessary to address energy efficiency as well. this results in bi-criteria optimization problems whereby often time efficiency and energy efficiency are conflicting objectives pushing in different directions. In this paper we define four optimization problems which are of particular interest for developers, give a formal description of these problems, and try to find optimal solutions for them efficiently with minimal effort. Essential is the fact that a user may specify time or energy constraints for which optimal work distributions onto the devices are determined. In addition, we raise the question how to recommend reasonable solutions, if no constraints have been specified. An experimental section examines the solutions obtained from our algorithms.

关键词： Optimization Time factors Energy consumption Computer architecture Clustering algorithms Hardware Computer science

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VerCors: A Layered Approach to Practical Verification of Concurrent Software

VerCors: A Layered Approach to Practical Verification of Con...

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Euromicro conference on Parallel, distributed and Network-Based Processing

作者： Afshin Amighi Stefan Blom Marieke Huisman Formal Methods and Tools University of Twente Enschede The Netherlands

this paper discusses how several concurrent program verification techniques can be combined in a layered approach, where each layer is especially suited to verify one aspect of concurrent programs, thus making verification of concurrent programs practical. At the bottom layer, we use a combination of implicit dynamic frames and CSL-style resource invariants, to reason about data race freedom of programs. We illustrate this on the verification of a lock-free queue implementation. On top of this, layer 2 enables reasoning about resource invariants that express a relationship between thread-local and shared variables. this is illustrated by the verification of a reentrant lock implementation, where thread-locality is used to specify for a thread which locks it holds, while there is a global notion of ownership, expressing for a lock by which thread it is held. Finally, the top layer adds a notion of histories to reason about functional properties. We illustrate how this is used to prove that the lock-free queue preserves the order of elements, without having to reverify the aspects related to data race freedom.

关键词： Message systems Synchronization Silicon Software History Concurrent computing Java

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Reasoning about Fences and Relaxed Atomics

Reasoning about Fences and Relaxed Atomics

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Euromicro conference on Parallel, distributed and Network-Based Processing

作者： Mengda He Viktor Vafeiadis Shengchao Qin João F. Ferreira Shenzhen University China School of Computing Teesside University UK Max Planck Institute for Software Systems (MPI-SWS) Germany

For efficiency reasons, weak (or relaxed) memory is now the norm on modern architectures. To cater for this trend, modern programming languages are adapting their memory models. the new C11 memory model [1] allows several levels of memory weakening, including non-atomics, relaxed atomics, release-acquire atomics, and sequentially consistent atomics. Under such weak memory models, multithreaded programs exhibit more behaviours, some of which would have been inconsistent under the traditional strong (i.e. sequentially consistent) memory model. this makes the task of reasoning about concurrent programs even more challenging. the GPS framework, recently developed by Turon et al.[22], has made a step forward towards tackling this challenge. By integrating ghost states, per-location protocols and separation logic, GPS can successfully verify programs with release-acquire atomics. In this paper, we present a program logic, an enhancement of the GPS framework, that can support the verification of a bigger class of C11 programs, that is, programs with release-acquire atomics, relaxed atomics and release-acquire fences. Key elements of our proposed logic include two new types of assertions, a more expressive resource model and a set of newly-designed verification rules.

关键词： Global Positioning System Radio frequency Message systems Semantics Cognition Synchronization Concurrent computing

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GPU-Accelerated Texture Analysis Using Steerable Riesz Wavelets

GPU-Accelerated Texture Analysis Using Steerable Riesz Wavel...

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Euromicro conference on Parallel, distributed and Network-Based Processing

作者： Anamaria Vizitiu Lucian Mihai Itu Ranveer Joyseeree Adrien Depeursinge Henning Müller Constantin Suciu Imaging and Computer Vision Corporate Technology Romania Automation and Information Technology Transilvania University of Brasov Romania HES-SO Sierre Institute of Information Systems Switzerland ETHZ Zürich Switzerland Medical Informatics University University Hospitals of Geneva Switzerland

Visual pattern recognition is a key research topic in the field of image processing and computer vision. Texture analysis based on steerable Riesz wavelets is powerful, but requires computing pixel-wise operations resulting in a run time in the order of days when large volumes of data are processed. To overcome this limitation we propose a Graphics Processing Unit (GPU) based solution. A standard CPU version is used as starting point for the development of baseline GPU versions. To further increase the performance, and to overcome compute and memory limitations we apply a series of optimization techniques, leading to five versions in total. the best performing GPU solution ensures a speed-up of 93× for the parallelized section of the application and of 29.6× for the entire application. Furthermore, we show that a higher Riesz order and/or a higher image resolution further increases the speed-up.

关键词： Graphics processing units Instruction sets Registers Support vector machines Memory management Kernel Training

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the Efficient In-band Management for Interconnect Network in Tianhe-2 System

The Efficient In-band Management for Interconnect Network in...

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Euromicro conference on Parallel, distributed and Network-Based Processing

作者： Jijun Cao Liquan Xiao Zhengbin Pang Kefei Wang Jiaqing Xu College of Computer National University of Defense Technology China Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology China

Interconnect network plays an important role in high performance computing systems. And its manageability directly affects the RAS (i.e., Reliability, Availability, and Serviceability) of the whole system. the Tianhe-2 system located in NSCC-gz (i.e., National Supercomputing Center of China in Guangzhou) uses proprietary interconnect network, which includes 5,856 high-radix network router chips (i.e., NRC) and 18,304 network interface chips (i.e., NIC). For such a very large-scale interconnect network, it is a great challenge to manage (such as configure, monitor, and debug) the numerous network chips and its network ports in an efficient way. By implementing the in-band management with very few hardware resources, the interconnect network in Tianhe-2 system achieves a highly efficient network management. In this paper, we introduce the design and implementation of the in-band management for interconnect network in Tianhe-2 system, especially emphasizing on several key features, including the set of achieved management functionalities, the architecture of network management, the format of management packets, the data flow and processing of management packets, etc. In this paper, we also evaluate the performance of in-band management by mainly comparing with out-band management scheme. the preliminary results demonstrate the efficiency of the in-band management for interconnect network in Tianhe-2 system.

关键词： Routing Ports (Computers) Network topology Optical switches Hardware Topology Registers

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X-Ray Computed Tomography Applied to Objects of Cultural Heritage: Porting and Testing the Filtered Back-Projection Reconstruction Algorithm on Low Power systems-on-Chip

X-Ray Computed Tomography Applied to Objects of Cultural Her...

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Euromicro conference on Parallel, distributed and Network-Based Processing

作者： Elena Corni Lucia Morganti Maria Pia Morigi Rosa Brancaccio Matteo Bettuzzi Giuseppe Levi Eva Peccenini Daniele Cesini Andrea Ferraro Department of Physics and Astronomy University of Bologna Bologna Italy Bologna Section Italian Institute for Nuclear Physics (INFN) Bologna Italy Enrico Fermi Center for Study and Research Roma Italy CNAF Section Italian Institute for Nuclear Physics (INFN) Bologna Italy

the embedded and high-performance computing (HPC) sectors, that in the past were completely separated, are now somehow converging under the pressure of two driving forces: the release of less power consuming server processors and the increased performance of the new low power systems-on-Chip (SoCs) developed to meet the requirements of the demanding mobile market. this convergence allows the porting to low power embedded architectures of applications that were originally confined to traditional HPC systems. In this paper, we present our experience of porting the Filtered Back-projection Algorithm to a low power, low cost system-on-chip, the NVIDIA Tegra K1, which is based on a quad core ARM CPU and on a NVIDIA Kepler GPU. this Filtered Back-projection Algorithm is heavily used in 3D Tomography reconstruction software. the porting has been done exploiting various programming languages (i.e. OpenMP, CUDA) and multiple versions of the application have been developed to exploit both the SoC CPU and GPU. the performances have been measured in terms of 2D slices (of a 3D volume) reconstructed per time unit and per energy unit. the results obtained with all the developed versions are reported and compared with those obtained on a typical x86 HPC node accelerated with a recent NVIDIA GPU. the best performances are achieved combining the OpenMP version and the CUDA version of the algorithm. In particular, we discovered that only three Jetson TK1 boards, equipped with Giga Ethernet interconnections, allow to reconstruct as many images per time unit as a traditional server, using one order of magnitude less energy. the results of this work can be applied for instance to the construction of an energy-efficient computing system of a portable tomographic apparatus.

关键词： Graphics processing units Image reconstruction Computer architecture Filtering algorithms Computed tomography Radiography

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proceedings - 2015 IEEE 24th international conference on Enabling Technologies: Infrastructures for Collaborative Enterprises, WETICE 2015

Proceedings - 2015 IEEE 24th International Conference on Ena...

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2015 24th IEEE international conference on Enabling Technologies: Infrastructures for Collaborative Enterprises, WETICE 2015

ISBN: (纸本)9781467376921

the proceedings contain 50 papers. the topics discussed include: engineering self-adaptive systems with the role-based architecture of Helena;collaborative infrastructure for on-demand crowdsourced tasks;a semantic framework for modeling adaptive autonomy in task allocation in robotic fleets;a mechanism for the causal ordered set representation in large-scale distributed systems;towards a provisioning algorithm for dynamic workflows in the cloud;collaborative autonomic container for the management of component-based applications;modeling change patterns for impact and conflict analysis in event-driven architectures;cognitive application area networks: a new paradigm for distributed computing and intelligent service orchestration;load index characterization: the scientific challenge and a survey approach;and a self-optimized storage for distributed data as a service.

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Cognitive Application Area Networks A New Paradigm for distributed computing and Intelligent Service Orchestration 24

Cognitive Application Area Networks A New Paradigm for Distr...

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IEEE 24th international conference on Enabling Technologies Infrastructures for Collaborative Enterprises

作者： Mikkilineni, Rao Morana, Giovanni Zito, Daniele C3 DNA Santa Clara CA 95054 USA

ISBN: (纸本)9781467376921

distributed systems are dynamic systems where software and hardware together deliver information processing services to allow modeling, interaction, reasoning, analysis and control of the external environment. the intent of the distributed computation is to execute computational workflows using computing resources. the software contains the algorithms that specify the tasks while the hardware provides the required resources to execute the algorithms. the initial structure is defined by the association of software with hardware and the dynamic structure is defined by their temporal evolution. the meta-knowledge of the intent of the algorithm, the association of specific algorithm to a specific device, their temporal evolution and exception handling when the computation deviates from the intent is outside the software and hardware design and is expressed in nonfunctional requirements. In this paper, we describe an architecture to capture the meta-knowledge in meta-containers and enforce the intent of the computation while the computation is in progress.

关键词： distributed computing cognitive application area networks distributed computing cluster DIME network architecture cognition service orchestration policy based application management

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