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The K2 parallel processor: architecture and hardware implementation

The K2 parallel processor: architecture and hardware impleme...

引用

Annual international symposium on Computer Architecture, ISCA

作者： M. Annaratone M. Fillo K. Nakabayashi M. Viredaz Integrated Systems Laboratory Swiss Federal Institute of Technology Zurich Switzerland

K2 is a distributed-memory parallel processor designed to support a multiuser, multitasking, time-sharing operating system and an automatically parallelizing Fortran compiler. The architecture and the hardware implementation of K2 are presented. The authors focus on the architectural features required by the operating system and the compiler. A prototype machine with 24 processors is currently being developed.< >

关键词： Hardware Operating systems Permission Sun Debugging Laboratories Time sharing computer systems Topology Information processing Process design

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A parallel architecture for data compression

A parallel architecture for data compression

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international symposium on parallel and distributed Processing (IPDPS)

作者： S. Henriques N. Ranganathan Center Microelectronics Research Department of Computer Science and Engineering University of South Florida Tampa FL USA

The authors describe a parallel algorithm and architecture for implementing the LZ technique for data compression. Data compression is the reduction of redundancy in data representation in order to decrease storage and communication costs. The LZ-based compression method is a very powerful technique and gives very high compression efficiency for text as well as image data. The proposed architecture is systolic and uses the principles of pipelining and parallelism in order to obtain high speed and throughput. The order of complexity of the computations is reduced from n/sup 2/ to n. The data compression hardware can be integrated into real time systems so that data can be compressed and decompressed on-the-fly. The basic processor cell for the systolic array is currently being implemented using CMOS VLSI technology.< >

关键词： parallel architectures Data compression Image coding CMOS technology parallel algorithms Costs Computer architecture Pipeline processing parallel processing Throughput

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Self scheduling and execution threads

Self scheduling and execution threads

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international symposium on parallel and distributed Processing (IPDPS)

作者： R.S. Francis A.N. Pears CSIRO DIT Carlton Australia La Trobe University Australia

Two major strategies exist for the exploitation of parallel execution on shared memory multiprocessors. Multiple threads of execution can be created within a shared program context and loop iterations can be scheduled between processors. While the two techniques are well established in isolation, the design of large, general purpose multi-user multiprocessors requires a seamless blend. The authors examine a set of system structures which combine the two parallel computing models to exploit inherent program parallelism. The objective is a general purpose parallel programming environment in which programs can create as many threads as desired, which are scheduled on the share of processor resource allocated to the program. From within any of these threads, the self scheduling of iterations interacts with the thread management so that free processor resource is dynamically allocated to parallel iterations.< >

关键词： Yarn Processor scheduling parallel processing Resource management Operating systems Australia Concurrent computing Programming environments Dynamic scheduling Process control

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parallel dynamic programming

Parallel dynamic programming

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international symposium on parallel and distributed Processing (IPDPS)

作者： V. Viswanathan S.-H.S. Huang Hongfei Liu Department of Computer Sciences University of Houston Houston TX USA

Recurrence formulations for various problems such as finding an optimal order of matrix multiplication, finding an optimal binary search tree and optimal triangulation of polygons assume a similar form. A CREW PRAM algorithm has been given to solve such dynamic programming problems. The algorithm uses O(n/sup 6//log n) processors and runs in O(log/sup 2/ n)time. A modified algorithm is presented which reduces the processor requirement to O(n/sup 6//log/sup 5/n) while maintaining the same time complexity of O(log/sup 2/ n).< >

关键词： Dynamic programming Binary search trees Computer science Phase change random access memory Open systems NASA Binary trees Equations H infinity control

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Computer network reliability evaluation from application's point of view

Computer network reliability evaluation from application's p...

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international symposium on parallel and distributed Processing (IPDPS)

作者： A. Kumar D.P. Agrawal Engineering Maths and Computer Science Department University of Louisville Louisville KY USA Department of Electrical & Computer Engineering North Carolina State University Raleigh NC USA

distributed computing systems are composed of processing elements, memory modules, data files, and programs. These shared resources are interconnected via communication links that enable a program (application) to run on a node by using data files available at other nodes. The authors introduce a very efficient one-step algorithm which can compute reliability parameters from an application's point of view directly, without requiring any a priori knowledge of multiterminal connections. This algorithm can be extended to evaluate many other reliability parameters such as computer network reliability, source to multiterminal reliability, distributed system reliability.< >

关键词： Computer network reliability distributed control distributed computing Telecommunication network reliability Application software Reliability engineering Computer science Computer networks Artificial intelligence

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Context streams a theoretical basis for a generic form of MIMD pipelining

Context streams a theoretical basis for a generic form of MI...

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international symposium on parallel and distributed Processing (IPDPS)

作者： T.E.A. Lees Department of Computer Sciences University of Edinburgh Edinburgh UK

Context flow (CF) is a canonical form of MIMD pipelining in which process contexts rather than either instructions or data are manipulated. The paper presents a formal definition of context flow. It defines the state of a CF computation as the stream of contexts which pass a particular point in a context flow graph during a given period of time. It shows that for a class of context flow graphs corresponding to dynamic multifunctional pipelines, the number of contexts which may exist at any point in a graph is bounded, and independent of the computation being performed. It presents methods for determining the numerical value of the upper bound or queue length for a variety of configurations of a acyclic graph.< >

关键词： Pipeline processing Hardware parallel processing Interleaved codes Computer science Upper bound Concurrent computing Data mining Councils Control systems

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Synthesis of simple distributed detection networks

Synthesis of simple distributed detection networks

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international symposium on parallel and distributed Processing (IPDPS)

作者： N.S.V. Rao Department of Computer Sciences Old Dominion University Norfolk VA USA

The article studies algorithmic issues of simple object detection problems in the context of a system consisting of a finite set of sensors S that monitor a workspace. Each sensor a in S detects the presence of any object that belongs to a certain subset, Det(a), of a given set of objects O. The detection problem is defined as follows: given that an object had been detected at a subset D contained in S of sensors, identify if the object in the workspace could be a member of O. If yes, compute the maximal set of such members. If not, declare the object in the workspace to be unidentified. Two versions are considered of this problem based on how the input is specified. In the forward detection problem, one is given (Det(a))/sub a in S/. In the backward detection problem, one is given (Set(b))/sub b in O/, where Set(b) is the set of sensors at which the object b in O would be detected. The article constructs a conceptual graph structure called the detection network that yields efficient implementation of detection algorithms using combinational circuits, message-based systems and parallel computing systems. It shows the problem of computing a network with minimum number of edges is computationally intractable, and then presents several polynomial-time approximation algorithms. Then it presents sequential algorithms to solve the detection problems with and without preprocessing. It also discusses parallel algorithms on shared memory systems and hypercube-based message passing systems. Finally, it shows that the problem of recognizing multiple objects is computationally intractable.< >

关键词： Network synthesis Object detection Computer networks Sensor systems Monitoring Detection algorithms Combinational circuits parallel processing Polynomials Approximation algorithms

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A probabilistic inference method with multiple evidences and its implementation using a layered network

A probabilistic inference method with multiple evidences and...

引用

international symposium on parallel and distributed Processing (IPDPS)

作者： A. Tanaka O. Nakamura NTT Communications and Information Processing Laboratories Musashino Tokyo Japan

The inference method can deal with multiple ambiguous evidences, and can describe effectiveness of evidences and relationships between evidences. Therefore, it is more advantageous than the Dempster-Shafer theory because of its ability to describe relationships between evidences. This method divides the whole world into possible worlds according to element value combinations. The probability of each possible world is decided so as to satisfy constraints corresponding to a priori knowledge and to maximize the entropy of the whole world. Furthermore, the method can be implemented using a layered network. In this network, individual network units do not have to perform complicated operations and connections between the layers are restricted. In other words, this network consists of simple units and restricted connections, thus, high speed processing will be possible using parallel processing.< >

关键词： Bayesian methods Artificial intelligence Information processing Laboratories Entropy parallel processing Humans Character recognition Expert systems Marine vehicles

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Multi-failure fault-tolerance of embedded loops on hypercubes: issues and performance study

Multi-failure fault-tolerance of embedded loops on hypercube...

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international symposium on parallel and distributed Processing (IPDPS)

作者： C.T. Liang W.T. Tsai Department of Computer Sciences University of Minnesota Minneapolis MN USA

The authors study the multi-failure fault-tolerance of hypercubes. Reconfiguration algorithms are proposed to reallocate the function of failed nodes to spare nodes so the communication structure of the interrupted parallel algorithms is preserved. Both clustered fault and concurrent fault are considered. Loops are selected as the embedded communication structures, where a wide variety of applications have been implemented. In early work, two classes of fault-tolerant embedded loops, Mapping II and III, have been designed and proved one-step reconfigurable for any single failure. The authors derive from shortest path algorithms a distributed reconfiguration algorithm for multiple failures on these embedded loops. Proof of reconfigurability for clustered fault is conducted for Mapping III. Performance of both mappings is evaluated by simulation with parameters such as the average number of tolerable failures, the average number of job migrations, and the utilization rate of nodes.< >

关键词： Fault tolerance Hypercubes Clustering algorithms parallel algorithms Network topology Hardware Computer science Computational modeling Large-scale systems Computer networks

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A comprehensive modeling for performance evaluation of regular interconnection network

A comprehensive modeling for performance evaluation of regul...

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international symposium on parallel and distributed Processing (IPDPS)

作者： C.C.-Y. Chen Hee Yong Youn Department of Computer Sciences University of North Texas Denton TX USA

Interconnection network is one of the major factors which determine the performance of a multiprocessor system. Therefore, it is imperative to have a model by which the efficiency of the interconnection network can be correctly evaluated for various application environments. The authors present an interconnection network evaluation mode where the memory bandwidth and processor acceptance probability are considered primary measures. The proposed analytical model includes typical network control policies such as bus arbitration and rejected request handling policies as well as home memory concept. The crossbar network is selected to test the model and computer simulation validates the correctness. The study also confirms that the home memory and dynamic bus arbitration policy improve the network performance.< >

关键词： Multiprocessor interconnection networks Bandwidth Multiprocessing systems Analytical models Testing Computer simulation Computer networks Application software Computer architecture parallel processing

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