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检索条件"任意字段=Proceedings International Symposium on Databases in Parallel and Distributed Systems"

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parallel execution of Lanczos algorithm in a CAM systolic ring

Parallel execution of Lanczos algorithm in a CAM systolic ri...

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international symposium on parallel and distributed Processing (IPDPS)

作者： C. Ko Department of Electrical and computer Engineering College of Engineering Rutgers University Piscataway NJ USA

The author presents an efficient array processing scheme to exploit Lanczos algorithm for solving a large-scale eigenvalue problem. He shows that an array of processing elements with content addressable memories (CAM), connected in a simple ring topology, can solve the problem efficiently. The nonzero elements of a problem matrix are stored in a content addressable memory for an efficient storage and the required operations are executed in a pipeline fashion around the systolic ring. The algorithm consists of two steps: Lanczos triangularisation followed by QR method to obtain full eigenvalues and eigenvectors. It is shown that the speedup obtained in such a system is almost linear with the number of processing elements used when the problem is partitioned to be executed with relatively small number of processing element.< >

关键词： Computer aided manufacturing CADCAM Eigenvalues and eigenfunctions Symmetric matrices Sparse matrices Associative memory Matrix decomposition Large-scale systems Topology Partitioning algorithms

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parallel time complexity of a heuristic algorithm for the k-center problem with usage weights

Parallel time complexity of a heuristic algorithm for the k-...

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international symposium on parallel and distributed Processing (IPDPS)

作者： Qingzhou Wang Kam Hoi Cheng Computer Science Department University of Houston Houston TX USA

ISBN: (纸本)0818620870

The authors analyze the parallel time-complexity of a heuristic algorithm for solving the NP-hard k-center problem with usage weights. The problem is to choose k vertices as service centers so that the maximum weighted service delivery distance to any vertex is minimized. The algorithm uses a greedy strategy to choose the vertex with maximum usage weights as the next service vertex. It generates results that are guaranteed to be no greater than twice the optimal solution values, which is the best possible polynomial time heuristic unless P=NP, and its uniprocessor time complexity is O(n/sup 3/). The authors show that the algorithm may be implemented on a multiprocessor system in O(n log/sup 2/ n) time, where n is the total number of vertices. They further show that even with unlimited parallelism, this algorithm will have higher than polylogarithmic time complexity unless polylogspace=P.< >

关键词： Heuristic algorithms Polynomials Multiprocessing systems Joining processes Computer science Algorithm design and analysis parallel processing Accidents Approximation algorithms Microwave integrated circuits

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Forward chaining parallel inference

Forward chaining parallel inference

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international symposium on parallel and distributed Processing (IPDPS)

作者： M.C. Rowe J. Labhart R. Bechtel S. Matney S. Carrow Merit Technology Inc.orporated Plano TX USA Naval Research Laboratory Inc. Washington D.C. DC USA

The paper describes the completed and ongoing efforts of the parallel Inferencing Performance Evaluation and Refinement project (PIPER). The PIPER inference engine is based on the Merit Enhanced Traversal Engine (METE) algorithm which is an extension of Forgy's (1979) RETE algorithm. To evaluate the efficacy of this design and implementation, an iterating 108 rule knowledge base was composed. This rule set was designed to roughly simulate the information rich nature of its target application domain, Strategic Defense Initiative contact discrimination, and was processed on from 7 to 89 Butterfly Plus processor nodes. Three uniprocessor control groups were also employed to gauge speed-up. Using the control group which produced the most conservation speed-up factors, the Phase I inference engine achieved a maximum true speed-up in excess of 31 utilizing 45 processors.< >

关键词： Production Inference algorithms Engines Laboratories Testing Assembly Load management parallel processing Pipeline processing Expert systems

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Topology of efficiently controllable banyan multistage networks

Topology of efficiently controllable banyan multistage netwo...

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international symposium on parallel and distributed Processing (IPDPS)

作者： A. Youssef B. Arden Department of Elect Engineering & Computer Sciences George Washington University Washington D.C. DC USA College of Engineering and Applied Science University of Rochester Rochester NY USA

Due to their unique path property, banyan multistage interconnection networks (MINs) can be self-routed using control tags. The paper introduces a number of routing control classes of MINs and studies their structure. These include the D-controllable networks where the control tags are the destination labels, the FD-controllable networks, where the control tags are function of the destination labels and the doubly D- or FD-controllable networks which are D- or FD-controllable forward and backward. The paper shows that all D- and FD-controllable networks have a recursive structure, and that all doubly D-controllable (resp., FD-controllable) networks are strictly (resp., widely) functionally equivalent to the baseline network. The subclass of MINs where the interconnections are digit permute is also studied and shown to be doubly FD-controllable and hence equivalent to the baseline. Finally, the paper presents an efficient parallel algorithm that relabels the terminals of any one network to simulate any other network in that subclass.< >

关键词： Network topology Control systems Routing Multiprocessor interconnection networks parallel algorithms Computational modeling parallel processing Costs Computer networks Educational institutions

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Scheduling precedence graphs to minimize total system time in partitionable parallel architectures

Scheduling precedence graphs to minimize total system time i...

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international symposium on parallel and distributed Processing (IPDPS)

作者： Hyeong-Ah Choi B. Narahari Dept. of Electr. Eng. & Comput. Sci. George Washington Univ. Washington DC USA Department of Electrical Engineering & Computer Sciences George Washington University Washington D.C. DC USA

Two issues are introduced into the scheduling problem: each of the sub-tasks can be performed using one of a number of parallel algorithms running on different configurations; and there is an overhead time to move data (reconfiguration time) from the configuration required by one algorithm to the configuration required by the algorithm of the successor sub-task. The execution time for each algorithm and the reconfiguration times between all pairs of algorithms are provided along with the precedence graph. The problem is to find for each sub-task the algorithm to be executed such that the total system time, which is the sum of the execution times and the data movement times of all the selected algorithms, is minimized. The authors show that the problem is NP-hard even when the total degree, of each node of the precedence graph is at most three. They show that it can be solved in polynomial time if the total degree of each node is at most two, thus completely closing the gap between the polynomially solvable cases and the NP-hard cases in terms of the maximum degree of the precedence graph.< >

关键词： parallel architectures Partitioning algorithms Processor scheduling parallel algorithms parallel processing Polynomials Concurrent computing Scheduling algorithm Process control Control systems

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The European Declarative System (EDS) as a platform for parallel logic programming

The European Declarative System (EDS) as a platform for para...

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international symposium on parallel and distributed Processing (IPDPS)

作者： K.-F. Wong U.C. Baron H. Benker S. Bescos A.B. Cheese F.J.N. Cosquer S.A. Delgado-Rannauro M. Dorochevsky P. Heuze M. Ibanez-Espiga J. Noye M. Paci M.J. Ratcliffe M.J. Reeve K. Schuerman A. Sexton A. Veron J. Xu Computer Architecture Group European Computer-Industry Research Centre GmbH Munich Germany

The overall architecture of the European Declarative System (EDS), ESPRIT II Project 2025 is briefly described. The aim of the project is to design and implement both the hardware and software for a parallel information server. The final system will be used to develop advanced business information systems. The EDS machine is designed to be a high speed backend accelerator, primarily for data/knowledge base applications, serving a range of host computers. It is a message passing multiprocessor with a distributed store, commonly referred to as a shared nothing architecture. Whilst shared nothing architectures are not novel, their application to declarative/symbolic languages is relatively new. The authors describe the EDS software activities at ECRC. A conclusion reporting the current status of the project is given.< >

关键词： Logic programming Computer architecture Hardware Switches Application software Message passing Network interfaces Communication switching Packet switching Dairy products

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Adaptive software cache management for distributed shared memory architectures

Adaptive software cache management for distributed shared me...

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Annual international symposium on Computer Architecture, ISCA

作者： J.K. Bennett J.B. Carter W. Zwaenepoel Department of Electrical & Computer Engineering Rice University Houston TX USA Department of Computer Sciences Rice University Houston TX USA

An adaptive cache coherence mechanism exploits semantic information about the expected or observed access behavior of particular data objects. The authors contend that, in distributed shared-memory systems, adaptive cache coherence mechanisms will outperform static cache coherence mechanisms. They have examined the sharing and synchronization behavior of a variety of shared-memory parallel programs. It is found that the access patterns of a large percentage of shared data objects fall into a small number of categories for which efficient software coherence mechanisms exist. In addition, the authors have performed a simulation study that provides two examples of how an adaptive caching mechanism can take advantage of semantic information.< >

关键词： Memory management Computer architecture Memory architecture Yarn Computer science Adaptive systems Hardware Pattern analysis

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Performance analysis of hierarchically structured multiple bus multiprocessor system

Performance analysis of hierarchically structured multiple b...

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international symposium on parallel and distributed Processing (IPDPS)

作者： A.K. Ramani N. Gore P.C. Sharma P.K. Chande School of Computer Sciences Devi Ahilya University Indore India Department of Computer Engineering Shri G.S. Institute of Technology and Science Indore India

This paper presents a discrete time model of multiple level multiprocessor network with multiple buses at each level of hierarchy. The model describes each processing element's (PE's) behavior by means of a semi-Markov process. It takes as input the number of PEs, the number of memory modules (MMs), number of buses, the mean think time of a PE and the first and second moments of connection time. The model produces as output the bandwidth, the MM utilization PE utilization, average queue length, and average wait-time experienced by a PE while waiting to access a MM. An important design issue in the system under consideration is to optimize the communication network at each hierarchical level, meeting the overall communication requirements. The model developed is used to study the system behavior with different accessing patterns and design changes in the interconnection network at different hierarchical levels, enabling optimization of the design scheme.< >

关键词： Performance analysis Multiprocessing systems Design optimization Multiprocessor interconnection networks distributed computing Bandwidth Communication networks Process control Computerized monitoring Computer architecture

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Implementation and evaluation of a parallel PMS simulator

Implementation and evaluation of a parallel PMS simulator

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international Conference on databases, parallel Architectures and Their Applications

作者： M. Rao Z. Segall Department of Electrical & Computer Engineering Carnegie Mellon University Pittsburgh PA USA The School of Computer Science Carnegie Mellon University Pittsburgh PA USA

The sources of parallelism in an event-driven simulator have been investigated. First, a simple and straightforward parallelization strategy was implemented. It was observed that this strategy did not provide sufficient parallelism. Then the advance scheduling strategy was developed, which has yielded a significantly higher degree of parallelism. The main contribution of this research has been the development of this advance scheduling strategy. This strategy trades a small amount of inaccuracy in the simulation results for a large gain in the amount of parallelism extracted from the simulator. This strategy can be effectively applied for statistical simulators, because the statistical methods of simulation themselves introduce variations in the results. It was observed that, with a proper choice for the overlap distance, the error in the final results is comparable to the variation in the results introduced by the statistical simulation methods employed. A modified implementation of the event queue (Runqueue), which exploits the disorder in event scheduling created by the advance scheduling strategy, is presented. This implementation should significantly reduce contention for the Runqueue. A simulation model was implemented to simulate a distributed memory architecture proposed by D. Black, Z. Segall, and L. Rudolph. With the help of this simulation model, extensive experiments can be conducted to determine the strengths and weaknesses of the proposed architecture.< >

关键词： Computational modeling Computer architecture parallel processing Analytical models Multiprocessing systems Computer science Computer performance Costs Microprocessors High performance computing

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1st international Conference on Cryptology, AUSCRYPT 1990

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1st international Conference on Cryptology, AUSCRYPT 1990

ISBN: (纸本)9783540530008

The proceedings contain 39 papers. The special focus in this conference is on Cryptology. The topics include: On the formal analysis of PKCS authentication protocols;some remarks on authentication systems;meet-in-the-middle attack on digital signature schemes;a binary sequence generator based on Ziv-Lempel source coding;a fast iterative algorithm for a shift register initial state reconstruction given the noisy output sequence;parallel generation of pseudo-random sequences;large primes in stream cipher cryptography;comparison of block ciphers;key scheduling in des type cryptosystems;direct demonstration of the power to break Public-Key cryptosystems;lOKI — A cryptographic primitive for authentication and secrecy applications;permutation generators of alternating groups;showing credentials without identification transferring signatures between unconditionally unlinkable pseudonyms;a (non-Practical) three-pass identification protocol using coding theory;demonstrating possession without revealing factors and its application;anonymous one-time signatures and flexible untraceable electronic cash;dyadic matrices and their potential significance in cryptography (abstract);a note on strong fibonacci pseudoprimes;on the significance of the directed acyclic word graph in cryptology;solving equations in sequences;continued fractions and the Berlekamp-Massey algorithm;the practical application of state of the art security in real environments;rSA as a benchmark for multiprocessor machines;range equations and range matrices: A study in statistical database security;record encryption in distributed databases;vLSI design for exponentiation in GF(2);a fast modular-multiplication module for smart cards;minòs: Extended user authentication;universal logic sequences;the three faces of information security;nonlinear generators of binary sequences with controllable complexity and double key.

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