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Dynamic simulator for WIP analysis in semiconductor manufacturing

Dynamic simulator for WIP analysis in semiconductor manufact...

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IEEE international symposium on Semiconductor Manufacturing

作者： D.W. Collins V. Lakshman L.D. Collins Arizona State University Mesa AZ USA

We present a FAB Simulator (FS) and Capacity Planner (CP) that permits the operational planner to introduce new product into an existing production mix with confidence as to the customer delivery dates and FAB Capacity This paper describes the implementation of these two dynamic tools in a semiconductor FAB in Arizona. These tools assist the operational planner with the planning of the daily production mix. This FAB produces 100's of different bipolar devices using 36 process flows. The key to success in calculating present and future production goals is real time operational level tracking. Real time tracked data includes data gathered from the Manufacturing Execution System (MES) for each product's work-in-process (WIP), process flow routing, and data gathered from the equipment utilization and emergency maintenance databases. This key information is fed through a GUI linked to the CP which in turn controls the stochastic dynamic simulation model of the FS. These links provide the operational planner with dynamic production data in real time and simulated time for decision-making. The CP and FS are running in parallel and are linked directly with the FAB's MES maintaining current production data.

关键词： Analytical models Virtual manufacturing Semiconductor device manufacture Production planning Real time systems Manufacturing processes Routing databases Graphical user interfaces Stochastic processes

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A Design Study of Alternative Network Topologies for the Beowulf parallel Workstation 96

A Design Study of Alternative Network Topologies for the Beo...

引用

proceedings of the 5th IEEE international symposium on High Performance distributed Computing

作者： Chance Reschke Thomas Sterling Daniel Ridge Donald Becker Phillip Merkey Daniel Savarese

ISBN: (纸本)9780818675829

Coupling PC-based commodity technology with distributed computing methodologies provides an important advance in the development of single-user dedicated systems. Beowulf is a class of experimental parallel workstations developed to evaluate and characterize the design space of this new operating point in price-performance. A key factor determining the realizable performance under real-world workloads is the means devised for interprocessor communications. A study has been performed to characterize a family of interconnect topologies feasible with low cost mass market network technologies. Behavior sensitivities to packet size and traffic density are determined. Findings are presented which compare more complex segmented topologies to the earlier parallel ``channel bonded'' scheme. It is shown that in many circumstances the more complex topologies perform better, and in some circumstances software routing techniques compare favorably to more expensive hardware switch mechanisms.

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Optimizing Concurrent Query Execution on Modern Multisocket Multicore Platform

Optimizing Concurrent Query Execution on Modern Multisocket ...

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IEEE symposium on Reliable distributed systems Workshops (SRDSW)

作者： Fang Xi Takeshi Mishima Haruo Yokota Department of Computer Science Tokyo Institute of Technology Tokyo Japan

The upcoming generation of computer hardware brought several new challenges for underling software. The number of cores on a chip grows exponentially, allowing for an ever-increasing number of processes to execute in parallel. Therefore, how to efficiently utilize all of the concurrent processing ability provided by multi-core platform becomes critical for achieving good system performances. We propose a CARIC-DA framework which optimizes the performance of DBMS on multicore platforms. Our middleware can improve the performance of the private cache levels by dispatching concurrent database queries to run on different processor cores according to the data needs of each query. Extensive experiments from microbenchmark to TPC-C benchmark have confirmed the effectiveness of CARIC-DA in improving the cache performance and providing higher throughput for DBMSs on modern AMD multicore platform. However, the multicore platforms are becoming more and more diverse and complex in recent years. Different manufactures are making different efforts to boost their performance by adopting different techniques. Therefore, it is important for software to be well turned according to the specific hardware features in order to fully take advantage of the target multicore platforms. In this paper, we analyzed the efficiency of our CARIC-DA framework on the modern multicore Intel platform. We compared the performance of different deployment strategies where we vary the mapping relationship between database processes and processor cores from Hyper-Threading enable to disable configurations. We evaluated the impact of CARIC-DA for different cache levels and for different query types on the Intel multicore platform.

关键词： Multicore processing Middleware databases Hardware Proposals Sockets

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Limits to the performance of software shared memory: a layered approach

Limits to the performance of software shared memory: a layer...

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IEEE symposium on High-Performance Computer Architecture

作者： A. Bilas Dongming Jiang Yuanyuan Zhou J.P. Singh Department of Electrical and Computer Engineering University of Toronto Toronto ONT Canada Department of Computer Science Princeton University Princeton NJ USA

Much research has been done in fast communication on clusters and in protocols for supporting software shared memory across them. However, the end performance of applications that were written for the more proven hardware-coherent shared memory is still not very good on these systems. Three major layers of software (and hardware) stand between the end user and parallel performance, each with its own functionality and performance characteristics. They include the communication layer, the software protocol layer that supports the programming model, and the application layer. These layers provide a useful framework to identify the key remaining limitations and bottlenecks in software shared memory systems, as well as the areas where optimization efforts might yield the greatest performance improvements. This paper performs such an integrated study, using this layered framework, for two types of software distributed shared memory systems: page-based shared virtual memory (SVM) and fine-grained software systems (FG). For the two system layers (communication and protocol), we focus on the performance costs of basic operations in the layers rather than on their functionalities. This is possible because their functionalities are now fairly mature. The less mature applications layer is treated through application restructuring. We examine the layers individually and in combination, understanding their implications for the two types of protocols and exposing the synergies among layers.

关键词： Software performance Application software Protocols Hardware Software systems parallel programming Support vector machines Cost function Software libraries Computer science

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parallel Retrograde Analysis on Different Architecture 01

Parallel Retrograde Analysis on Different Architecture

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proceedings of the 10th IEEE international symposium on High Performance distributed Computing

作者： Ren Wu

Abstract: Retrograde analysis is an efficient exhaustive search method. It is a powerful tool that can be used in solving problems where end states have known values but starting states do not. It has been widely used to solve mathematically-precise games such as chess endgames, and is potentially usable in energy-minimization problems. With increasing computing power, both in speed and storage capacity, retrograde analysis will become more and more useful. This paper looks at successful applications to games, the challenges ahead, and the modifications that are required to utilize distributed hardware. The power and the usefulness of retrograde analysis are still limited by the computing resources one has access to. Today, the best sequential retrograde algorithms are capable of solving problems with about 10 9 states in a few hours on a standard personal computer. Bigger problems need more powerful computers, or take much longer to solve, or are simply out of reach of today's technologies. Introducing parallelism to retrograde analysis is a natural way to attack the bigger problems. There are today three main architectures available for doing parallel retrograde analysis: namely Symmetric Multiprocessor systems, High-speed network based distributed systems, and Internet based distributed systems. In this paper, we discuss some of the key issues in doing parallel retrograde analysis on these different architectures. Technical challenges are addressed in detail, as well as some examples and proposals. These examples and proposals are drawn from various board games, but the ideas can be applied to other problem domains.

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Checkpointing and rollback of wide-area distributed applications using mobile agents

Checkpointing and rollback of wide-area distributed applicat...

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international symposium on parallel and distributed Processing (IPDPS)

作者： Jiannong Cao G.H. Chan Weijia jia T.S. Dillon Internet Computing and E-Commerce Lab Department of Computing Hong Kong Polytechnic University Hong Kong China Department of Computer Science City University of Hong Kong Hong Kong China

ISBN: (纸本)0769509908

We consider the problem of designing rollback error recovery algorithms for dynamic, wide area distributed systems like the Internet. The characteristics and the scale of such a system complicate the design and performance of the algorithms. Traditional message passing based algorithms incur large overhead, in both the network traffic and message passing delay, in such a wide-area environment. In this paper, we propose a novel approach to designing checkpointing and rollback algorithms using mobile agents as an aid. Using mobile agent leads to a reduction of the total amount of communication and allows us to design algorithms that take the advantage of the most up to date system information for decision making. It also allows us to develop algorithms implementing flexible and adaptive policies. A mobile agent enabled hybrid algorithm combining independent and coordinated checkpointing is proposed. A prototype of the algorithms is developed using IBM's Aglets. Results of performance evaluation are presented and discussed.

关键词： Checkpointing Algorithm design and analysis Mobile agents Message passing Heuristic algorithms Internet Telecommunication traffic Mobile communication Decision making Prototypes

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Simulating heterogeneous models on multi-core platforms using Julia's computing language parallel potential 20

Simulating heterogeneous models on multi-core platforms usin...

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proceedings of the IEEE/ACM 24th international symposium on distributed Simulation and Real Time Applications

作者： Sergey Suslov Michael Schiek Markus Robens Christian Grewing Stefan van Waasen ZEA-2 - Electronic Systems Germany

This paper addresses the questions of high-level system modelling using heterogeneous multi-tool modelling environment on parallel multi-core processing systems for simulation acceleration. The modelling technique has been applied for high-level validation of a high-precision Indoor Positioning System for Motion Analysis (IPS-MA) developed in the Central Institute Electronic systems (ZEA-2) of the Research Center Juelich GmbH. The heterogeneous modelling environment has been built using an implementation-level model designed in Matlab Simulink, a verification model for describing the system environment using Modelica language, and Julia language for automatic generation of binding modelling environment and parallelizing the simulation of the overall model. The approach showed a good flexibility in system description and verification in the multi-instrument modelling environment and a good performance gain due to simulation parallelism.

关键词： modelica Julia computing language high level system modelling parallelized simulation distributed simulation functional verification

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Pufferscale: Rescaling HPC Data Services for High Energy Physics Applications

Pufferscale: Rescaling HPC Data Services for High Energy Phy...

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IEEE/ACM international symposium on Cluster Computing and the Grid (CCGRID)

作者： Nathanaël Cheriere Matthieu Dorier Gabriel Antoniu Stefan M. Wild Sven Leyffer Robert Ross Inria CNRS IRISA Univ. Rennes Rennes France Argonne National Laboratory Lemont IL USA

ISBN: (数字)9781728160955

User-space HPC data services are emerging as an appealing alternative to traditional parallel file systems, because of their ability to be tailored to application needs while eliminating unnecessary overheads incurred by POSIX compliance. The High Energy Physics (HEP) community is progressively turning towards such services to enable high-throughput accesses under heavy concurrency to billions of event data produced by instruments and consumed by subsequent analysis workflows. Such services would benefit from the possibility to be rescaled up and down to adapt to changing workloads, as experimental campaigns progress , in order to optimize resource usage. This paper formalizes rescaling a distributed storage system as a multi objective optimization problem considering three criteria: load balance, data balance, and duration of the rescaling operation. We propose a heuristic for rapidly finding a good approximate solution, while allowing users to weight the criteria as needed. The heuristic is evaluated with Pufferscale, a new rescaling manager for microservice-based distributed storage systems. To validate our approach in a real-world ecosystem, we showcase the use of Pufferscale as a means to enable storage malleability in the HEPnOS storage system for HEP applications.

关键词： Servers Virtual machining High energy physics distributed databases Load management Measurement Peer-to-peer computing

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Reconfigurable mesh-connected processor arrays using row-column bypassing and direct replacement

Reconfigurable mesh-connected processor arrays using row-col...

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international symposium on parallel Architectures, Algorithms and Networks (ISPAN)

作者： N. Tsuda T. Shimizu Computer & Network Systems Core Kanazawa Institute of Technology Japan

ISBN: (纸本)0769509363

This paper proposes an advanced reconfiguration scheme using row-column bypassing and direct replacement for two-dimensional mesh-connected processing-node arrays that makes an array usable for massively parallel computing and stand-alone computing in an efficient divided manner. This scheme uses an array providing a switching circuit in every node for row-column bypassing and a simple bypass network with a tree structure allocated to the array by graph-node coloring with a minimum inter-node distance of three for direct replacement. It can reconfigure a subarray with a regular matrix of free nodes usable for parallel computing in the array while allowing a small delay in the mesh connections but maintaining a communication path from every busy node being used as stand-alone computing to the outside of the array. The direct replacement is used for substitution of busy nodes which are not covered by row-column bypassing with free nodes located in the rows or columns to be bypassed, helping to enlarge the size of the reconfigured subarray. The bypass allocation with a minimum distance of three enables distributed communications and simple routing in the array while attaining a large success probability of the direct replacement. The proposed scheme is advantageous for constructing fault-tolerant massively parallel systems by using personal computers or workstations as processing nodes and Ethernet devices for interconnections.

关键词： parallel processing Concurrent computing Switching circuits Tree data structures Matrices Delay Routing Fault tolerant systems Microcomputers Workstations

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Considerations on transaction response time and configuration checking in autonomous decentralized DB (ADDS)

Considerations on transaction response time and configuratio...

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international symposium on Autonomous Decentralized systems (ISADAS)

作者： I. Kaji K. Kano Department of Space Design and Information System School of Project Design Miyagi University Kurokawa Miyagi Japan

In a distributed computing environment, the autonomous decentralized database system (ADDS) has been proposed to avoid the single point of failure. In ADDS, the update operations at each node are autonomously performed without communicating with other nodes if the amount of update requests are within the allowance volume (AV), thus the short response time of the transactions can be realized. Each node starts the AV adjustments when given AV amounts reach the threshold value, and gets the AV from relatively surplus nodes. To communicate with other nodes, there are two types of communications, one is a point to point (P2P) communication and the other is a mobile agent (MA) circulation. This paper discusses the relationship among the message amount, the configuration check frequency and the transaction response time in the P2P communication. We have defined the configuration checking frequency (f) that expresses how frequently a node confirms the configuration per AV request. It is expected that the value f which gives the minimum transaction response may exist. The simulator has been developed to evaluate the relationship and simulations have been performed in various parameters.

关键词： Delay Database systems Mobile communication distributed databases distributed computing Frequency Mobile agents Computational modeling Information systems Performance evaluation

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