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Skew-Aware Task Scheduling in Clouds

Skew-Aware Task Scheduling in Clouds

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2013 IEEE Seventh international symposium on Service-Oriented System Engineering

作者： Dongsheng Li Yixing Chen Richard Hu Hai National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology China Raffles Business Institute Singapore

ISBN: (纸本)9781467356596

Data skew is an important reason for the emergence of stragglers in MapReduce-like cloud systems. In this paper, we propose a Skew-Aware Task Scheduling (SATS) mechanism for iterative applications in MapReduce-like systems. The mechanism utilizes the similarity of data distribution in adjacent iterations of iterative applications to reduce the straggle problem caused by data skew. It collects the data distribution information during the execution of tasks for the current iteration, and uses the information to guide data partitioning in tasks for the next iteration. We implement the mechanism in the HaLoop system and deploy it in a cluster. Experiments show that the proposed mechanism could deal with the data skew and improve the load balancing effectively.

关键词： Load management distributed databases File systems Processor scheduling Computational modeling Data models Data structures

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Filesystem aware scalable I/O framework for data-intensive parallel applications

Filesystem aware scalable I/O framework for data-intensive p...

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2013 IEEE 37th Annual Computer Software and Applications Conference, COMPSAC 2013

作者： Xu, Rengan Araya-Polo, Mauricio Chapman, Barbara Department of Computer Science University of Houston Houston United States Geophysics Development Repsol Houston United States

ISBN: (纸本)9780769549798

The growing speed gap between CPU and memory makes I/O the main bottleneck of many industrial applications. Some applications need to perform I/O operations for very large volume of data frequently, which will harm the performance seriously. This work's motivation are geophysical applications used for oil and gas exploration. These applications process Terabyte size datasets in HPC facilities. The datasets represent subsurface models and field recorded data. In general term, these applications read as inputs and write as intermediate/final results huge amount of data, where the underlying algorithms implement seismic imaging techniques. The traditional sequential I/O, even when couple with advance storage systems, cannot complete all I/O operations for so large volumes of data in an acceptable time range. parallel I/O is the general strategy to solve such problems. However, because of the dynamic property of many of these applications, each parallel process does not know the data size it needs to write until its computation is done, and it also cannot identify the position in the file to write. In order to write correctly and efficiently, communication and synchronization are required among all processes to fully exploit the parallel I/O paradigm. To tackle these issues, we use a dynamic load balancing framework that is general enough for most of these applications. And to reduce the expensive synchronization and communication overhead, we introduced a I/O node that only handles I/O request and let compute nodes perform I/O operations in parallel. By using both POSIX I/O and memory-mapping interfaces, the experiment indicates that our approach is scalable. For instance, with 16 processes, the bandwidth of parallel reading can reach the theoretical peak performance (2.5 GB/s) of the storage infrastructure. Also, the parallel writing can be up to 4.68x (speedup, POSIX I/O) and 7.23x (speedup, memory-mapping) more efficient than the serial I/O implementation. Since, mo

关键词： Dynamic loads

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Generating efficient data movement code for heterogeneous architectures with distributed-memory

Generating efficient data movement code for heterogeneous ar...

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international Conference on parallel Architecture and Compilation Techniques (PACT)

作者： Roshan Dathathri Chandan Reddy Thejas Ramashekar Uday Bondhugula Department of Computer Science and Automation Indian Institute of Science Bangalore India

ISBN: (纸本)9781479910205

Programming for parallel architectures that do not have a shared address space is extremely difficult due to the need for explicit communication between memories of different compute devices. A heterogeneous system with CPUs and multiple GPUs, or a distributed-memory cluster are examples of such systems. Past works that try to automate data movement for distributed-memory architectures can lead to excessive redundant communication. In this paper, we propose an automatic data movement scheme that minimizes the volume of communication between compute devices in heterogeneous and distributed-memory systems. We show that by partitioning data dependences in a particular non-trivial way, one can generate data movement code that results in the minimum volume for a vast majority of cases. The techniques are applicable to any sequence of affine loop nests and works on top of any choice of loop transformations, parallelization, and computation placement. The data movement code generated minimizes the volume of communication for a particular configuration of these. We use a combination of powerful static analyses relying on the polyhedral compiler framework and lightweight runtime routines they generate, to build a source-to-source transformation tool that automatically generates communication code. We demonstrate that the tool is scalable and leads to substantial gains in efficiency. On a heterogeneous system, the communication volume is reduced by a factor of 11× to 83× over state-of-the-art, translating into a mean execution time speedup of 1.53×. On a distributed-memory cluster, our scheme reduces the communication volume by a factor of 1.4× to 63.5× over state-of-the-art, resulting in a mean speedup of 1.55×. In addition, our scheme yields a mean speedup of 2.19× over hand-optimized UPC codes.

关键词： Receivers distributed databases Computer architecture Runtime Tiles Program processors Computational modeling

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Reducing false transactional conflicts with speculative sub-blocking state-An empirical study for ASF transactional memory system

Reducing false transactional conflicts with speculative sub-...

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2013 IEEE 37th Annual Computer Software and Applications Conference, COMPSAC 2013

作者： Nai, Lifeng Lee, Hsien-Hsin S. School of Electrical and Computer Engineering Georgia Institute of Technology United States

ISBN: (纸本)9780769549798

Conflict detection and resolution are among the most fundamental issues in transactional memory systems. Hardware transactional memory (HTM) systems such as AMD's Advanced Synchronization Facility (ASF) employ inherent cache coherence protocol messages to perform conflict detection among transactions. Such an implementation has the advantage of design simplicity, nonetheless, it also generates false transactional conflicts due to false sharing within cache lines, unnecessarily reducing the overall performance. In this work, we first investigated the behavior of false transactional conflicts under the AMD's ASF system. It is found that false conflicts showed rather stable pattern within each cache line that subsequently inspired our false transactional conflict reduction technique using our proposed speculative sub-blocking state. By adding an extra speculative state for each cache line's sub-block, we can maintain conflict detection at the granularity of sub-blocks while keeping the original cache coherence protocol intact. The overall design is simple and highly implementable for achieving a high-efficiency HTM system with minimum impact in hardware. We evaluated our proposed technique using PTLsim-ASF and compared it with a baseline ASF HTM system and an ideal system with no false transactional conflict. Our results showed that the proposed lightweight technique can avoid false conflicts effectively and efficiently. With four sub-blocks in a cache line, our technique can eliminate 56.4% false transactional conflicts and 31.3% of all transactional conflicts on average, which approaches the performance of an ideal system. © 2013 IEEE.

关键词： parallel programming

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Accelerating all-to-all protein structures comparison with TMalign using a NoC many-cores processor architecture

Accelerating all-to-all protein structures comparison with T...

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IEEE international symposium on parallel and distributed Processing Workshops and PhD Forum

作者： Anuj Sharma Antonis Papanikolaou Elias S. Manolakos Department of Informatics and Telecommunications University of Athens Institute of Communication and Computer Systems National Technical University of Athens

ISBN: (纸本)9781479913725

Computational challenges for the one-to-many and many-to-many protein structure comparison (PSC) problem are a result of several factors: constantly expanding large-size structural proteomics databases, high computational complexity of pairwise protein comparison algorithms, and the multitude of pairwise comparison approaches used in the field. Advances in processor architectures, such as many-core CPUs, have enabled them to support parallelism making them of interest in speeding up PSC techniques. We present rckAlign, an implementation of the popularly used TM-align PSC algorithm, designed for the Single-Chip Cloud Computer (SCC), an experimental processor created by Intel Labs. We developed a skeleton library, rckskel, and implemented a master-slaves variant of TM-align to exploit the parallelism offered by the SCC. We evaluated rckAlign on the SCC and compared it with existing TM-align software running on a dual-core AMD CPU (2.4 GHz) and on a single-core Intel P54C Pentium CPU (800 MHz). We observed an 11-fold speedup relatively to the former and a 44-fold speedup relatively to the latter. A key aspect of the performance of rckAlign on the SCC, is the almost linear speedup achieved with the number of SCC cores used as slaves. The method presented can easily be applied to other PSC algorithms and extended to running multiple PSC algorithms within the same SCC chip.

关键词： Protein structure comparison TM-align Manycore processors parallel algorithms Master-slaves parallel computing

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Multiprocessor implementation of parallel multiobjective genetic algorithm for optimized allocation of chlorination stations in drinking water distribution system-a new water quality model approach

Multiprocessor implementation of parallel multiobjective gen...

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13th IFAC symposium on Large Scale Complex systems: Theory and Applications, LSS 2013

作者： Ewald, Grzegorz Zubowicz, Tomasz Brdys, Mietek A. Department of Control Systems Engineering Gdansk University of Technology ul. G. Narutowicza 11/12 80-233 Gdansk Poland Department of Electronic Electrical and Computer Engineering College of Engineering and Physical Sciences University of Birmingham Edgbaston Birmingham B15 2TT United Kingdom

The Critical Infrastructure systems (CISs) have received in recent years a consid- erable attention due to their heavy impact on sustainable development of modern societies. Most CISs may be classified as large scale complex systems of network structure, inuenced by strong interactions form the surrounding environment, internal and external interconnections. The later is a result of inter-CIS dependencies. The control, monitoring and control of these system is crucial to guaranty safe access to the resources distributed by the means of CIS. Among those systems the Drinking Water Distribution System (DWDS) may be found { a nonlinear dynamic carrier-load networked system. To handle these systems in a proper (robustly feasible) manner one needs to consider a nontrivial control task complimented by a set of input and state constraints. This surely points to model predictive optimal control schemes. To carry on the control a set of actuators { disinfectant booster stations { needs to be allocated within the DWDS to enable the control system to be robustly feasible. The task of optimised allocation has been addressed within this paper based on old (linear) and new (nonlinear) quality models in order to determine the impact of model structure and thus precision on the allocation results. The allocation task is formulated as a multiobjective, nonlinear/linear mixed-integer optimisation problem to be solved by a genetic algorithm (implementation of NSGA-II) due to nature of the problem. The newly obtained numerical examples are to illustrate the results. For this purpose a Chojnice (city in northern Poland) DWDS case study plant was utilised. © IFAC.

关键词： Water distribution systems

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A GPGPU Algorithm for c-Approximate r-Nearest Neighbor Search in High Dimensions

A GPGPU Algorithm for c-Approximate r-Nearest Neighbor Searc...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Lee A. Carraher Philip A. Wilsey Fred S. Annexstein School of Electronic and Computing Systems University of Cincinnati Cincinnati USA

ISBN: (纸本)9781479913725

Nearest Neighbor search is one of the simplest and most intuitive ideas in data mining. Due to it's simplicity and diverse utility, Nearest Neighbor search is often found to be the workhorse of a variety of data mining, machine learning, and computer vision algorithms. For very high dimensional data, the naive linear search tends to be optimal. This is due to the so called curse of dimensionality in database search. To accelerate the search time, may researchers have turned to the power and efficiency of GPGPU computing; mainly for computing the data intensive distance metrics. Though promising speedups are achieved through this method, it fails to capitalize on many of the recent advances in algorithms for bounded error approximate nearest neighbor searches. Approximate nearest neighbor methods give satisfactory results, especially in very large and possibly redundant datasets, while boasting sub-linear search complexities. In this paper we present a c-approximate r-nearest neighbor search algorithm for CUDA using Locality Sensitive Hash with Nearest Neighbor search (LSH-NN). We implement this system in CUDA and test it on real world image SIFT vector data. Our tests show that we are able to achieve significant speedup over the serial version, with good approximations on scalability, while achieving the near-optimal search complexity of LSH-NN.

关键词： Vectors Lattices Decoding Complexity theory Nearest neighbor searches Instruction sets databases

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On the design and implementation of a simulator for parallel file system research

On the design and implementation of a simulator for parallel...

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IEEE/NASA Goddard Conference on Mass Storage systems and Technologies, (MSST)

作者： Yonggang Liu Renato Figueiredo Yiqi Xu Ming Zhao Department of Electrical and Computer Engineering University of Florida Gainesville FL USA School of Computing and Information Sciences Florida International University Miami FL USA

ISBN: (纸本)9781479902170

Due to the popularity and importance of parallel File systems (PFSs) in modern High Performance Computing (HPC) centers, PFS designs and I/O optimizations are active research topics. However, the research process is often time-consuming and faces cost and complexity challenges in deploying experiments in real HPC systems. This paper describes PFSsim, a trace-driven simulator of distributed storage systems that allows the evaluation of PFS designs, I/O schedulers, network structures, and workloads. PFSsim differentiates itself from related work in that it provides a powerful platform featuring a modular design with high flexibility in the modeling of subsystems including the network, clients, data servers and I/O schedulers. It does so by designing the simulator to capture abstractions found in common PFSs. PFSsim also exposes script-based interfaces for detailed configurations. Experiments and validation against real systems considering sub-modules and the entire simulator show that PFSsim is capable of simulating a representative PFS (PVFS2) and of modeling different I/O scheduler algorithms with good fidelity. In addition, the simulation speed is also shown to be acceptable.

关键词： Servers File systems Throughput Computational modeling Scheduling algorithms distributed databases Data models

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Introducing a Data Sliding Mechanism for Cooperative Caching in Manycore Architectures

Introducing a Data Sliding Mechanism for Cooperative Caching...

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IEEE international symposium on parallel and distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Safae Dahmani Loïc Cudennec Guy Gogniat Lab-STICC Laboratory University of Bretagne Sud Lorient France CEA LIST Embedded Real Time Systems Laboratory Gif-sur-Yvette France

ISBN: (纸本)9781479913725

In future micro-architectures, the increase of the number of cores and wire network complexity is leading to several performance degradation. These platforms are intended to process large amount of data. One of the biggest challenges for systems scalability is actually the memory wall: the memory latency is hardly increasing compared to technology expectations. Recent works explore potential software and hardware solutions mainly based on different caching schemes for addressing off-chip access issues. In this paper, we propose a new cooperative caching method improving the cache miss rate for many core micro-architectures. The work is motivated by some limitations of recent adaptive cooperative caching proposals. Elastic Cooperative caching (ECC), is a dynamic memory partitioning mechanism that allows sharing cache across cooperative nodes according to the application behavior. However, it is mainly limited with cache eviction rate in case of highly stressed neighborhood. Another system, the adaptive Set-Granular Cooperative Caching (ASCC), is based on finer set-based mechanisms for a better adaptability. However, heavy localized cache loads are not efficiently managed. In such a context, we propose a cooperative caching strategy that consists in sliding data through closer neighbors. When a cache receives a storing request of a neighbor's private block, it spills the least recently used private data to a close neighbor. Thus, solicited saturated nodes slide local blocks to their respective neighbors to always provide free cache space. We also propose a new Priority-based Data Replacement policy to decide efficiently which blocks should be spilled, and a new mechanism to choose host destination called Best Neighbor selector. The first analytic performance evaluation shows that the proposed cache management policies reduce by half the average global communication rate. As frequent accesses are focused in the neighboring zones, it efficiently improves on-Chip traffic

关键词： Cooperative caching Radiation detectors Protocols System-on-chip Context Large Hadron Collider distributed databases

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IBIS: interposed big-data I/O scheduler 13

IBIS: interposed big-data I/O scheduler

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proceedings of the 22nd international symposium on High-performance parallel and distributed computing

作者： Yiqi Xu Adrian Suarez Ming Zhao Florida International University Miami FL USA

ISBN: (纸本)9781450319102

Existing big-data systems (e.g., Hadoop/MapReduce) do not expose management of shared storage I/O resources. As such, application's performance may degrade in unpredictable ways under I/O contention, even with fair sharing of computing resources. This paper proposes \emph{IBIS}, a new Interposed Big-data I/O Scheduler, to provide performance differentiation for competing applications' I/Os in a shared MapReduce-type big-data system. IBIS is implemented in Hadoop by interposing HDFS I/Os and use an SFQ-based proportional-sharing algorithm. Experiments show that the IBIS provides strong performance isolation for one application against another highly I/O-intensive application. IBIS also enforces good proportional sharing of the global bandwidth among competing parallel applications, by coordinating distributed IBIS schedulers to deal with the uneven distribution of local services in big-data systems.

关键词： proportional sharing

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