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Quantifying and Reducing Execution Variance in STM via Model Driven Commit optimization 2019

Quantifying and Reducing Execution Variance in STM via Model...

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17th ieee/acm international symposium on code generation and optimization (CGO)

作者： Mururu, Girish Gavrilovska, Ada Pande, Santosh Georgia Inst Technol Sch Comp Sci Atlanta GA 30332 USA

ISBN: (纸本)9781728114361

Simplified parallel programming coupled with an ability to express speculative computation is realized with Software Transactional Memory (STM). Although STMs are gaining popularity because of significant improvements in parallel performance, they exhibit enormous variation in transaction execution with non-repeatable performance behavior which is unacceptable in many application domains, especially in which frame rates and responsiveness should be *** other domains reproducible transactional behavior helps towards system provisioning. Thus, reducing execution variance in STM is an important performance goal that has been mostly overlooked. In this work, we minimize the variance in execution time of threads in STM by reducing non-determinism exhibited due to speculation. We define the state of STM, and we use it to first quantify non-determinism and then generate an automaton that models the execution behavior of threads in STM. We finally use the state automaton to guide the STM to avoid non-predictable transactional behavior thus reducing non-determinism in rollbacks which in turn results in reduction in variance. We observed average reduction of variance in execution time of threads up to 74% in 16 cores and 53% in 8 cores by reducing non-determinism up to 24% in 16 cores and 44% in 8 cores, respectively, on STAMP benchmark suite while experiencing average slowdown of 4.8% in 8 cores and 19.2% in 16 cores. We also reduced the variance in frame rate by maximum of 65% on a version of real world game Quake3 without degradation in timing.

关键词： Software Transactional Memory (STM) Execution Variance Quake3

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IGC: The Open Source Intel Graphics Compiler 2019

IGC: The Open Source Intel Graphics Compiler

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17th ieee/acm international symposium on code generation and optimization (CGO)

作者： Chandrasekhar, Anupama Chen, Gang Chen, Po-Yu Chen, Wei-Yu Gu, Junjie Guo, Peng Kumar, Shruthi Hebbur Prasanna Lueh, Guei-Yuan Mistry, Pankaj Pan, Wei Raoux, Thomas Trifunovic, Konrad Intel Corp Santa Clara CA 95054 USA Intel Corp Gdansk Poland

ISBN: (纸本)9781728114361

With increasing general purpose programming capability, GPUs have become the mainstay for a wide variety of compute intensive tasks from cloud to edge computing. Because of its availability on nearly every desktop and mobile processor that Intel ships, Intel integrated GPU offers a plethora of opportunities for researchers and application developers to make significant real-world impact. In this paper we present the Intel Graphics Compiler (IGC), the LLVM-based production compiler for Intel HD and Iris graphics. IGC supports all major graphics and compute APIs, and its OpenCL compute stack including compute runtime, compiler frontend and backend, and architecture specification is fully open-source, giving a unique opportunity for developers to optimize the entire stack. We highlight several custom optimizations that address the challenges for GPU compilation. Examples include SIMD size selection, divergence analysis, instruction scheduling, addressing mode selection, and redundant copy elimination. These optimizations take advantage of features in the Intel GPU architecture such as a larger register file, indirect register addressing, and multiple memory addressing modes. Experimental results show that our optimizations deliver significant speedup on a number of OpenCL benchmarks;compared to the baseline, we see a geometric mean of 12% speed up across benchmarks with a peak gain of 45%.

关键词： Graphics processing units optimization Registers Graphics Computer architecture Benchmark testing Kernel

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Link-Time optimization for Power Efficiency in a Tagless Instruction Cache

Link-Time Optimization for Power Efficiency in a Tagless Ins...

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9th annual ieee/acm international symposium on code generation and optimization (CGO)

作者： Jones, Timothy M. Bartolini, Sandro Maebe, Jonas Chanet, Dominique Univ Edinburgh Sch Infonnat Edinburgh EH8 9YL Midlothian Scotland Univ Siena Fac Engn Siena Italy Univ Ghent ELIS Dept Ghent Belgium Gateway Architecture Grp Technicolor Edegem Belgium

ISBN: (纸本)9781612843551

The instruction cache is a critical component in any microprocessor. It must have high performance to enable fetching of instructions on every cycle. However, current designs waste a large amount of energy on each access as tags and data banks from all cache ways are consulted in parallel to fetch the correct instructions as quickly as possible. Existing approaches to reduce this overhead remove unnecessary accesses to the data banks or to the ways that are not likely to hit. However, tag banks still need to be checked. This paper considers a new hybrid hardware and linker-assisted approach to tagless instruction caching. Our novel cache architecture, supported by the compilation toolchain, removes the need for tag checks entirely for the majority of cache accesses. The linker places frequency-executed instructions in specific program regions that are then mapped into the cache without the need for tag checks. This requires minor hardware modifications, no ISA changes and works across cache configurations. Our approach keeps the software and hardware independent, resulting in both backward and forward compatibility. Evaluation on a superscalar processor with and without SMT support shows power savings of 66% within the instruction cache with no loss of performance. This translates to a 49% saving when considering the combined power of the instruction cache and translation lookaside buffer, which is involved in managing our tagless scheme.

关键词： instruction cache Cache memory Data banks TAGGING dynamic efficiency energy capacity instruction translation lookaside buffer superscalar processor combined dynamic fetch Connector Device Component

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Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks 35

Vector vs. superscalar and VLIW architectures for embedded m...

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35th annual ieee/acm international symposium on Microarchitecture

作者： Kozyrakis, C Patterson, D Stanford Univ Dept Elect Engn Stanford CA 94305 USA

ISBN: (纸本)0769518591

Multimedia processing on embedded devices requires an architecture that leads to high performance, low power consumption, reduced design complexity, and small code size. In this paper, we use EEMBC, an industrial benchmark suite, to compare the VIRAM vector architecture to super-scalar and VLIW processors for embedded multimedia applications. The comparison covers the VIRAM instruction set, vectorizing compiler and the prototype chip that integrates a vector processor with DRAM main memory. We demonstrate that executable code for VIRAM is up to 10 times smaller than VLIW code and comparable to x86 CISC code. The simple, cache-less VIRAM chip is 2 times faster than a 4-way superscalar RISC processor that uses a 5 times faster clock frequency and consumes 10 times more power VIRAM is also 10 times faster than cache-based VLIW processors. Even after manual optimization of the VLIW code and insertion of SIMD and DSP instructions, the single-issue VIRAM processor is 60% faster than 5-way to 8-way VLIW designs.

关键词： Clocks Design optimization Digital signal processing chips Energy consumption Frequency Manuals Prototypes Reduced instruction set computing Vector processors VLIW

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CompilerGym: Robust, Performant Compiler optimization Environments for AI Research 22

CompilerGym: Robust, Performant Compiler Optimization Enviro...

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20th ieee/acm international symposium on code generation and optimization (CGO)

作者： Cummins, Chris Wasti, Bram Guo, Jiadong Cui, Brandon Ansel, Jason Gomez, Sahir Jain, Somya Liu, Jia Teytaud, Olivier Steiner, Benoit Tian, Yuandong Leather, Hugh Meta Menlo Pk CA 94025 USA

ISBN: (纸本)9781665405843

Interest in applying Artificial Intelligence (AI) techniques to compiler optimizations is increasing rapidly, but compiler research has a high entry barrier. Unlike in other domains, compiler and AI researchers do not have access to the datasets and frameworks that enable fast iteration and development of ideas, and getting started requires a significant engineering investment. What is needed is an easy, reusable experimental infrastructure for real world compiler optimization tasks that can serve as a common benchmark for comparing techniques, and as a platform to accelerate progress in the field. We introduce CompilerGym, a set of environments for real world compiler optimization tasks, and a toolkit for exposing new optimization tasks to compiler researchers. CompilerGym enables anyone to experiment on production compiler optimization problems through an easy-to-use package, regardless of their experience with compilers. We build upon the popular OpenAI Gym interface enabling researchers to interact with compilers using Python and a familiar API. We describe the CompilerGym architecture and implementation, characterize the optimization spaces and computational efficiencies of three included compiler environments, and provide extensive empirical evaluations. Compared to prior works, CompilerGym offers larger datasets and optimization spaces, is 27x more computationally efficient, is fault-tolerant, and capable of detecting reproducibility bugs in the underlying compilers. In making it easy for anyone to experiment with compilers - irrespective of their background - we aim to accelerate progress in the AI and compiler research domains.

关键词： Fault tolerance Fault tolerant systems Computer bugs Production Reproducibility of results Computational efficiency Artificial intelligence

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Optimal versus heuristic global code scheduling

Optimal versus heuristic global code scheduling

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40th annual ieee/AMC international symposium on Microarchitecture

作者： Winkel, Sebastian Intel Corp Intel Compiler Lab 3600 Juliette Lane Santa Clara CA 95054 USA

ISBN: (纸本)9780769530475

We present a global instruction scheduler based on integer linear programming (ILP) that was implemented experimentally in the Intel Itanium(R) product compiler It features virtually the full scale of known EPIC scheduling optimizations, more than its heuristic counterpart in the compiler, GCS, and in contrast to the latter it computes optimal solutions in the form of schedules with minimal length. Due to our highly efficient ILP model it can solve problem instances with 500-750 instructions, and in combination with region scheduling we are able to schedule routines of arbitrary size. In experiments on five SPEC(R) CPU2006 integer benchmarks, ILP-scheduled code exhibits a 32% schedule length advantage and a 10% runtime speedup over GCS-scheduled code, at the highest compiler optimization levels typically used for SPEC submissions. We further study the impact of different code motion classes, region sizes, and target microarchitectures, gaining insights into the nature of the global instruction scheduling problem.

关键词： Scheduling

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Tensor Algebra Compilation with Workspaces 2019

Tensor Algebra Compilation with Workspaces

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17th ieee/acm international symposium on code generation and optimization (CGO)

作者： Kjolstad, Fredrik Ahrens, Willow Kamil, Shoaib Amarasinghe, Saman MIT Cambridge MA 02139 USA Adobe Res San Jose CA USA

ISBN: (纸本)9781728114361

This paper shows how to extend sparse tensor algebra compilers to introduce temporary tensors called workspaces to avoid inefficient sparse data structures accesses. We develop an intermediate representation (IR) for tensor operations called concrete index notation that specifies when sub-computations occur and where they are stored. We then describe the workspace transformation in this IR, how to programmatically invoke it, and how the IR is compiled to sparse code. Finally, we show how the transformation can be used to optimize sparse tensor kernels, including sparse matrix multiplication, sparse tensor addition, and the matricized tensor times Khatri-Rao product (MTTKRP). Our results show that the workspace transformation brings the performance of these kernels on par with hand-optimized implementations. For example, we improve the performance of MTTKRP with dense output by up to 35%, and enable generating sparse matrix multiplication and MTTKRP with sparse output, neither of which were supported by prior tensor algebra compilers.

关键词： sparse tensor algebra concrete index notation code optimization temporaries workspaces

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Experiences Building an MLIR-Based SYCL Compiler 24

Experiences Building an MLIR-Based SYCL Compiler

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22nd ieee/acm international symposium on code generation and optimization (CGO)

作者： Tiotto, Ettore Perez, Victor Tsang, Whitney Sommer, Lukas Oppermann, Julian Lomueller, Victor Goli, Mehdi Brodman, James Intel Corp Toronto ON Canada Codeplay Software Edinburgh Midlothian Scotland Intel Corp Boston MA USA

ISBN: (纸本)9798350395099

Similar to other programming models, compilers for SYCL, the open programming model for heterogeneous computing based on C++, would benefit from access to higher-level intermediate representations. The loss of high-level structure and semantics caused by premature lowering to low-level intermediate representations and the inability to reason about host and device code simultaneously present major challenges for SYCL compilers. The MLIR compiler framework, through its dialect mechanism, allows to model domain-specific, high-level intermediate representations and provides the necessary facilities to address these challenges. This work therefore describes practical experience with the design and implementation of an MLIR-based SYCL compiler. By modeling key elements of the SYCL programming model in host and device code in the MLIR dialect framework, the presented approach enables the implementation of powerful device code optimizations as well as analyses across host and device code. Compared to two LLVM-based SYCL implementations, this yields speedups of up to 4.3x on a collection of SYCL benchmark applications. Finally, this work also discusses challenges encountered in the design and implementation and how these could be addressed in the future.

关键词： SYCL MLIR compiler optimization heterogeneous programming

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Automatic Array Inlining in Java Virtual Machines 08

Automatic Array Inlining in Java Virtual Machines

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6th international symposium on code generation and optimization

作者： Wimmer, Christian Moessenboeck, Hanspeter Johannes Kepler Univ Linz Inst Syst Software Christian Doppler Lab Automated Software Engn A-4040 Linz Austria

ISBN: (纸本)9781595939784

Array inlining expands the concepts of object inlining to arrays. Groups of objects and arrays that reference each other are placed consecutively in memory so that their relative offsets are fixed, i.e. they are colocated. This allows memory loads to be replaced by address arithmetic, which reduces the costs of field and array accesses. We implemented this optimization for Sun Microsystems' Java HotSpot (TM) VM. The optimization is performed automatically and requires no actions on the part of the programmer. Arrays are frequently used for the implementation of dynamic data structures. Therefore, the length of arrays often varies, and fields referencing such arrays have to be changed whenever the array is reallocated. We present an efficient code pattern that detects these changes and allows the optimized access of such array fields. It is integrated into the array bounds check. We also claim that inlining array element objects into an array is not possible without a global data flow analysis. The evaluation shows that our dynamic approach can optimize frequently accessed fields with a reasonable low compilation and analysis overhead. The peak performance of SPECjvm98 is improved by 10% on average, with a maximum of 25%.

关键词： Java object inlining array inlining just-in-time compilation garbage collection optimization performance

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Tackling the Matrix Multiplication Micro-kernel generation with EXO 24

Tackling the Matrix Multiplication Micro-kernel Generation w...

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22nd ieee/acm international symposium on code generation and optimization (CGO)

作者： Castello, Adrian Bellavita, Julian Dinh, Grace Ikarashi, Yuka Martinez, Hector Univ Politecn Valencia Valencia Spain Cornell Univ Ithaca NY USA Univ Calif Berkeley Berkeley CA USA MIT CSAIL Cambridge MA USA Univ Cordoba Cordoba Spain

ISBN: (纸本)9798350395099

The optimization of the matrix multiplication (or GEMM) has been a need during the last decades. This operation is considered the flagship of current linear algebra libraries such as BLIS, OpenBLAS, or Intel OneAPI because of its widespread use in a large variety of scientific applications. The GEMM is usually implemented following the GotoBLAS philosophy, which tiles the GEMM operands and uses a series of nested loops for performance improvement. These approaches extract the maximum computational power of the architectures through small pieces of hardware-oriented, high-performance code called micro-kernel. However, this approach forces developers to generate, with a nonnegligible effort, a dedicated micro-kernel for each new hardware. In this work, we present a step-by-step procedure for generating micro-kernels with the EXO compiler that perform close to (or even better than) manually developed microkernels written with intrinsic functions or assembly language. Our solution also improves the portability of the generated code, since a hardware target is fully specified by a concise library-based description of its instructions.

关键词： code generation high performance Exo linear algebra micro-kernels

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