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共 546 条记录，以下是101-110 订阅

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Tackling the Matrix Multiplication Micro-kernel generation with EXO 24

Tackling the Matrix Multiplication Micro-kernel Generation w...

引用

22nd ieee/acm international symposium on code generation and optimization (CGO)

作者： Castello, Adrian Bellavita, Julian Dinh, Grace Ikarashi, Yuka Martinez, Hector Univ Politecn Valencia Valencia Spain Cornell Univ Ithaca NY USA Univ Calif Berkeley Berkeley CA USA MIT CSAIL Cambridge MA USA Univ Cordoba Cordoba Spain

ISBN: (纸本)9798350395099

The optimization of the matrix multiplication (or GEMM) has been a need during the last decades. This operation is considered the flagship of current linear algebra libraries such as BLIS, OpenBLAS, or Intel OneAPI because of its widespread use in a large variety of scientific applications. The GEMM is usually implemented following the GotoBLAS philosophy, which tiles the GEMM operands and uses a series of nested loops for performance improvement. These approaches extract the maximum computational power of the architectures through small pieces of hardware-oriented, high-performance code called micro-kernel. However, this approach forces developers to generate, with a nonnegligible effort, a dedicated micro-kernel for each new hardware. In this work, we present a step-by-step procedure for generating micro-kernels with the EXO compiler that perform close to (or even better than) manually developed microkernels written with intrinsic functions or assembly language. Our solution also improves the portability of the generated code, since a hardware target is fully specified by a concise library-based description of its instructions.

关键词： code generation high performance Exo linear algebra micro-kernels

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Checking Correctness of code Generator Architecture Specifications

Checking Correctness of Code Generator Architecture Specific...

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proceedings of the ieee/acm international symposium on code generation and optimization (CGO)

作者： Hasabnis, Niranjan Qiao, Rui Sekar, R. SUNY Stony Brook Stony Brook NY 11794 USA

ISBN: (纸本)9781479981618

Modern instruction sets are complex, and extensions are proposed to them frequently. This makes the task of modelling architecture specifications used by the code generators of modern compilers complex and error-prone. Given the important role played by the compilers, it is necessary that they are tested thoroughly, so that most of the bugs are detected early on. Unfortunately, modern compilers such as GCC do not target testing of individual components of a compiler, but instead perform end-to-end testing. In this paper, we target the problem of checking correctness of the architecture specifications used by code generators of modern compilers. Our solution leverages the architecture of modern compilers where a language-specific front-end compiles source-code into an intermediate representation (IR), which is then translated by the compiler's code generator into assembly code. Hence our approach is to test code generators by testing the equivalence of IR snippets and the corresponding assembly code generated. For this purpose, we have developed an efficient, architecture-neutral test case generation strategy. Using our prototype implementation, we performed correctness checking of 140 assembly instructions (80 general-purpose and 60 SSE out of around 600 x86 instructions) of GCC's x86 code generator, and found semantic differences in 39 of them, at least one of which has already been fixed by the GCC community in response to our report. We believe that our approach can be invaluable when developing support for a new architecture, as well as during frequent updates made to existing architectures such as x86 for the purpose of supporting new instructions.

关键词： Specifications

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COLE: Compiler optimization Level Exploration 08

COLE: Compiler Optimization Level Exploration

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6th international symposium on code generation and optimization

作者： Hoste, Kenneth Eeckhout, Lieven Univ Ghent ELIS Dept B-9000 Ghent Belgium

ISBN: (纸本)9781595939784

Modern compilers implement a large number of optimizations which all interact in complex ways, and which all have a different impact oil code quality, compilation time, code size, energy consumption, etc. For this reason, compilers typically provide a limited number of standard optimization levels, such as -01, -02, -03 and -0s, that combine various optimizations providing a number of trade-offs between multiple objective functions (such as code quality, compilation time and code size). The construction of these optimization levels, i.e., choosing which optimizations to activate at each level, is a manual process typically done using high-level heuristics based on the compiler developer's experience. This paper proposes COLE, Compiler optimization Level Exploration, a framework or automatically finding Pareto optimal optimization levels through multi-objective evolutionary searching. Our experimental results using GCC and the SPEC CPU benchmarks show that the automatic construction of optimization levels is feasible in practice, and in addition, yields better optimization levels than GCC's manually derived (-0s, -01, -02 and -03) optimization levels, as well as the optimization levels obtained through random sampling. We also demonstrate that COLE can be used to gain insight into the effectiveness of compiler optimizations as well as to better understand a benchmark's sensitivity to compiler optimizations.

关键词： compiler optimization multi-objective search

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Accelerating Deep Neural Networks on Mobile Multicore NPUs 2023

Accelerating Deep Neural Networks on Mobile Multicore NPUs

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21st acm/ieee international symposium on code generation and optimization (CGO)

作者： Jung, Hanwoong Ji, Hexiang Pushchin, Alexey Ostapenko, Maxim Niu, Wenlong Palachev, Ilya Qu, Yutian Fedin, Pavel Gribov, Yuri Nam, Heewoo Lim, Dongguen Kim, Hyunjun Song, Joonho Lee, Seungwon Han, Hwansoo Samsung Adv Inst Technol Suwon South Korea Samsung R&D Inst Xian Peoples R China

ISBN: (纸本)9798400701016

Neural processing units (NPUs) have become indispensable parts of mobile SoCs. Furthermore, integrating multiple NPU cores into a single chip becomes a promising solution for ever-increasing computing power demands in mobile devices. This paper addresses techniques to maximize the utilization of NPU cores and reduce the latency of on-device inference. Mobile NPUs typically have a small amount of local memory (or scratch pad memory, SPM) that provides space only enough for input/output tensors and weights of one layer operation in deep neural networks (DNNs). Even in multicore NPUs, such local memories are distributed across the cores. In such systems, executing network layer operations in parallel is the primary vehicle to achieve performance. By partitioning a layer of DNNs into multiple sub-layers, we can execute them in parallel on multicore NPUs. Within a core, we can also employ pipelined execution to reduce the execution time of a sub-layer. In this execution model, synchronizing parallel execution and loading/storing intermediate tensors in global memory are the main bottlenecks. To alleviate these problems, we propose novel optimization techniques which carefully consider partitioning direction, execution order, synchronization, and global memory access. Using six popular convolutional neural networks (CNNs), we evaluate our optimization techniques in a flagship mobile SoC with three cores. Compared to the highest-performing partitioning approach, our techniques improve performance by 23%, achieving a speedup of 2.1x over single-core systems.

关键词： Neural networks Multicore Neural processing unit Layer partitioning Scheduling optimization

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Enhancing Performance through Control-Flow Unmerging and Loop Unrolling on GPUs 24

Enhancing Performance through Control-Flow Unmerging and Loo...

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22nd ieee/acm international symposium on code generation and optimization (CGO)

作者： Murtovi, Alnis Georgakoudis, Giorgis Parasyris, Konstantinos Liao, Chunhua Laguna, Ignacio Steffen, Bernhard TU Dortmund Univ Dortmund Germany Lawrence Livermore Natl Lab Lawrence KS USA

ISBN: (纸本)9798350395099

Compilers use a wide range of advanced optimizations to improve the quality of the machine code they generate. In most cases, compiler optimizations rely on precise analyses to be able to perform the optimizations. However, whenever a control-flow merge is performed information is lost as it is not possible to precisely reason about the program anymore. One existing solution to this issue is code duplication, which involves duplicating instructions from merge blocks to their predecessors. This paper introduces a novel and more aggressive approach to code duplication, grounded in loop unrolling and control-flow unmerging that enables subsequent optimizations that cannot be enabled by applying only one of these transformations. This paper introduces a novel and more aggressive approach to code duplication, grounded in loop unrolling and control-flow unmerging that enables subsequent optimizations that cannot be enabled by applying only one of these transformations. We implemented our approach inside LLVM, and evaluated its performance on a collection of GPU benchmarks in CUDA. Our results demonstrate that, even when faced with branch divergence, which complicates code duplication across multiple branches and increases the associated cost, our optimization technique achieves performance improvements of up to 81%.

关键词： compiler code duplication LLVM GPU

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AXI4MLIR: User-Driven Automatic Host code generation for Custom AXI-Based Accelerators 24

AXI4MLIR: User-Driven Automatic Host Code Generation for Cus...

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22nd ieee/acm international symposium on code generation and optimization (CGO)

作者： Agostini, Nicolas Bohm Haris, Jude Gibson, Perry Jayaweera, Malith Rubin, Norm Tumeo, Antonino Abellan, Jose L. Cano, Jose Kaeli, David Northeastern Univ Boston MA 02115 USA Univ Glasgow Glasgow Lanark Scotland Univ Murcia Murcia Spain Pacific Northwest Natl Lab Richland WA USA

ISBN: (纸本)9798350395099

This paper addresses the need for automatic and efficient generation of host driver code for arbitrary custom AXI-based accelerators targeting linear algebra algorithms, an important workload in various applications, including machine learning and scientific computing. While existing tools have focused on automating accelerator prototyping, little attention has been paid to the host-accelerator interaction. This paper introduces AXI4MLIR, an extension of the MLIR compiler framework designed to facilitate the automated generation of host-accelerator driver code. With new MLIR attributes and transformations, AXI4MLIR empowers users to specify accelerator features (including their instructions) and communication patterns and exploit the host memory hierarchy. We demonstrate AXI4MLIR's versatility across different types of accelerators and problems, showcasing significant CPU cache reference reductions (up to 56%) and up to a 1.65x speedup compared to manually optimized driver code implementations. AXI4MLIR implementation is opensource and available at: https://***/AXI4MLIR/axi4mlir.

关键词： MLIR AXI Compilers code generation

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SGXELIDE: Enabling Enclave code Secrecy via Self-Modification 2018

SGXELIDE: Enabling Enclave Code Secrecy via Self-Modificatio...

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16th international symposium on code generation and optimization (CGO)

作者： Bauman, Erick Wang, Huibo Zhang, Mingwei Lin, Zhiqiang Univ Texas Dallas Richardson TX 75083 USA Intel Labs Hillsboro OR USA

ISBN: (纸本)9781450356176

Intel SGX provides a secure enclave in which code and data are hidden from the outside world, including privileged code such as the OS or hypervisor. However, by default, enclave code prior to initialization can be disassembled and therefore no secrets can be embedded in the binary. This is a problem for developers wishing to protect code secrets. This paper introduces SGXELIDE, a nearly-transparent framework that enables enclave code confidentiality. The key idea is to treat program code as data and dynamically restore secrets after an enclave is initialized. SGXELIDE can be integrated into any enclave, providing a mechanism to securely decrypt or deliver the secret code with the assistance of a developer-controlled trusted remote party. We have implemented SGXELIDE atop a recently released version of the Linux SGX SDK, and our evaluation with a number of programs shows that SGXELIDE can be used to protect the code secrecy of practical applications with no overhead after enclave initialization.

关键词： SGX self-modifying code code obfuscation

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AskIt: Unified Programming Interface for Programming with Large Language Models 24

AskIt: Unified Programming Interface for Programming with La...

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22nd ieee/acm international symposium on code generation and optimization (CGO)

作者： Okuda, Katsumi Amarasinghe, Saman MIT CSAIL Cambridge MA 02139 USA Mitsubishi Electr Corp Amagasaki Hyogo Japan

ISBN: (纸本)9798350395099

Large Language Models (LLMs) exhibit a unique phenomenon known as emergent abilities, demonstrating adeptness across numerous tasks, from text summarization to code generation. While these abilities open up novel avenues in software design and crafting, their incorporation presents substantial challenges. Developers face decisions regarding the use of LLMs for directly performing tasks within applications as well as for generating and executing code to accomplish these tasks. Moreover, effective prompt design becomes a critical concern, given the necessity of extracting data from natural language outputs. To address these complexities, this paper introduces AskIt, a domain-specific language (DSL) specifically designed for LLMs. AskIt simplifies LLM integration by providing a unified interface that not only allows for direct task execution using LLMs but also supports the entire cycle of code generation and execution. This dual capability is achieved through (1) typeguided output control, (2) template-based function definitions, and (3) prompt generation for both usage modes. Our evaluations underscore AskIt's effectiveness. Across 50 tasks, AskIt generated concise prompts, achieving a 16.14 % reduction in prompt length compared to benchmarks. Additionally, by enabling a seamless transition between using LLMs directly in applications and for generating code, AskIt achieved significant efficiency improvements, as observed in our GSM8K benchmark experiments. The implementations of AskIt in TypeScript and Python are available at https://***/katsumiok/ts- askit and https://***/katsumiok/pyaskit, respectively.

关键词： domain specific language code generation large language model software engineering artificial intelligence

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Fast Track: A Software System for Speculative Program optimization 09

Fast Track: A Software System for Speculative Program Optimi...

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7th international symposium on code generation and optimization

作者： Kelsey, Kirk Bai, Tongxin Ding, Chen Hang, Chengliang Univ Rochester Dept Comp Sci Rochester NY 14627 USA Microsoft Corp Redmond WA 98052 USA

ISBN: (纸本)9780769535760

Fast track is a software speculation system that enables unsafe optimization of sequential code. It speculatively runs optimized code to improve performance and then checks the correctness of the speculative code by running the original program on multiple processors. We present the interface design and system implementation for Fast Track. It lets a programmer or a profiling tool mark fast-track code regions and uses a run-time system to manage the parallel execution of the speculative process and its checking processes and ensures the correct display of program outputs. The core of the run-time system is a novel concurrent algorithm that balances exploitable parallelism and available processors when the fast track is too slow or too fast. The programming interface closely affects the run-time support. Our system permits both explicit and implicit end markers for speculatively optimized code regions as well as extensions that allow the use of multiple tracks and user defined correctness checking. We discuss the possible uses of speculative optimization and demonstrate the effectiveness of our prototype system by examples of unsafe semantic optimization and a general system for fast memory-safety checking, which is able to reduce the checking time by factors between 2 and 7 for large sequential code on a 8-CPU system.

关键词： Software systems Tracking loops Programming profession Runtime Hardware Kirk field collapse effect Computer science Displays Parallel processing Prototypes

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proceedings of the 14th international symposium on code generation and optimization, CGO 2016

Proceedings of the 14th International Symposium on Code Gene...

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14th annual ieee/acm international symposium on code generation and optimization, CGO 2016

ISBN: (纸本)9781450337786

The proceedings contain 25 papers. The topics discussed include: Cheetah: detecting false sharing efficiently and effectively;AutoFDO: automatic feedback-directed optimization for warehouse-scale applications;portable performance on asymmetric multicore processors;StructSlim: a lightweight profiler to guide structure splitting;exploiting recent SIMD architectural advances for irregular applications;exploiting mixed SIMD parallelism by reducing data reorganization overhead;a black-box approach to energy-aware scheduling on integrated CPU-GPU systems;portable and transparent software managed scheduling on accelerators for fair resource sharing;communication-aware mapping of stream graphs for multi-GPU Platforms;GPUCC: an open-source GPGPU compiler;a basic linear algebra compiler for structured matrices;opening polyhedral compiler's black box;trace-based affine reconstruction of codes;and inference of peak density of indirect branches to detect ROP attacks.

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