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检索条件"任意字段=Proceedings of Annual IEEE/ACM International Symposium on Code Generation and Optimization"

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international symposium on code generation and optimization, CGO 2004

International symposium on code generation and optimization,...

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international symposium on code generation and optimization, CGO 2004

ISBN: (纸本)0769521029

The proceedings contains 25 papers from the international symposium on code generation and optimization, CGO 2004. Topics discussed include: compiler optimization of memory-resident value communication between speculative threads;exploring code cache eviction granularities in dynamic optimization systems;specialized dynamic optimizations for high-performance energy-efficient microarchitecture;using dynamic binary translation to fuse dependent instructions;the accuracy of initial prediction in two-phase dynamic binary translators;and a compiler scheme for reusing intermediate computation results.

关键词： Microprocessor chips

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Revealing Compiler Heuristics through Automated Discovery and optimization 24

Revealing Compiler Heuristics through Automated Discovery an...

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22nd ieee/acm international symposium on code generation and optimization (CGO)

作者： Seeker, Volker Cummins, Chris Cole, Murray Franke, Bjorn Hazelwood, Kim Leather, Hugh Meta AI Menlo Pk CA 94025 USA Univ Edinburgh Edinburgh Midlothian Scotland

ISBN: (纸本)9798350395099

Tuning compiler heuristics and parameters is well known to improve optimization outcomes dramatically. Prior works have tuned command line flags and a few expert identified heuristics. However, there are an unknown number of heuristics buried, unmarked and unexposed inside the compiler as a consequence of decades of development without auto-tuning being foremost in the minds of developers. Many may not even have been considered heuristics by the developers who wrote them. The result is that auto-tuning search and machine learning can optimize only a tiny fraction of what could be possible if all heuristics were available to tune. Manually discovering all of these heuristics hidden among millions of lines of code and exposing them to auto-tuning tools is a Herculean task that is simply not practical. What is needed is a method of automatically finding these heuristics to extract every last drop of potential optimization. In this work, we propose Heureka, a framework that automatically identifies potential heuristics in the compiler that are highly profitable optimization targets and then automatically finds available tuning parameters for those heuristics with minimal human involvement. Our work is based on the following key insight: When modifying the output of a heuristic within an acceptable value range, the calling code using that output will still function correctly and produce semantically correct results. Building on that, we automatically manipulate the output of potential heuristic code in the compiler and decide using a Differential Testing approach if we found a heuristic or not. During output manipulation, we also explore acceptable value ranges of the targeted code. Heuristics identified in this way can then be tuned to optimize an objective function. We used Heureka to search for heuristics among eight thousand functions from the LLVM optimization passes, which is about 2% of all available functions. We then use identified heuristics to tune the compila

关键词： Terms-Search Methodologies Compiler optimization Differential Testing

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CollectionSwitch: A Framework for Efficient and Dynamic Collection Selection 2018

CollectionSwitch: A Framework for Efficient and Dynamic Coll...

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16th international symposium on code generation and optimization (CGO)

作者： Costa, Diego Andrzejak, Artur Heidelberg Univ Inst Comp Sci Heidelberg Germany

ISBN: (纸本)9781450356176

Selecting collection data structures for a given application is a crucial aspect of the software development. Inefficient usage of collections has been credited as a major cause of performance bloat in applications written in Java, C++ and C#. Furthermore, a single implementation might not be optimal throughout the entire program execution. This demands an adaptive solution that adjusts at runtime the collection implementations to varying workloads. We present CollectionSwitch, an application-level framework for efficient collection adaptation. It selects at runtime collection implementations in order to optimize the execution and memory performance of an application. Unlike previous works, we use workload data on the level of collection allocation sites to guide the optimization process. Our framework identifies allocation sites which instantiate suboptimal collection variants, and selects optimized variants for future instantiations. As a further contribution we propose adaptive collection implementations which switch their underlying data structures according to the size of the collection. We implement this framework in Java, and demonstrate the improvements in terms of time and memory behavior across a range of benchmarks. To our knowledge, it is the first approach which is capable of runtime performance optimization of Java collections with very low overhead.

关键词： data structure performance optimization adaptive algorithms

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A Compiler Framework for Optimizing Dynamic Parallelism on GPUs 22

A Compiler Framework for Optimizing Dynamic Parallelism on G...

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20th ieee/acm international symposium on code generation and optimization (CGO)

作者： Olabi, Mhd Ghaith Luna, Juan Gomez Mutlu, Onur Hwu, Wen-mei El Hajj, Izzat Amer Univ Beirut Beirut Lebanon Swiss Fed Inst Technol Zurich Switzerland NVIDIA Santa Clara CA USA Univ Illinois Urbana IL USA

ISBN: (纸本)9781665405843

Dynamic parallelism on GPUs allows GPU threads to dynamically launch other GPU threads. It is useful in applications with nested parallelism, particularly where the amount of nested parallelism is irregular and cannot be predicted beforehand. However, prior works have shown that dynamic parallelism may impose a high performance penalty when a large number of small grids are launched. The large number of launches results in high launch latency due to congestion, and the small grid sizes result in hardware underutilization. To address this issue, we propose a compiler framework for optimizing the use of dynamic parallelism in applications with nested parallelism. The framework features three key optimizations: thresholding, coarsening, and aggregation. Thresholding involves launching a grid dynamically only if the number of child threads exceeds some threshold, and serializing the child threads in the parent thread otherwise. Coarsening involves executing the work of multiple thread blocks by a single coarsened block to amortize the common work across them. Aggregation involves combining multiple child grids into a single aggregated grid. Thresholding is sometimes applied manually by programmers in the context of dynamic parallelism. We automate it in the compiler and discuss the challenges associated with doing so. Coarsening is sometimes applied as an optimization in other contexts. We propose to apply coarsening in the context of dynamic parallelism and automate it in the compiler as well. Aggregation has been automated in the compiler by prior work. We enhance aggregation by proposing a new aggregation technique that uses multi-block granularity. We also integrate these three optimizations into an open-source compiler framework to simplify the process of optimizing dynamic parallelism code. Our evaluation shows that our compiler framework improves the performance of applications with nested parallelism by a geometric mean of 43.0 x over applications that use dynam

关键词： Context codes Graphics processing units Parallel processing Hardware optimization Open source software

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Revisiting Out-of-SSA Translation for Correctness, code Quality, and Efficiency 09

Revisiting Out-of-SSA Translation for Correctness, Code Qual...

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7th international symposium on code generation and optimization

作者： Boissinot, Benoit Darte, Alain Rastello, Fabrice de Dinechin, Benoit Dupont Guillon, Christophe UCB Lyon Inria ENS Lyon CNRS UMR 5668LIPCompsys Team Lyon France STMicroelect CEC Comp Grp Grenoble France

ISBN: (纸本)9780769535760

Static single assignment (SSA) form is an intermediate program representation in which many code optimizations can be performed with fast and easy-to-implement algorithms. However, some of these optimizations create situations where the SSA variables arising from the same original variable now have overlapping live ranges. This complicates the translation out of SSA code into standard code. There are three issues to consider: correctness, code quality (elimination of copies), and algorithm efficiency (speed and memory footprint). Briggs et al. proposed patches to correct the initial approach of Cytron et al. A cleaner and more general approach was proposed by Sreedhar et al., along with techniques to reduce the number of generated copies. We propose a new approach based on coalescing and a precise view of interferences, in which correctness and optimizations are separated. Our approach is provably correct and simpler to implement, with no patches or particular cases as in previous solutions, while reducing the number of generated copies. Also, experiments with SPEC CINT2000 show that it is 2x faster and 10x less memory-consuming than the Method III of Sreedhar et al., which makes it suitable for just-in-time compilation.

关键词： Compilers SSA form JIT-compilation

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Jumbo: Run-time code generation for Java and its applications

Jumbo: Run-time code generation for Java and its application...

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international symposium on code generation and optimization

作者： Kamin, S Clausen, L Jarvis, A Univ Illinois Dept Comp Sci Urbana IL 61801 USA

ISBN: (纸本)076951913X

Run-time code generation is a well-known technique for improving the efficiency of programs by exploiting dynamic information. Unfortunately, the difficulty of constructing run-time code-generators has hampered their widespread use. We describe Jumbo, a tool for easily creating run-time code generators for Java. Jumbo is a compiler for a two-level version of Java, where programs can contain quoted code fragments. The Jumbo AN allows the code fragments to be combined at run-time and then executed We illustrate Jumbo with several examples that show significant speed-ups over similar code written in plain Java, and argue further that Jumbo is a generalized software component system.

关键词： run-time code generation Java

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JITSPMM: Just-in-Time Instruction generation for Accelerated Sparse Matrix-Matrix Multiplication 24

JITSPMM: Just-in-Time Instruction Generation for Accelerated...

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22nd ieee/acm international symposium on code generation and optimization (CGO)

作者： Fu, Qiang Rolinger, Thomas B. Huang, H. Howie Adv Micro Devices Inc Austin TX 95054 USA NVIDIA Austin TX USA George Washington Univ Washington DC USA Lab Phys Sci Austin TX USA

ISBN: (纸本)9798350395099

Achieving high performance for Sparse MatrixMatrix Multiplication (SpMM) has received increasing research attention, especially on multi-core CPUs, due to the large input data size in applications such as graph neural networks (GNNs). Most existing solutions for SpMM computation follow the aheadof-time (AOT) compilation approach, which compiles a program entirely before it is executed. AOT compilation for SpMM faces three key limitations: unnecessary memory access, additional branch overhead, and redundant instructions. These limitations stem from the fact that crucial information pertaining to SpMM is not known until runtime. In this paper, we propose JITSPMM, a just-in-time (JIT) assembly code generation framework to accelerated SpMM computation on multi-core CPUs with SIMD extensions. First, JITSPMM integrates the JIT assembly code generation technique into three widely-used workload division methods for SpMM to achieve balanced workload distribution among CPU threads. Next, with the availability of runtime information, JITSPMM employs a novel technique, coarse-grain column merging, to maximize instruction-level parallelism by unrolling the performance-critical loop. Furthermore, JITSPMM intelligently allocates registers to cache frequently accessed data to minimizing memory accesses, and employs selected SIMD instructions to enhance arithmetic throughput. We conduct a performance evaluation of JITSPMM and compare it two AOT baselines. The first involves existing SpMM implementations compiled using the Intel icc compiler with auto-vectorization. The second utilizes the highly-optimized SpMM routine provided by Intel MKL. Our results show that JITSPMM provides an average improvement of 3.8x and 1.4x, respectively.

关键词： SpMM Just-in-Time Instruction generation Performance Profiling Performance optimization

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Synthesizing Benchmarks for Predictive Modeling

Synthesizing Benchmarks for Predictive Modeling

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ieee/acm international symposium on code generation and optimization (CGO)

作者： Cummins, Chris Petoumenos, Pavlos Wang, Zheng Leather, Hugh Univ Edinburgh Edinburgh Midlothian Scotland Univ Lancaster Lancaster England

ISBN: (纸本)9781509049318

Predictive modeling using machine learning is an effective method for building compiler heuristics, but there is a shortage of benchmarks. Typical machine learning experiments outside of the compilation field train over thousands or millions of examples. In machine learning for compilers, however, there are typically only a few dozen common benchmarks available. This limits the quality of learned models, as they have very sparse training data for what are often high-dimensional feature spaces. What is needed is a way to generate an unbounded number of training programs that finely cover the feature space. At the same time the generated programs must be similar to the types of programs that human developers actually write, otherwise the learning will target the wrong parts of the feature space. We mine open source repositories for program fragments and apply deep learning techniques to automatically construct models for how humans write programs. We sample these models to generate an unbounded number of runnable training programs. The quality of the programs is such that even human developers struggle to distinguish our generated programs from hand-written code. We use our generator for OpenCL programs, CLgen, to automatically synthesize thousands of programs and show that learning over these improves the performance of a state of the art predictive model by 1.27x. In addition, the fine covering of the feature space automatically exposes weaknesses in the feature design which are invisible with the sparse training examples from existing benchmark suites. Correcting these weaknesses further increases performance by 4.30x.

关键词： Synthetic program generation OpenCL Benchmarking Deep Learning GPUs

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An Evaluation of Misaligned Data Access Handling Mechanisms in Dynamic Binary Translation Systems 09

An Evaluation of Misaligned Data Access Handling Mechanisms ...

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7th international symposium on code generation and optimization

作者： Li, Jianjun Wu, Chenggang Hsu, Wei-Chung Chinese Acad Sci Inst Comp Technol Key Lab Comp Syst & Architecture Beijing Peoples R China Univ Minnesota Dept Comp Sci Minneapolis MN 55455 USA

ISBN: (纸本)9780769535760

Binary translation (BT) has been an important approach to migrate application software across instruction set architectures (ISAs). Some architectures, such as X86, allow misaligned data accesses (MDAs), while most modern architectures have the alignment restriction that requires data to be aligned in memory on natural boundaries. In a binary translation system, where the source ISA allows MDA and the target ISA does not, memory operations must be carefully translated to satisfy the alignment restriction. Naive translation will cause frequent misaligned data access traps to occur at runtime on the target machine, and severely slow down the migrated application. This paper evaluates different approaches in handling MDA in binary translation systems. It also proposes a new mechanism to deal with MDAs. Measurements based on SPEC CPU2000 and CPU2006 benchmark show that the proposed approach can significantly outperform existing methods.

关键词： optimization misaligned memory access binary translation

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Energy-Aware Tile Size Selection for Affine Programs on GPUs 24

Energy-Aware Tile Size Selection for Affine Programs on GPUs

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22nd ieee/acm international symposium on code generation and optimization (CGO)

作者： Jayaweera, Malith Kong, Martin Wang, Yanzhi Kaeli, David Northeastern Univ Dept Elect & Comp Engn Boston MA USA Ohio State Univ Dept Comp Sci & Engn Columbus OH USA

ISBN: (纸本)9798350395099

Loop tiling is a high-order transformation used to increase data locality and performance. While previous work has considered its application to several domains and architectures, its potential impact on energy efficiency has been largely ignored. In this work, we present an Energy-Aware Tile Size Selection Scheme (EATSS) for affine programs targeting GPUs. We automatically derive non-linear integer formulations for affine programs and use the Z3 solver to find effective tile sizes that meet architectural resource constraints, while maximizing performance and minimizing energy consumption. Our approach builds on the insight that reducing the liveness of in-cache data, together with exploiting automatic power scaling, can lead to substantial gains in performance and energy efficiency. We evaluate EATSS on NVIDIA Xavier and GA100 GPUs, and report median performance-per-Watt improvement relative to PPCG on several affine kernels. On Polybench kernels, we achieve 1.5x and 1.2x improvement and obtain up to 6.3x improvement on non-Polybench high-dimensional affine kernels.

关键词： loop tiling energy optimization affine transformations GPUs

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