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检索条件"任意字段=Proceedings of Annual IEEE/ACM International Symposium on Code Generation and Optimization"

共 546 条记录，以下是151-160 订阅

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Object Versioning for Flow-Sensitive Pointer Analysis

Object Versioning for Flow-Sensitive Pointer Analysis

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international symposium on code generation and optimization (CGO)

作者： Mohamad Barbar Yulei Sui Shiping Chen CSIRO's Data61 Australia University of Technology Sydney Australia

ISBN: (数字)9781728186139

ISBN: (纸本)9781728186146

Flow-sensitive points-to analysis provides better precision than its flow-insensitive counterpart. Traditionally performed on the control-flow graph, it incurs heavy analysis overhead. For performance, staged flow-sensitive analysis (SFS) is conducted on a pre-computed def-use (value-flow) graph where points-to sets of variables are propagated across def-use chains sparsely rather than across control-flow in the control-flow graph. SFS makes the propagation of different objects' points-to sets sparse (multiple-object sparsity), however, it suffers from redundant propagation between instructions of the same object's points-to sets (single-object sparsity). The points-to set of an object is often duplicated, resulting in redundant propagation and storage, especially in real-world heap-intensive programs. We notice that a simple graph prelabelling extension can identify much of this redundancy in a pre-analysis. With this pre-analysis, multiple nodes (instructions) in the value-flow graph can share an individual memory object's points-to set rather than each node maintaining its own points-to set for that single object. We present object versioning for flow-sensitive points-to analysis, a finer single-object sparsity technique which maintains the same precision while allowing us to avoid much of the redundancy present in propagating and storing points-to sets. Our experiments conducted on 15 open-source programs, when compared with SFS, show that our approach runs up to 26.22× faster (5.31× on average), and reduces memory usage by up to 5.46× (2.11 × on average).

关键词： Redundancy Labeling optimization Open source software

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Time Squeezing for Tiny Devices 19

Time Squeezing for Tiny Devices

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46th international symposium on Computer Architecture (ISCA) / Workshop on Computer Architecture Education (WCAE)

作者： Fan, Yuanbo Campanoni, Simone Joseph, Russ NVIDIA Santa Clara CA 95051 USA Northwestern Univ Evanston IL 60208 USA

ISBN: (纸本)9781450366694

Dynamic timing slack has emerged as a compelling opportunity for eliminating inefficiency in ultra-low power embedded systems. This slack arises when all the signals have propagated through logic paths well in advance of the clock signal. When it is properly identified, the system can exploit this unused cycle time for energy savings. In this paper, we describe compiler and architecture co-design that opens new opportunities for timing slack that are otherwise impossible. Through cross-layer optimization, we introduce novel mechanisms in the hardware and in the compiler that work together to improve the benefit of circuit-level timing speculation by effectively squeezing time during execution. This approach is particularly well-suited to tiny embedded devices. Our evaluation on a gate-level model of a complete processor shows that our co-design saves (on average) 40.5% of the original energy consumption (additional 16.5% compared to the existing clock scheduling technique) across 13 workloads while retaining transparency to developers.

关键词： code generation timing speculation timing slack

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UNIT: Unifying Tensorized Instruction Compilation

UNIT: Unifying Tensorized Instruction Compilation

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international symposium on code generation and optimization (CGO)

作者： Jian Weng Animesh Jain Jie Wang Leyuan Wang Yida Wang Tony Nowatzki Amazon Web Services USA University of California Los Angeles USA

ISBN: (数字)9781728186139

ISBN: (纸本)9781728186146

Because of the increasing demand for intensive computation in deep neural networks, researchers have developed both hardware and software mechanisms to reduce the compute and memory burden. A widely adopted approach is to use mixed precision data types. However, it is hard to benefit from mixed precision without hardware specialization because of the overhead of data casting. Recently, hardware vendors offer tensorized instructions specialized for mixed-precision tensor operations, such as Intel VNNI, Nvidia Tensor Core, and ARM DOT. These instructions involve a new computing idiom, which reduces multiple low precision elements into one high precision element. The lack of compilation techniques for this emerging idiom makes it hard to utilize these instructions. In practice, one approach is to use vendor-provided libraries for computationally-intensive kernels, but this is inflexible and prevents further optimizations. Another approach is to manually write hardware intrinsics, which is error-prone and difficult for programmers. Some prior works tried to address this problem by creating compilers for each instruction. This requires excessive efforts when it comes to many tensorized instructions. In this work, we develop a compiler framework, UNIT, to unify the compilation for tensorized instructions. The key to this approach is a unified semantics abstraction which makes the integration of new instructions easy, and the reuse of the analysis and transformations possible. Tensorized instructions from different platforms can be compiled via UNIT with moderate effort for favorable performance. Given a tensorized instruction and a tensor operation, UNIT automatically detects the applicability of the instruction, transforms the loop organization of the operation, and rewrites the loop body to take advantage of the tensorized instruction. According to our evaluation, UNIT is able to target various mainstream hardware platforms. The generated end-to-end inference model achi

关键词： Tensors Transforms US Department of Transportation Hardware Software Kernel optimization

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AxMemo: Hardware-Compiler Co-Design for Approximate code Memoization 19

AxMemo: Hardware-Compiler Co-Design for Approximate Code Mem...

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46th international symposium on Computer Architecture (ISCA) / Workshop on Computer Architecture Education (WCAE)

作者： Liu, Zhenhong Yazdanbakhsh, Amir Wang, Dong Kai Esmaeilzadeh, Hadi Kim, Nam Sung Univ Illinois Urbana IL 61801 USA Google Brain Mountain View CA USA Univ Calif San Diego San Diego CA 92103 USA

ISBN: (纸本)9781450366694

Historically, continuous improvements in general-purpose processors have fueled the economic success and growth of the IT industry. However, the diminishing benefits from transistor scaling and conventional optimization techniques necessitates moving beyond common practices. Approximate computing is one such unconventional technique that has shown promise in pushing the boundaries of general-purpose processing. This paper sets out to employ approximation for processors that are commonly used in cyberphysical domains and may become building blocks of Internet of Things. To this end, we propose AxMemo to exploit the computation redundancy that stems from data similarity in the inputs of code blocks. Such input behavior is prevalent in cyber-physical systems as they deal with real-world data that naturally harbors redundancy. Therefore, in contrast to existing memoization techniques that replace costly floating-point arithmetic operations with limited number of inputs, AxMemo focuses on memoizing blocks of code with potentially many inputs. As such, AxMemo aims to replace long sequences of instructions with a few hash and lookup operations. By reducing the number of dynamic instructions, AxMemo alleviates the von Neumann and execution overheads of passing instructions through the processor pipeline altogether. The challenge AxMemo facing is to provide low-cost hashing mechanisms that can generate rather unique signature for each multi-input combination. To address this challenge, we develop a novel use of Cyclic Redundancy Checking (CRC) to hash the inputs. To increase lookup table hit rate, AxMemo employs a two-level memoization lookup, which utilizes small dedicated SRAM and spare storage in the last level cache. These solutions enable AxMemo to efficiently memoize relatively large code regions with variable input sizes and types using the same underlying hardware. Our experiment shows that AxMemo offers 2.64xspeedup and 2.58xenergy reduction with mere 0.2% of qualit

关键词： Memoization Approximate Computing Hardware-Software Co-Design

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Formalizing Loop-carried Dependencies in Coq for High-Level Synthesis 27

Formalizing Loop-carried Dependencies in Coq for High-Level ...

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27th ieee annual international symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Faissole, Florian Constantinides, George A. Thomas, David Univ Paris Saclay INRIA F-91120 Palaiseau France CNRS LRI F-91405 Orsay France Univ Paris Sud F-91405 Orsay France Imperial Coll London London England

ISBN: (纸本)9781728111315

High-level synthesis (HLS) tools such as VivadoHLS interpret C/C++ code supplemented by proprietary optimization directives called pragmas. In order to perform loop pipelining, HLS compilers have to deal with non-trivial loop-carried data dependencies. In VivadoHLS, the dependence pragma could be used to enforce or to eliminate such dependencies, but, the behavior of this directive is only informally specified through examples. Most of the time programmers and the compiler seem to agree on what the directive means, but the accidental misuse of this pragma can lead to the silent generation of an erroneous register-transfer level (RTL) design, meaning code that previously worked may break with newer more aggressively optimised releases of the compiler. We use the Coq proof assistant to formally specify and verify the behavior of the VivadoHLS dependence pragma. We first embed the syntax and the semantics of a tiny imperative language Imp in Coq and specify a conformance relation between an Imp program and a dependence pragma based on data-flow transformations. We then implement semi-automated methods to formally verify such conformance relations for non-nested loop bodies.

关键词： Tools Pipeline processing Hardware optimization Program processors Semantics Field programmable gate arrays

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Persist Level Parallelism: Streamlining Integrity Tree Updates for Secure Persistent Memory

Persist Level Parallelism: Streamlining Integrity Tree Updat...

引用

ieee/acm international symposium on Microarchitecture (MICRO)

作者： Alexander Freij Shougang Yuan Huiyang Zhou Yan Solihin North Carolina State University University of Central Florida

ISBN: (数字)9781728173832

ISBN: (纸本)9781728173849

Emerging non-volatile main memory (NVMM) is rapidly being integrated into computer systems. However, NVMM is vulnerable to potential data remanence and replay attacks. Memory encryption and integrity verification have been introduced to protect against such data integrity attacks. However, they are not compatible with a growing use of NVMM for providing crash recoverable persistent memory. Recent works on secure NVMM pointed out the need for data and its metadata, including the counter, the message authentication code (MAC), and the Bonsai Merkle Tree (BMT) to be persisted atomically. However, memory persistency models have been overlooked for secure NVMM, which is essential for crash recoverability. In this work, we analyze the invariants that need to be ensured in order to support crash recovery for secure NVMM. We highlight that by not adhering to these invariants, prior research has substantially under-estimated the cost of BMT persistence. We propose several optimization techniques to reduce the overhead of atomically persisting updates to BMTs. The optimizations proposed explore the use of pipelining, out-of-order updates, and update coalescing while conforming to strict or epoch persistency models, respectively. We evaluate our work and show that our proposed optimizations significantly reduce the performance overhead of secure crash-recoverable NVMM from 720% to just 20%.

关键词： Out of order Nonvolatile memory Computational modeling Metadata Computer crashes Encryption optimization

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MGPUSim: Enabling Multi-GPU Performance Modeling and optimization 19

MGPUSim: Enabling Multi-GPU Performance Modeling and Optimiz...

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46th international symposium on Computer Architecture (ISCA)

作者： Sun, Yifan Baruah, Trinayan Mojumder, Saiful A. Dong, Shi Gong, Xiang Treadway, Shane Bao, Yuhui Hance, Spencer McCardwell, Carter Zhao, Vincent Barclay, Harrison Ziabari, Amir Kavyan Chen, Zhongliang Ubal, Rafael Abelian, Jose L. Kim, John Joshi, Ajay Kaeli, David Northeastern Univ Boston MA 02115 USA Boston Univ Boston MA 02215 USA AMD Boston MA USA Univ Catolica San Antonio Murcia Murcia Spain Korea Adv Inst Sci & Technol Daejeon South Korea

ISBN: (纸本)9781450366694

The rapidly growing popularity and scale of data-parallel workloads demand a corresponding increase in raw computational power of Graphics Processing Units (GPUs). As single-GPU platforms struggle to satisfy these performance demands, multi-GPU platforms have started to dominate the high-performance computing world. The advent of such systems raises a number of design challenges, including the GPU microarchitecture, multi-GPU interconnect fabric, runtime libraries, and associated programming models. The research community currently lacks a publicly available and comprehensive multi-GPU simulation framework to evaluate next-generation multi-GPU system designs. In this work, we present MGPUSim, a cycle-accurate, extensively validated, multi-GPU simulator, based on AMD's Graphics Core Next 3 (GCN3) instruction set architecture. MGPUSim comes with in-built support for multi-threaded execution to enable fast, parallelized, and accurate simulation. In terms of performance accuracy, MGPUSim *** by only 5.5% on average from the actual GPU hardware. We also achieve a 3.5x and a 2.5x average speedup running functional emulation and detailed timing simulation, respectively, on a 4-core CPU, while delivering the same accuracy as serial simulation. We illustrate the flexibility and capability of the simulator through two concrete design studies. In ***, we propose the Locality API, an API extension that allows the GPU programmer to both avoid the complexity of multi-GPU programming, while precisely controlling data placement in the multi-GPU memory. In the second design study, we propose Progressive Page SplittingMigration (PASI), a customized multi-GPU memory management system enabling the hardware to progressively improve data placement. For a discrete 4-GPU system, we observe that the Locality API can speed up the system by 1.6x (geometric mean), and PASI can improve the system performance by 2.6x (geometric mean) across all benchmarks, compared to a *** 4-GPU platf

关键词： multi-GPU systems simulation memory management

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SGXELIDE: Enabling Enclave code Secrecy via Self-Modification 2018

SGXELIDE: Enabling Enclave Code Secrecy via Self-Modificatio...

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16th international symposium on code generation and optimization (CGO)

作者： Bauman, Erick Wang, Huibo Zhang, Mingwei Lin, Zhiqiang Univ Texas Dallas Richardson TX 75083 USA Intel Labs Hillsboro OR USA

ISBN: (纸本)9781450356176

Intel SGX provides a secure enclave in which code and data are hidden from the outside world, including privileged code such as the OS or hypervisor. However, by default, enclave code prior to initialization can be disassembled and therefore no secrets can be embedded in the binary. This is a problem for developers wishing to protect code secrets. This paper introduces SGXELIDE, a nearly-transparent framework that enables enclave code confidentiality. The key idea is to treat program code as data and dynamically restore secrets after an enclave is initialized. SGXELIDE can be integrated into any enclave, providing a mechanism to securely decrypt or deliver the secret code with the assistance of a developer-controlled trusted remote party. We have implemented SGXELIDE atop a recently released version of the Linux SGX SDK, and our evaluation with a number of programs shows that SGXELIDE can be used to protect the code secrecy of practical applications with no overhead after enclave initialization.

关键词： SGX self-modifying code code obfuscation

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CollectionSwitch: A Framework for Efficient and Dynamic Collection Selection 2018

CollectionSwitch: A Framework for Efficient and Dynamic Coll...

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16th international symposium on code generation and optimization (CGO)

作者： Costa, Diego Andrzejak, Artur Heidelberg Univ Inst Comp Sci Heidelberg Germany

ISBN: (纸本)9781450356176

Selecting collection data structures for a given application is a crucial aspect of the software development. Inefficient usage of collections has been credited as a major cause of performance bloat in applications written in Java, C++ and C#. Furthermore, a single implementation might not be optimal throughout the entire program execution. This demands an adaptive solution that adjusts at runtime the collection implementations to varying workloads. We present CollectionSwitch, an application-level framework for efficient collection adaptation. It selects at runtime collection implementations in order to optimize the execution and memory performance of an application. Unlike previous works, we use workload data on the level of collection allocation sites to guide the optimization process. Our framework identifies allocation sites which instantiate suboptimal collection variants, and selects optimized variants for future instantiations. As a further contribution we propose adaptive collection implementations which switch their underlying data structures according to the size of the collection. We implement this framework in Java, and demonstrate the improvements in terms of time and memory behavior across a range of benchmarks. To our knowledge, it is the first approach which is capable of runtime performance optimization of Java collections with very low overhead.

关键词： data structure performance optimization adaptive algorithms

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CUDAAdvisor: LLVM-Based Runtime Profiling for Modern GPUs 2018

CUDAAdvisor: LLVM-Based Runtime Profiling for Modern GPUs

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16th international symposium on code generation and optimization (CGO)

作者： Shen, Du Song, Shuaiwen Leon Li, Ang Liu, Xu Coll William & Mary Williamsburg VA 23187 USA Pacific Northwest Natl Lab Richland WA 99352 USA

ISBN: (纸本)9781450356176

General-purpose GPUs have been widely utilized to accelerate parallel applications. Given a relatively complex programming model and fast architecture evolution, producing efficient GPU code is nontrivial. A variety of simulation and profiling tools have been developed to aid GPU application optimization and architecture design. However, existing tools are either limited by insufficient insights or lacking in support across different GPU architectures, runtime and driver versions. This paper presents CUDAAdvisor, a profiling framework to guide code optimization in modern NVIDIA GPUs. CUDAAdvisor performs various fine-grained analyses based on the profiling results from GPU kernels, such as memory-level analysis (e.g., reuse distance and memory divergence), control flow analysis (e.g., branch divergence) and code-/data-centric debugging. Unlike prior tools, CUDAAdvisor supports GPU profiling across different CUDA versions and architectures, including CUDA 8.0 and Pascal architecture. We demonstrate several case studies that derive significant insights to guide GPU code optimization for performance improvement.

关键词： GPU LLVM Profiling optimization

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